CN116246954A - Method for preparing electronic circuit with resolution of 2nm - Google Patents
Method for preparing electronic circuit with resolution of 2nm Download PDFInfo
- Publication number
- CN116246954A CN116246954A CN202211562991.3A CN202211562991A CN116246954A CN 116246954 A CN116246954 A CN 116246954A CN 202211562991 A CN202211562991 A CN 202211562991A CN 116246954 A CN116246954 A CN 116246954A
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- China
- Prior art keywords
- paper folding
- electronic circuit
- circuit diagram
- resolution
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000010586 diagram Methods 0.000 claims abstract description 23
- 239000010931 gold Substances 0.000 claims abstract description 23
- 229910052737 gold Inorganic materials 0.000 claims abstract description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000002105 nanoparticle Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 11
- ZEMPKEQAKRGZGQ-AAKVHIHISA-N 2,3-bis[[(z)-12-hydroxyoctadec-9-enoyl]oxy]propyl (z)-12-hydroxyoctadec-9-enoate Chemical compound CCCCCCC(O)C\C=C/CCCCCCCC(=O)OCC(OC(=O)CCCCCCC\C=C/CC(O)CCCCCC)COC(=O)CCCCCCC\C=C/CC(O)CCCCCC ZEMPKEQAKRGZGQ-AAKVHIHISA-N 0.000 claims description 4
- 125000003396 thiol group Chemical class [H]S* 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 claims 1
- 229910001425 magnesium ion Inorganic materials 0.000 claims 1
- 238000004381 surface treatment Methods 0.000 abstract description 2
- 238000001900 extreme ultraviolet lithography Methods 0.000 abstract 1
- 108020004414 DNA Proteins 0.000 description 11
- 238000002360 preparation method Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 3
- 238000001962 electrophoresis Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000012521 purified sample Substances 0.000 description 2
- 102000053602 DNA Human genes 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000005580 one pot reaction Methods 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- SFIHWLKHBCDNCE-UHFFFAOYSA-N uranyl formate Chemical compound OC=O.OC=O.O=[U]=O SFIHWLKHBCDNCE-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for preparing an electronic circuit with resolution of 2nm, which comprises the following steps: firstly, designing a required electronic circuit diagram, folding a long-chain DNA back and forth into a required electronic circuit diagram frame based on a paper folding principle, designing a proper connecting site, and introducing a large number of short chains (staple chains) to fix the frame. All strands were mixed and annealed to form a DNA origami pattern. The paper folding structure is influenced by the length of a long chain, only patterns with the size of hundreds of nanometers can be formed, and macroscopic patterns are difficult to directly form. By depositing gold nano particles on a silicon wafer, carrying out surface treatment to form thiol gold bonds, complementing short-chain bases designed in advance on the edges of the patterns, and fixing each DNA pattern on a specific position of the silicon wafer. The different paper folding patterns are connected with each other to form a complete macroscopic electronic circuit diagram. Because the diameter of the DNA spiral is about 2 nanometers, the drawn electronic circuit diagram ensures the macroscopic characteristics of the DNA spiral and realizes the minimum resolution of 2 nanometers. The advantages are that: compared with the conventional extreme ultraviolet lithography and other methods, the method has low cost and high resolution, and provides a feasible method for the development of electronic information.
Description
Technical Field
The invention relates to a preparation method of a high-resolution circuit diagram, in particular to a preparation method of a macroscopic circuit diagram with resolution of about 2 nanometers.
Background
The chip manufacturing is an important support for technological development, and along with the development of high integration of electronic circuits, it is particularly important to manufacture a circuit template with small volume and high resolution, but along with the gradual increase of etching precision, the conventional etching technology of traditional photoetching such as ultraviolet photoetching, extreme ultraviolet photoetching and the like is affected by various factors such as resolution limit, high manufacturing cost and the like to prevent the development of the circuit template, so that the development of the manufacturing technology with low cost and high resolution is particularly important.
In recent years, with the development of DNA technology, a bottom-up manufacturing technology, DNA paper folding technology, is known gradually, and by folding a long DNA strand and fixing it in cooperation with a short strand, arbitrary patterns of nanometer resolution, including two-dimensional and three-dimensional patterns, can be constructed.
DNA origami is typically only a few hundred nano-structures due to the long chain length. This feature prevents its specific application and development. The gold nano particles are introduced to carry out surface treatment on the gold nano particles to connect a plurality of small paper folding patterns, so that a macroscopic electronic circuit diagram is formed, and the minimum resolution of the gold nano particles can reach 2 nanometers.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for preparing an electronic circuit with resolution of 2nm, which is based on the paper folding principle to construct a required electronic circuit diagram, and the minimum resolution of 2nm can be realized by the drawn electronic circuit diagram because the diameter of a DNA spiral is about 2 nm. However, the characteristic that each paper folding structure is about hundreds of nanometers is limited to practical application due to the influence of the long chain length of the paper folding structure, and the gold nanoparticles are deposited on the surface of the silicon wafer, so that the gold nanoparticles can connect different paper folding structures to form a complete electronic circuit diagram. The invention not only ensures the high resolution of the circuit, but also ensures the macroscopic application of the circuit, and solves the problems of high preparation cost, harsh conditions, low resolution and the like of the conventional preparation.
The technical scheme adopted for solving the technical problems is as follows: a method for preparing an electronic circuit with a resolution of 2nm, characterized in that a circuit diagram with a resolution of about 2nm on a macroscopic scale is constructed by a DNA origami method; the preparation method comprises the following steps:
step one: drawing the required electronic circuit diagram.
Step two: and (5) designing a paper folding frame. According to the design of the pattern, long chains (m 13p18 is about 900 nt) are folded back and forth to form a bracket structure, proper connecting sites are designed, and a large number of short chains (staple chains) are introduced to fix the frame. A short chain connecting chain complementary with the thiol gold bond is designed at the end point of the paper folding frame for later use.
And forming a paper folding pattern. The designed long chain and all short chains (including the connecting chain) were mixed in a molar ratio (1:10) and annealed. The annealing temperature is gradually reduced from 95 ℃ to 20 ℃ and the total time is less than 2 hours.
Step four: and (5) gold nanoparticle deposition. Depositing gold nanoparticles on specific positions on the surface of the silicon substrate, and treating the surfaces of the gold nanoparticles to form thiol gold bonds.
Step five: the paper folding structure is connected with the gold nano particles. And (3) dripping the annealed solution containing the paper folding structure on the surface of the silicon wafer, complementing a connecting chain at the end point of the paper folding pattern with a thiol gold bond, connecting and fixing the paper folding pattern at a specific position, and sequentially connecting the paper folding patterns to form a complete electronic circuit diagram.
Compared with the prior art, the invention has the advantages that:
1) The experimental conditions are simple, and extreme experimental conditions are not needed;
2) The cost is low, and the DNA chain synthesis is simple;
3) The resolution is high, and the minimum resolution can reach 2 nanometers.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a partial circuit diagram of the design of the present invention;
FIG. 2 is a partial DNA origami pattern forming process according to the present invention;
FIG. 3 is a schematic diagram of the connection of one end of a DNA pattern designed in the invention with gold nanoparticles;
Detailed Description
The present invention will be described in further detail with reference to the drawings and the specific embodiments, which are not intended to limit the scope of the claims.
Implementation example 1:
step one: a geometric model of the DNA structure is created that will approximate the desired shape.
Step two: folding a long DNA chain of a long M13p18 phage according to the circuit diagram of the first step to form a framework structure, and designing a large number of short chain connection points based on the base pairing principle to fix the framework structure so as to avoid deformation and distortion of the pattern.
Step three: the long chain and all the short chains are mixed and annealed in one pot to form the required pattern.
Step four: and (3) carrying out electrophoresis purification on the annealed pattern to obtain a relevant electrophoresis strip.
Step five: the purified bands were cut and centrifuged for later use.
Step five: 3ul of the purified sample was taken for AFM imaging.
Step six: the purified sample was taken in 5ul, stained with uranyl formate for 1 min, and allowed to stand for 5 min for TEM imaging.
Claims (6)
1. A method of making an electronic circuit having a resolution of 2nm, comprising the steps of:
step one: drawing the required electronic circuit diagram.
Step two: and (5) designing a paper folding frame. According to the design of the pattern, long chains (m 13p18 is about 900 nt) are folded back and forth to form a bracket structure, proper connecting sites are designed, and a large number of short chains (staple chains) are introduced to fix the frame. A short chain connecting chain complementary with the thiol gold bond is designed at the end point of the paper folding frame for later use.
Step three: and forming a paper folding pattern. The designed long chain and all short chains (including the connecting chain) were mixed in a molar ratio (1:10) and annealed. The annealing temperature is gradually reduced from 95 ℃ to 20 ℃ and the total time is less than 2 hours.
Step four: and (5) gold nanoparticle deposition. Depositing gold nanoparticles on specific positions on the surface of the silicon substrate, and treating the surfaces of the gold nanoparticles to form thiol gold bonds.
Step five: the paper folding structure is connected with the gold nano particles. And (3) dripping the annealed solution containing the paper folding structure on the surface of the silicon wafer, complementing a connecting chain at the end point of the paper folding pattern with a thiol gold bond, connecting and fixing the paper folding pattern at a specific position, and sequentially connecting the paper folding patterns to form a complete electronic circuit diagram.
2. A method of manufacturing an electronic circuit with a resolution of 2nm according to claim 1, characterized in that: the drawn circuit diagram comprises a total circuit diagram and a local circuit diagram corresponding to each paper folding, and is limited by the long chain size of the paper folding, and only the local circuit diagram can be formed in each paper folding pattern.
3. A method of manufacturing an electronic circuit with a resolution of 2nm according to claim 1, characterized in that: folding the long chain to form a framework, such that it comprises one of the two chains in each helix; the progression of the stent from one spiral to another creates an additional set of intersections. The connecting strand at the end point has a specific sequence and can only be complementary to the specific sequence.
4. A method of manufacturing an electronic circuit with a resolution of 2nm according to claim 1, characterized in that: the magnesium ion concentration plays a key role in structure formation in the annealing process, and different structures correspond to different concentrations.
5. A method of manufacturing an electronic circuit with a resolution of 2nm according to claim 1, characterized in that: the spacing between the deposited gold nano particles is consistent with the size of a paper folding pattern formed in each step, and the thiolated gold nano particles on the surface of the silicon wafer fix the paper folding structure at a preset position on the surface of the silicon wafer through the identification and connection of the gold nano particles with a specific connecting chain.
6. A method of manufacturing an electronic circuit with a resolution of 2nm according to claim 1, characterized in that: each gold nanoparticle surface connecting chain has specificity and can only be connected with the connecting chain at the end point of the preset paper folding structure, and adjacent DNA paper folding patterns are connected through the shared gold nanoparticles to form a complete circuit diagram.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211562991.3A CN116246954A (en) | 2022-12-07 | 2022-12-07 | Method for preparing electronic circuit with resolution of 2nm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211562991.3A CN116246954A (en) | 2022-12-07 | 2022-12-07 | Method for preparing electronic circuit with resolution of 2nm |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116246954A true CN116246954A (en) | 2023-06-09 |
Family
ID=86633845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211562991.3A Pending CN116246954A (en) | 2022-12-07 | 2022-12-07 | Method for preparing electronic circuit with resolution of 2nm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116246954A (en) |
-
2022
- 2022-12-07 CN CN202211562991.3A patent/CN116246954A/en active Pending
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