CN116245067A - OPC method for optimizing electrical parameters of transistors with different sizes - Google Patents

OPC method for optimizing electrical parameters of transistors with different sizes Download PDF

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Publication number
CN116245067A
CN116245067A CN202310107636.5A CN202310107636A CN116245067A CN 116245067 A CN116245067 A CN 116245067A CN 202310107636 A CN202310107636 A CN 202310107636A CN 116245067 A CN116245067 A CN 116245067A
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China
Prior art keywords
polysilicon
transistors
polycrystalline silicon
layout
electrical parameters
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Pending
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CN202310107636.5A
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Chinese (zh)
Inventor
朱辰雨
袁洋
李磊
朱作华
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Priority to CN202310107636.5A priority Critical patent/CN116245067A/en
Publication of CN116245067A publication Critical patent/CN116245067A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The invention provides an OPC method for optimizing electrical parameters of transistors with different sizes, and provides polycrystalline silicon CD and different widths of an active region corresponding to the polycrystalline silicon CD; collecting process values of the polycrystalline silicon CD corresponding to different widths of the active region; providing a layout graph formed by the same polysilicon CD which comprises active areas with different widths and corresponds to the active areas with different widths respectively; segmenting the layout graph; grouping the active regions according to different widths of the active regions; calculating deviation between the polysilicon CD corresponding to the width of each active region and the process value of the polysilicon CD; correcting the polysilicon CD according to the grouping and the deviation; the layout pattern is checked to conform to the design rules of the layout. The method can detect the change of the polysilicon CD under different active region widths, reduce the electrical deviation brought in the actual process and improve the performance of the device.

Description

OPC method for optimizing electrical parameters of transistors with different sizes
Technical Field
The invention relates to the technical field of semiconductors, in particular to an OPC method for optimizing electrical parameters of transistors with different sizes.
Background
The minimum design size of the 55nm logic process gate width (namely the device channel length) is 54nm, the change of the polysilicon CD (Poly CD) has a great influence on the electrical parameters of the transistor, and according to the FEM result, the change amplitude of the MOS tube Idsat of W9L0.054 along with the Poly CD is RVTN-11 uA/um and RVTP-5 uA/um respectively;
the largest difference between the actual poly etching CD made on different active area widths (AA Width) is found in the 55LP platform MPW and the mass product, and the largest difference between the device CD of different AA Width in the same shot is about 4.5nm, and the difference causes the electrical deviation of the device. Since the CMOS design structure is fixed, this difference cannot be corrected from the design, and as the nodes continue to decrease, the electrical performance and circuit operating efficiency of transistors of more dimensions in the chip area will be affected;
the existing OPC correction method controls the appearance of the photoresist to fluctuate in a smaller range through the pitch, but the difference still exists when the measurement positions have the same line=0.054 and pitch=0.252, namely, the photoresist cannot be corrected through the pitch;
the test key (testkey) used to check OPC on the existing mask only considers the rule and process bias (bias) of the poly-on-layer, and does not monitor poly CD variations on different AA widths.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an OPC method for optimizing electrical parameters of transistors with different dimensions, which is used for solving the problem that the prior art cannot monitor the variation of the polysilicon CD corresponding to different widths of the active area.
To achieve the above and other related objects, the present invention provides an OPC method for optimizing electrical parameters of transistors of different sizes, at least comprising:
step one, providing polycrystalline silicon CD and different widths of an active area corresponding to the polycrystalline silicon CD; collecting process values of the polysilicon CD corresponding to different widths of the active region;
step two, providing a layout graph formed by the same polycrystalline silicon CD which comprises the active areas with different widths and the active areas with different widths respectively;
step three, segmenting the layout graph;
step four, grouping the active areas according to different widths of the active areas;
calculating deviation between the polysilicon CD corresponding to the width of each active region and the technological value of the polysilicon CD; correcting the polysilicon CD according to the grouping and the deviation;
and step six, checking the layout graph to accord with the design rule of the layout.
Preferably, the polysilicon CD in the first step is a critical dimension design value of the polysilicon in the transistor process.
Preferably, the process value of the polysilicon CD in the first step is the actual CD of the polysilicon formed after etching the polysilicon layer in the transistor process of different widths of the active area corresponding to the polysilicon CD.
Preferably, the layout pattern in the second step includes an active region pattern and a polysilicon pattern, where the active region pattern and the polysilicon pattern are respectively located in different layers.
Preferably, in the third aspect, segmenting the layout graph includes: and respectively segmenting the long side and the short side of the polycrystalline silicon graph.
Preferably, in the third aspect, segmenting the layout graph includes: and respectively segmenting the long side and the short side of the active region graph.
Preferably, the method for correcting the polysilicon CD in the fifth step includes: and expanding the polycrystalline silicon CD.
Preferably, the method for correcting the polysilicon CD in the fifth step includes: and shrinking the polycrystalline silicon CD.
Preferably, in the fifth step, the polysilicon CD is corrected based on the segmented layout pattern.
Preferably, in the fifth step, the polysilicon CD is corrected based on the segmented layout pattern.
As described above, the OPC method for optimizing electrical parameters of transistors of different sizes of the present invention has the following advantages: the method can detect the change of the polysilicon CD under different active region widths, reduce the electrical deviation brought in the actual process and improve the performance of the device.
Drawings
Fig. 1 to 3 are schematic diagrams of layout structures of the same polysilicon CD corresponding to different widths of the active regions in the present invention;
FIG. 4 is a flow chart of an OPC method for optimizing electrical parameters of transistors of different sizes in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides an OPC method for optimizing electrical parameters of transistors with different sizes, as shown in FIG. 4, FIG. 4 shows a flow chart of the OPC method for optimizing electrical parameters of transistors with different sizes, the method at least comprises the following steps:
step one, providing polycrystalline silicon CD and different widths of an active area corresponding to the polycrystalline silicon CD; collecting process values of the polysilicon CD corresponding to different widths of the active region;
in the present invention, the CD of the polysilicon in the first step of the present embodiment is a critical dimension design value of the polysilicon in the transistor process.
In the first step of the present embodiment, the process value of the polysilicon CD is the actual CD of the polysilicon formed after etching the polysilicon layer in the transistor process with different widths of the active area corresponding to the polysilicon CD.
Providing polycrystalline silicon CD and different widths of an active area corresponding to the polycrystalline silicon CD; collecting process values of the polysilicon CD corresponding to different widths of the active region; the polysilicon CD in this embodiment is a critical dimension design value of polysilicon in the transistor process. The process value of the polysilicon CD is the actual CD of the polysilicon formed after the polysilicon layer is etched in the transistor process of different widths of the active area corresponding to the polysilicon CD.
Step two, providing a layout graph formed by the same polycrystalline silicon CD which comprises the active areas with different widths and the active areas with different widths respectively; as shown in fig. 1 to 3, fig. 1 to 3 are schematic layout structures of the same polysilicon CD corresponding to different widths of the active regions in the present invention. Wherein the CD of the polysilicon is the same in fig. 1-3 and the width of the Active Area (AA) is different from each other in fig. 1-3.
In the second step of this embodiment, the layout pattern further includes an active region pattern and a polysilicon pattern, where the active region pattern and the polysilicon pattern are respectively located in different layers. In fig. 1, a polysilicon pattern 01 and an active region pattern 02 are combined to form a layout pattern, and in other embodiments, the layout pattern may also include other patterns. In fig. 2, a polysilicon pattern 01 and an active region pattern 02 form another layout pattern; in other embodiments, the layout pattern may also include other patterns. The layout pattern in fig. 3 is different from the layout pattern in fig. 1 and 2, and is composed of a polysilicon pattern 01 and an active region pattern 02; in other embodiments, the layout pattern may also include other patterns. Thus, fig. 1-3 are each three different layout patterns, with the polysilicon pattern on one layer and the active region pattern on the other layer.
Step three, segmenting the layout graph;
the invention further provides a step three of the embodiment, wherein the step of segmenting the layout graph comprises the following steps: and respectively segmenting the long side and the short side of the polycrystalline silicon graph.
The invention further provides a step three of the embodiment, wherein the step of segmenting the layout graph comprises the following steps: and respectively segmenting the long side and the short side of the active region graph. That is, the modification of OPC requires segmentation of layout patterns, and segmentation of each side for different patterns. The segmented layout pattern is not shown in fig. 1 to 3. And then, the contraction or expansion of each edge can be carried out according to the segmented layout graph.
Step four, grouping the active areas according to different widths of the active areas; a plurality of different groups is obtained.
Calculating deviation between the polysilicon CD corresponding to the width of each active region and the technological value of the polysilicon CD; correcting the polysilicon CD according to the grouping and the deviation; that is, the CD of the polysilicon with the width of each active region combined with the active region in each layout pattern is calculated, and in the actual process, the CD of the polysilicon will change after etching, that is, the CD of the polysilicon with the changed etching is the process value, that is, the CD of the polysilicon obtained in the actual process.
The method for correcting the polysilicon CD in the fifth step of the present embodiment further includes: and expanding the polycrystalline silicon CD.
The method for correcting the polysilicon CD in the fifth step of the present embodiment further includes: and shrinking the polycrystalline silicon CD. That is, the modification of the polysilicon CD in the present invention includes shrinking or expanding the polysilicon CD.
In the fifth step of the present embodiment, the polysilicon CD is further modified based on the segmented layout pattern.
And step six, checking the layout graph to accord with the design rule of the layout.
The present invention further provides that in step six of the present embodiment, the checking of the layout pattern includes checking the polysilicon CD corrected in the layout pattern.
The method of the embodiment further comprises a step seven of performing photoetching simulation if the design rule conforming to the layout is checked; obtaining a final photomask pattern; if the inspection does not accord with the design rule, returning to the step five until the inspection accords with the design rule, and then carrying out photoetching simulation to obtain the final photomask pattern.
The method of the invention collects more deviation data, from which rules are established for the transistors: taking the influence of the Width (AA Width) of the lower active region into consideration, performing special correction treatment on a device with larger size according to the polycrystalline silicon CD (poly CD) and WAT sensitivity (WAT sensitivity), for example, correcting the polycrystalline silicon CD of an NMOS tube with AA width=9 by 3nm, reducing RVTN Idsat by about 30uA/cm, increasing Vtlin and simultaneously reducing Ioff; an OPC check model under the minimum polysilicon CD is designed and the actual polysilicon CD under the same pitch is monitored.
In summary, the method of the invention can detect the variation of the polysilicon CD under different active region widths, reduce the electrical deviation brought in the actual process and improve the device performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (11)

1. An OPC method for optimizing electrical parameters of transistors of different sizes, comprising at least:
step one, providing polycrystalline silicon CD and different widths of an active area corresponding to the polycrystalline silicon CD; collecting process values of the polysilicon CD corresponding to different widths of the active region;
step two, providing a layout graph formed by the same polycrystalline silicon CD which comprises the active areas with different widths and the active areas with different widths respectively;
step three, segmenting the layout graph;
step four, grouping the active areas according to different widths of the active areas;
calculating deviation between the polysilicon CD corresponding to the width of each active region and the technological value of the polysilicon CD;
correcting the polysilicon CD according to the grouping and the deviation;
and step six, checking the layout graph to accord with the design rule of the layout.
2. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: the polysilicon CD in the first step is a critical dimension design value of the polysilicon in the transistor process.
3. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: the process value of the polysilicon CD in the first step is the actual CD of the polysilicon formed after the polysilicon layer is etched in the transistor process of different widths of the active area corresponding to the polysilicon CD.
4. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: the layout pattern in the second step comprises an active area pattern and a polysilicon pattern, wherein the active area pattern and the polysilicon pattern are respectively positioned on different layers.
5. The OPC method of claim 4 wherein the electrical parameters of the different sized transistors are optimized by: the step three, the step of segmenting the layout graph comprises the following steps: and respectively segmenting the long side and the short side of the polycrystalline silicon graph.
6. The OPC method of claim 4 wherein the electrical parameters of the different sized transistors are optimized by: the step three, the step of segmenting the layout graph comprises the following steps: and respectively segmenting the long side and the short side of the active region graph.
7. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: the method for correcting the polycrystalline silicon CD in the fifth step comprises the following steps: and expanding the polycrystalline silicon CD.
8. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: the method for correcting the polycrystalline silicon CD in the fifth step comprises the following steps: and shrinking the polycrystalline silicon CD.
9. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: and fifthly, correcting the polycrystalline silicon CD based on the segmented layout graph.
10. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: and step six, checking the layout graph comprises checking the corrected polycrystalline silicon CD in the layout graph.
11. The OPC method of claim 1 wherein the electrical parameters of the transistors of different sizes are optimized by: the method further comprises a step seven of performing photoetching simulation if the design rule conforming to the layout is checked; obtaining a final photomask pattern; if the inspection does not accord with the design rule, returning to the step five until the inspection accords with the design rule, and then carrying out photoetching simulation to obtain the final photomask pattern.
CN202310107636.5A 2023-02-13 2023-02-13 OPC method for optimizing electrical parameters of transistors with different sizes Pending CN116245067A (en)

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Application Number Priority Date Filing Date Title
CN202310107636.5A CN116245067A (en) 2023-02-13 2023-02-13 OPC method for optimizing electrical parameters of transistors with different sizes

Publications (1)

Publication Number Publication Date
CN116245067A true CN116245067A (en) 2023-06-09

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