CN116235130A - Driver circuitry - Google Patents

Driver circuitry Download PDF

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Publication number
CN116235130A
CN116235130A CN202180064066.5A CN202180064066A CN116235130A CN 116235130 A CN116235130 A CN 116235130A CN 202180064066 A CN202180064066 A CN 202180064066A CN 116235130 A CN116235130 A CN 116235130A
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CN
China
Prior art keywords
circuitry
signal
output
supply voltage
controller
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Pending
Application number
CN202180064066.5A
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Chinese (zh)
Inventor
R·C·摩根
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Cirrus Logic International Semiconductor Ltd
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Cirrus Logic International Semiconductor Ltd
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Priority claimed from GB2102561.4A external-priority patent/GB2597818B/en
Application filed by Cirrus Logic International Semiconductor Ltd filed Critical Cirrus Logic International Semiconductor Ltd
Publication of CN116235130A publication Critical patent/CN116235130A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16—Sound input; Sound output
    • G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3212—Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/016—Input arrangements with force or tactile feedback as computer generated output to the user
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
    • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
    • H02P25/032—Reciprocating, oscillating or vibrating motors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
    • H02P27/14—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation with three or more levels of voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
    • H02J7/0048—Detection of remaining charge capacity or state of charge [SOC]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0047—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
    • H02J7/005—Detection of state of health [SOH]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Human Computer Interaction (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • General Health & Medical Sciences (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present disclosure relates to a circuit system, comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage of the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.

Description

Driver circuitry
Technical Field
The following description sets forth exemplary embodiments according to the present disclosure. Additional exemplary embodiments and implementations will be apparent to those of ordinary skill in the art. In addition, one of ordinary skill in the art will recognize that various equivalent techniques may be applied in place of or in combination with the embodiments discussed below, and that all such equivalent techniques should be considered to be encompassed by the present disclosure.
Exemplary embodiments in the present disclosure relate to analog and/or digital circuitry for controlling or driving transducers and/or electronic circuitry.
Background
One way to control the speed of a transducer, such as a DC motor, for example, is to adjust the supply voltage applied to the motor. Thus, without any load on the motor, at a higher supply voltage the speed of the motor is higher, and at a lower supply voltage the speed of the motor is lower. Controlling speed in this manner, however, limits the power and/or torque of the motor and makes the speed of the motor sensitive to the load on the motor. In addition, since the motor speed depends on the supply voltage, any change in the supply voltage (e.g., a decrease in the supply voltage due to, for example, a discharge of a battery providing the supply voltage) will also affect the motor speed.
An alternative method of controlling the speed of a transducer, such as a DC motor, for example, is to use a digital signal, such as a Pulse Width Modulated (PWM) or Pulse Duration Modulated (PDM) drive signal, for example, to control the speed of the DC motor. The speed of the motor is controlled by varying the duty cycle of the digital drive signal output to the motor by the digital driver circuitry such that the motor speed is effectively controlled by the RMS (root mean square) value of the digital drive signal. In an open loop motor control system in which the supply voltage varies (e.g., in which the supply voltage to the digital driver circuitry is provided by a power source such as a battery), the speed is a function of both the duty cycle of the digital drive signal and the supply voltage, since as the supply voltage varies, the RMS value of the digital drive signal varies accordingly.
In another exemplary embodiment, one way to control the power efficiency of a transducer and driver arrangement, such as an audio speaker system, for example, is to adjust the supply voltage applied to the audio speaker driver. The audio speaker driver may drive the audio speaker using analog drive signals and circuitry (e.g., such as those associated with class G and/or class H amplifiers), as will be appreciated by one of ordinary skill in the art. In such an analog situation, a larger input signal would require a larger supply voltage in order to avoid clipping of the output signal, but would require more energy, and a smaller input signal would require a smaller supply voltage, thereby saving energy and making the transducer and driver arrangement more power efficient.
Furthermore, transducers like motor drivers, audio drivers and haptic drivers, for example, may require abrupt and potentially large transient currents from batteries such as lithium ion batteries. The independent and cumulative effects of these transient current demands may be, for example: premature system power down due to the battery supply level instantaneously dropping below its power down threshold; and/or spoofing circuitry and other components and/or systems of the host device incorporating the circuitry to consider the battery as having reached its end-of-charge threshold when the battery has not actually reached its end-of-charge threshold. In addition, transient demands from one transducer may cause battery supply transients to drop, with the result that output power supplied to the other transducer may be affected. Furthermore, the cumulative power consumption of these concurrent current demands may result in undesirable thermal heating of the circuitry and/or other components or systems of the host device incorporating the circuitry.
To alleviate the problem of motor speed depending on the supply voltage level and the duty cycle of the digital drive signal, the supply voltage to the digital drive circuitry may be regulated by voltage regulator circuitry, such as DC-DC converter circuitry, low Dropout (LDO) regulator circuitry, and the like. However, the use of such additional voltage regulator circuitry increases the physical size, component count, and cost of the system, for example, for controlling the DC motor, and may also reduce the power efficiency of the system due to inefficiencies in the additional voltage regulator circuitry and the necessary margin requirements of the voltage regulator circuitry.
Digital drive signals may also be used to drive other transducers, such as LEDs (light emitting diodes), tactile transducers, resonant actuators, etc., and similar problems as those described above may occur when digital and/or analog drive signals are used in such applications.
Disclosure of Invention
According to a first aspect, the present invention provides circuitry comprising:
digital circuitry configured to generate a digital output signal; and
monitoring circuitry configured to monitor a supply voltage of the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.
The digital circuitry is operable to control a parameter of the digital output signal based on the control signal.
The digital circuitry is operable to control a pulse width of a pulse of the digital output signal based on the control signal to maintain a given average voltage per cycle of the digital output signal to at least partially compensate for a change in a magnitude of the supply voltage.
The circuitry may be configured to increase a pulse width of a pulse of the digital output signal to at least partially compensate for the decrease in the magnitude of the supply voltage.
The circuitry may be configured to reduce a pulse width of a pulse of the digital output signal to at least partially compensate for the increase in magnitude of the supply voltage.
The monitoring circuitry may be configured to receive an input signal for the digital circuitry and output the modified input signal as a control signal to the digital circuitry, and the digital circuitry may be configured to generate a digital output signal based on the modified input signal.
The monitoring circuitry may include:
waveform generator circuitry configured to generate a voltage having an amplitude that varies over time based on a magnitude of a supply voltage;
comparator circuitry configured to compare the voltage with a reference voltage and to output a comparison signal when the voltage reaches the reference voltage; and
logic circuitry configured to receive an input signal and a comparison signal and generate a modified input signal for digital circuitry based on the input signal and the comparison signal.
The waveform generator circuitry may be configured such that the rate of increase of the voltage is inversely proportional to the magnitude of the supply voltage.
The waveform generator circuitry may be configured to generate a ramp voltage.
The monitoring circuitry may include:
a capacitor;
voltage-to-current converter circuitry configured to generate a first current based on a supply voltage;
current generator circuitry configured to generate a constant current for charging a capacitor; and
current mirror circuitry; and
a current control transistor, wherein the current mirror circuitry is configured to mirror the first current to a control terminal of the current control transistor such that the current control transistor controls a portion of the constant current that is diverted away from the capacitor.
The monitoring circuitry may include:
analog-to-digital converter (ADC) circuitry configured to generate a digital output signal based on a supply voltage;
timer circuitry configured to:
receiving an input signal and a digital output signal;
starting to time a time period upon detection of a characteristic of the input signal, wherein the duration of the time period is based on the digital output signal; and is also provided with
Outputting a timer output signal at the end of the time period; and
Logic circuitry configured to receive the input signal and the timer output signal and to generate a modified input signal for the PWM circuitry based on the input signal and the timer output signal.
The timer circuitry may be configured such that the duration of the time period is inversely proportional to the magnitude of the supply voltage.
The characteristic of the input signal may be a rising edge of a pulse of the input signal.
The monitoring circuitry may include:
voltage Controlled Oscillator (VCO) circuitry configured to generate an oscillating output signal having a frequency based on a supply voltage;
counter circuitry configured to:
receiving an input signal and an oscillating output signal;
starting counting cycles of the oscillating signal upon detection of a characteristic of the input signal; and is also provided with
Outputting a counter output signal when the count reaches a count value representing a magnitude of the supply voltage; and
logic circuitry configured to receive the input signal and the counter output signal and to generate a modified input signal for the PWM circuitry based on the input signal and the clocked counter output signal.
The VCO circuitry may be configured such that the frequency of the oscillating output signal is inversely proportional to the magnitude of the supply voltage.
The characteristic of the input signal may be a rising edge of a pulse of the input signal.
The digital circuitry may include Pulse Width Modulation (PWM) circuitry configured to generate PWM output signals.
According to a second aspect, the present invention provides an integrated circuit system comprising the circuitry as described in the first aspect.
According to a third aspect, the present invention provides a system comprising circuitry as claimed in any one of the first aspects and an output transducer configured to receive a digital output signal from the digital circuitry.
The output transducer may include one or more of a motor, a Light Emitting Diode (LED) or LED array, a haptic actuator, a resonant actuator, and/or a servo system.
According to a fourth aspect, the present invention provides a device comprising circuitry as described in the first aspect, wherein the device comprises a battery powered device, a computer game controller, a Virtual Reality (VR) or Augmented Reality (AR) device, a goggles, a mobile phone, a tablet or laptop computer, an accessory device, an earpiece, a headset, or a headset.
According to a fifth aspect, the present invention provides monitoring circuitry configured to receive a supply voltage applied to the digital circuitry and an input signal for the digital circuitry, the monitoring circuitry being configured to generate a modified input signal for the digital circuitry based on the input signal and the supply voltage.
According to a sixth aspect, the present invention provides digital driver circuitry comprising:
digital output circuitry; and
monitoring circuitry, wherein the monitoring circuitry is configured to receive an input signal for the digital output circuitry and a supply voltage applied to the digital output driver circuitry, and to generate a modified input signal for the digital output circuitry based on the input signal and the supply voltage.
According to a seventh aspect, the present invention provides digital control circuitry comprising:
digital output driver circuitry configured to generate a digital signal based on an input signal; and
circuitry configured to introduce a time offset into the digital signal, wherein the time offset is based on a magnitude of a supply voltage applied to the digital output driver circuitry.
According to an eighth aspect, the present invention provides circuitry comprising:
a digital signal modulator configured to output a modulated digital signal; and
circuitry configured to monitor a supply voltage of the modulator and output a control signal for controlling the modulator, wherein the control signal is based on the supply voltage.
According to a ninth aspect, the present invention provides a digital signal modulator configured to output a modulated digital signal, the digital signal modulator comprising:
circuitry configured to monitor a supply voltage of the modulator and output a control signal for controlling the modulation signal, wherein the control signal is based on the supply voltage.
According to a tenth aspect, the present invention provides circuitry for driving a load using a digital signal, wherein the circuitry is configured to regulate, control or adjust the width of one or more digital pulses to compensate for variations in a supply voltage to a digital modulator of the circuitry so as to maintain a uniform average voltage per cycle of the digital signal for a given load condition.
According to an eleventh aspect, the present invention provides a system comprising:
A plurality of driver circuits, each configured to output a drive signal for driving a load, wherein the drive signal is based on an input signal; and
a controller configured to control parameters of one or more of the drive signals to at least partially compensate for variations in components of the system.
The parameters of one or more of the drive signals may include a pulse width or a pulse amplitude of a digital drive signal output by one or more of the plurality of driver circuits.
The system may further include a power supply for providing a supply voltage to each of the plurality of driver circuits. The variations in the components of the system may include variations in the supply voltage.
The power supply may include a battery, and the change in a component of the system may include a change in a parameter of the battery.
The parameters of the battery may include one or more of the following:
an output voltage of the battery;
a state of charge of the battery;
the state of health of the battery; and
temperature of the battery.
The system may also include a voltage regulator. The change in a component of the system may include a change in an output voltage of the voltage regulator.
Variations in the components of the system may include variations in parasitic elements of the system.
The parasitic element may include a parasitic resistance.
The change in the component of the system may include a change in the temperature of the component.
The system may include one or more thermal monitors for providing thermal information to the controller.
The change in a component of the system may include a change in a parameter of the input signal.
The system may include one or more voltage monitors for monitoring the battery output voltage and/or the regulator output voltage.
The system may include one or more impedance monitors for measuring or estimating the impedance of the battery.
The one or more impedance monitors may be configured to measure an impedance of the battery or estimate the impedance of the battery based on one or more characteristics of the battery.
The one or more characteristics of the battery may include one or more of a state of charge, a state of health, a temperature, a parasitic element, a sense resistance, and/or a battery resistance.
The controller may be configured to estimate, calculate, or otherwise determine a predicted power demand for each drive signal based on one or more parameters of the system.
The one or more parameters of the system may include:
an amplitude level of an input signal on which the drive signal is based;
characteristics of the load driven by the drive signal;
for estimating a transient gradient of the inrush current;
A frequency;
average power; and/or
Transducer efficiency.
The controller may be configured to control parameters of one or more of the drive signals based on the predicted power requirements of the drive signals or a subset of the drive signals.
The controller may be configured to calculate, estimate, or otherwise determine a total predicted power demand and output a signal indicative of the total predicted power demand to the battery charger controller.
The battery charger controller may be configured to adjust the battery charging current based on the signal indicative of the total predicted power demand.
According to a twelfth aspect, the present invention provides a system comprising:
a plurality of driver circuits, each configured to output a driving signal for driving a load;
a power supply for providing a supply voltage to a plurality of driver circuits; and
a controller configured to regulate, control or adjust a parameter of one or more of the drive signals based on a level of the supply voltage and an indication of an expected transient load in the system.
According to a thirteenth aspect, the present invention provides a system comprising:
a power regulator or controller associated with the transducer;
One or more processors or controllers for controlling the power regulator or controller; and
a look-ahead controller configured to monitor control and/or data signals from one or more processors or controllers of the system, the look-ahead controller configured to adjust the transducer output power based on the supply voltage level and the monitored control and/or data signals.
The look-ahead controller may be configured to adjust the transducer output power to:
reducing or avoiding a power down condition; and/or
Providing a consistent output level; and/or
Reducing the cumulative output power requirement.
According to a fourteenth aspect, the present invention provides circuitry comprising:
one or more signal paths, each of the one or more signal paths configured to carry a signal for driving a load;
controller circuitry configured to receive data from at least one of the one or more signal paths and to output control data to one or more of the one or more signal paths for controlling one or more characteristics of signals carried by one or more of the one or more signal paths.
The data received by the controller circuitry from at least one of the one or more signal paths may include voltage data and/or thermal data and/or signal data.
The controller circuitry may include look-ahead controller circuitry.
The one or more signal paths may include an analog signal path and/or a digital signal path.
Each of the one or more signal paths may include transducer driver circuitry.
The controller circuitry may be configured to output control data to limit signal power of a load associated with one or more of the one or more signal paths.
The control data may be configured to cause attenuation of signals carried by one or more of the one or more signal paths.
The controller circuitry may be configured to output the control data to delay signals in one or more of the one or more signal paths.
According to a fifteenth aspect, the present invention provides circuitry comprising:
one or more driver signal paths, each driver signal path associated with a load for providing a drive signal to the load; and
advanced circuitry configured to:
Receiving signal data from a driver signal path;
estimating a power demand of a load based on the signal data and/or characteristics of the load coupled to the driver signal path;
predicting a future supply voltage based at least in part on the estimated power demand, the power supply parameter; and
parameters of signals in one or more of the driver signal paths are adjusted based on the predicted future supply voltage.
The power supply parameters may include one or more of the following:
a measure of the current battery supply level;
a supply decoupling capacitor; and
the battery RC is dynamic.
The battery RC dynamics may be based on battery parameters including one or more of the following:
a state of charge;
a state of health; and
temperature.
According to a sixteenth aspect, the present invention provides circuitry for receiving a voltage from a voltage supply for controlling one or more signal paths, comprising a controller configured to receive:
voltage data relating to at least the circuitry; and/or
Thermal data relating to at least the circuitry; and/or
Signal data from the one or more signal paths, wherein each signal path includes a respective transducer driver,
Wherein the circuitry is configured to output control data to the one or more signal paths to control one or more characteristics of respective signals in the one or more respective signal paths, wherein the controller is a predictive controller for controlling one or more characteristics of respective signals based on one or more of the received data before respective signals in one or more respective signal paths are output from their respective transducer drivers, so as to mitigate or avoid adverse voltage and/or thermal and/or signal conditions associated with at least the circuitry.
The adverse voltage condition may be a voltage supply power down condition.
The adverse thermal condition may be an undesirable thermal heating of the circuitry.
The adverse thermal condition may be undesirable thermal heating of other components or systems of the host device incorporating the circuitry.
The voltage data may originate from the battery monitor and/or the voltage monitor.
The battery monitor may be configured to monitor a battery parameter.
The battery parameters may include one or more of a state of charge of the battery, a state of health of the battery, and/or parasitic elements of and/or associated with the battery.
The thermal data may originate from one or more thermal monitors.
The signal data may originate from one or more points along the one or more signal paths.
The control data may control at least one signal parameter in the respective signal path. The at least one signal parameter controlled may be input to the controller.
The control data may control the gain of at least one signal in the respective signal path.
Circuitry may provide consistent power output.
The controller may output a total predicted power demand signal.
The total predicted power demand signal may be input to a battery controller.
Drawings
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1a is a schematic diagram showing circuitry for driving a transducer using digital signals;
FIG. 1b is a schematic diagram showing circuitry for driving a transducer using an analog signal;
FIG. 2 is a graph showing the digital signal output by the circuitry of FIG. 1a over time;
FIG. 3 is a schematic diagram illustrating exemplary circuitry for driving a transducer using digital signals according to the present disclosure;
FIG. 4 is a graph showing the digital signal output by the circuitry of FIG. 3 over time;
FIG. 5 is a schematic diagram illustrating exemplary monitoring circuitry for use in the circuitry of FIG. 3;
FIGS. 6a and 6b are timing diagrams illustrating operation of the circuitry of FIG. 5;
FIG. 7 is a schematic diagram illustrating exemplary ramp generator circuitry;
fig. 8 is a schematic diagram illustrating alternative exemplary monitoring circuitry.
Fig. 9a and 9b are timing diagrams illustrating the operation of the circuitry of fig. 8.
Fig. 10 is a schematic diagram illustrating additional alternative exemplary monitoring circuitry.
FIGS. 11a and 11b are timing diagrams illustrating the operation of the circuitry of FIG. 10;
FIG. 12 is a schematic diagram showing a host device incorporating the circuitry of FIG. 3;
FIG. 13a is a schematic diagram showing circuitry for driving a plurality of transducers using a corresponding plurality of digital signals;
FIG. 13b is a schematic diagram showing circuitry for driving a plurality of transducers using a corresponding plurality of digital signals;
FIG. 14 is a graph showing the digital signal output by the circuitry of FIG. 13a or FIG. 13b over time;
FIG. 15a is a schematic block diagram showing the monitoring and control elements;
FIG. 15b is a simplified schematic block diagram illustrating the monitoring and control elements;
FIG. 16 shows an exemplary waveform showing a sensor event under high dynamic load; and is also provided with
Fig. 17 shows the signal delayed to the transducer.
Detailed Description
Fig. 1a is a simplified schematic diagram of circuitry for driving a transducer using digital (e.g., PWM) signals. Circuitry, shown generally at 100a, includes digital output driver circuitry 110 coupled to a load 120. The load 120 may be, for example, a transducer such as a motor, LED (or LED array), servo system, haptic transducer, resonant actuator, or the like. Alternatively, the load 120 may be, for example, electronic circuitry, such as, for example, an audio amplifier.
Digital output driver circuitry 110 receives a supply voltage VBat from a power supply, which in this example is a battery 130, but may equally be a power supply or power converter, regulator, etc., whose output voltage may vary due to transient loads from other components or systems of the host device incorporating circuitry 100.
In this example, digital output driver circuitry 110 includes first and second inverters, 112 and 114, respectively, connected in series. The first inverter 112 receives the digital input signal SIn at its input node 140 and outputs a digital inverted signal of SIn at its output node 145, i.e
Figure BDA0004133540390000161
Second inverter 114 receives the inverted digital signal at its input node 140>
Figure BDA0004133540390000162
And outputs an inverted digital output signal digital out at its output node 150. Thus, the digital inputThe output signal DigitalOut has the same logic state or level as the digital input signal SIn.
Fig. 1b is a simplified schematic diagram of circuitry for driving a transducer using an analog signal analog out, which in this exemplary embodiment is derived from a digital signal SIn. The circuitry, shown generally at 100b, includes mixed signal (i.e., analog and digital signal) output driver circuitry 111, which is coupled to a load 120. The load 120 may be, for example, a transducer such as an audio transducer, a speaker, a haptic transducer, an ultrasonic transducer, or the like. Alternatively, the load 120 may be, for example, electronic circuitry, such as, for example, an audio amplifier.
The mixed signal output driver circuitry 111 receives the supply voltage VBat from the power supply as described with respect to fig. 1 a.
In this example, the mixed signal output driver circuitry 111 includes a digital-to-analog converter (DAC) 113 that receives a digital input signal SIn at its input node 140 and outputs an analog equivalent input signal AIn at its output node 146. The analog equivalent input signal AIn is input to the delay circuitry 115 in the signal path and to a DC/DC converter 117, such as a charge pump, for example. In this exemplary embodiment, the output of delay circuitry 115 is input to a pre-amplifier 119 in the signal path, and the output of pre-amplifier 119 is input to an output driver or power amplifier 121 in the signal path. The output driver or power amplifier 121 receives a bipolar supply voltage from the DC/DC converter 117, which receives its supply voltage from the battery 130. The bipolar voltage (v+, V-) supplied to the output driver 121 is controlled based on a parameter of the equivalent input signal Ain, such as for example the amplitude, such that the voltage supplied to the output driver 121 is controlled as a function of the parameter of the equivalent input signal AIn. The output signal analog out output at the output node 151 of the power amplifier 121 is used to drive the load 120. The arrangement and operation of such mixed signal output driver circuitry 111 is well known and understood by those of ordinary skill in the art. Those of ordinary skill in the art will also recognize and understand that even though the circuitry shown at 100b includes mixed signal (i.e., analog and digital signal) output driver circuitry 111, dac113 may be part of some other circuitry (not shown) such that output driver circuitry 111 is analog output driver circuitry 111 that receives analog equivalent input signal AIn as an input signal. Furthermore, the delay circuitry 115 may not receive a digital look-ahead signal instead of an analog look-ahead signal in the analog portion of the signal path, as shown in fig. 1b, but rather in the digital portion of the signal path upstream of the DAC113 and the DC-DC converter.
To maintain a constant average voltage per PWM period (and thus a consistent output of load 120, e.g., a consistent motor speed if load 120 is a DC motor, or a consistent light intensity if load 120 is an LED or LED array), PWM output driver circuitry 110 generates PWM output signal PWMOut having a constant duty cycle or mark-space ratio. This approach is effective when the supply voltage VBat is kept constant. However, if the supply voltage VBat changes, for example, due to the battery 130 discharging over time and/or due to other components, systems, transients, or circuitry of the host device drawing current from the battery 130, the average voltage of the PWM output signal PWMOut over the PWM signal period also drops, as will now be explained with reference to fig. 2.
FIG. 2 illustrates exemplary digital (e.g., PWM) pulses 210-250 output by PWM output driver circuitry 110 as supply voltage VBat (shown in phantom in FIG. 2) decreases over a plurality of PWM time periods P1-P5. It should be appreciated that FIG. 2 is a highly simplified representation of PWM pulses 210-250 for illustrative purposes only. Those of ordinary skill in the art will recognize that in practical applications, the frequency of the PWM signal will be much higher, e.g., on the order of kilohertz or megahertz.
Those of ordinary skill in the art will recognize that the average voltage (or equivalently, the average power) supplied by the PWM output driver circuitry 110 to the load 120 during the first PWM period P1 is represented by the area of the pulses 210. Similarly, the average voltage supplied by the modulator circuitry 110 to the load 120 during each of the PWM periods P2-P5 is represented by the area of the pulses 220-250, respectively.
If the supply voltage VBat is constant, the average voltage supplied by the PWM output driver circuitry 110 to the load 120 during each of the PWM periods P1-P5 will be the same, and thus the pulses 210-250 will all have the same area. However, in the example shown, the supply voltage VBat decreases over time, and thus, although the width of each of the pulses 210-250 (i.e., the on-time in each PWM period) is the same, the pulses 210-250 do not all have the same voltage magnitude (i.e., not all have the same amplitude or height), and thus the average voltage supplied to the load 120 per PWM period is not constant. This results in an inconsistent output signal PWMOut driving the load 120, which results in an inconsistent motor speed, for example, if the transducer 130 is a DC motor, or an inconsistent light intensity if the load 120 is an LED or LED array.
Fig. 3 is a schematic representation of circuitry for driving load 120 using a digital (e.g., PWM) signal configured to regulate, control, or adjust a parameter of the digital signal, such as, for example, the width of one or more PWM pulses, to compensate for variations in the supply voltage to PWM modulator 310 in order to maintain a uniform average voltage per PWM period and, thus, uniform load output performance.
The circuitry, shown generally at 300 in fig. 3, includes elements in common with the circuitry 100 of fig. 1 a. Such common elements are denoted by common reference numerals and will not be described in detail here.
Circuitry 300 includes PWM output driver circuitry 310, which is identical in structure and operation to PWM output driver circuitry 110 of fig. 1a, and therefore will not be described in detail herein.
The circuitry 300 also includes monitoring circuitry 320 configured to receive the supply voltage VBat and the input signal SIn and output a modified input signal SIn' to the PWM output driver circuitry 310 based on the level (e.g., amplitude) of the supply voltage VBat and the input signal SIn. The operation of the PWM output driver circuitry 310 is thus controlled based on the modified input signal SIn', as will be described in more detail below.
In the example shown, PWM output driver circuitry 310 is configured to receive modified input signal SIn from monitoring circuitry 320 and output an output PWM signal PWMOut based on modified input signal SIn'. Thus, the modified input signal SIn' may be considered a control signal for controlling the operation of the PWM output driver circuitry 310, which is based on the supply voltage VBat and the input signal SIn and is output by the monitoring circuitry 320. Thus, circuitry 300 may control or adapt the pulse width of one or more pulses of PWM output signal PWMOut to maintain a desired average voltage (or equivalently, a desired average output power) per PWM period in response to varying supply voltage VBat in order to maintain a desired load condition (e.g., to maintain a desired motor speed if load 120 is a motor).
Such a method is illustrated in fig. 4, which shows exemplary digital (e.g., PWM) pulses 410-450 output by PWM output driver circuitry 310 when the supply voltage VBat (shown in dashed lines in fig. 4) decreases over a plurality of PWM time periods P1-P5.
In contrast to the pulses 210-250 shown in fig. 2, the pulses 410-450 do not have the same width (i.e., duration). In contrast, the first pulse 410 of the first PWM period P1 is narrower (i.e., has a shorter duration) than the second pulse 430 of the second PWM period P2 and the third pulse 440 of the third PWM period P3. The fourth pulse 440 of the fourth PWM period P4 is slightly wider (has a slightly longer duration) than the second pulse 420 and the third pulse 430, and the fifth pulse 450 of the fifth PWM period is also wider (has a longer duration) than the second pulse 420 and the third pulse 430. (note that the width of the pulses is exaggerated in fig. 4 for purposes of illustration, and thus the exemplary pulses 410-450 shown in fig. 4 do not necessarily have equal areas, however, as will be apparent from the description below, each of the pulses 410-450 represents the same average voltage per PWM period).
Accordingly, PWM output driver circuitry 310 controls or adjusts the width of pulses 410-450 (relative to the default pulse width) to compensate for the varying supply voltage VBat such that the average voltage supplied to load 120 during each of PWM periods P1-P5 is the same in order to maintain a desired load condition (e.g., to maintain a desired motor speed if load 120 is a motor). Thus, for the first pulse 410, the pulse width has been reduced compared to the second pulse 420 and the third pulse 430 to compensate for its increased amplitude (height) relative to the second pulse 420 and the third pulse 430, while the pulse width of the fifth pulse 450 has been increased compared to the second pulse 420 and the third pulse 430 to compensate for its reduced amplitude (height) relative to the second pulse 420 and the third pulse 430. Thus, the total area of each of pulses 410-450 is the same.
Fig. 5 is a schematic representation of exemplary circuitry implementing monitoring circuitry 320. In the example shown in fig. 5, the monitoring circuitry (shown generally at 500) is configured to generate a modified input signal SIn 'and output the modified input signal SIn' to the digital (e.g., PWM) output driver circuitry 510 to control operation of the digital output driver circuitry 510.
The PWM digital output driver circuitry 510 of fig. 5 is identical in structure and operation to the digital PWM output driver circuitry 110 of fig. 1a, and therefore will not be described in detail herein.
The monitoring circuitry 500 includes waveform generator circuitry 530 configured to receive the supply voltage VBat (e.g., from the battery 130) and the input signal SIn, and in this example, generate an increased ramp voltage VRamp, the rate of which is based on the amplitude of the voltage VBat. The ramp voltage VRamp is output to a first non-inverting (+) input of the comparator circuitry 540. The second inverting (-) input of comparator circuitry 540 receives the reference or threshold voltage VRef from a suitable reference voltage source.
The output of comparator circuitry 540 is coupled to a first input of logic circuitry 550, which may include one or more flip-flops, logic gates, etc., as will be apparent to one of ordinary skill in the art. A second input of the logic circuitry 550 receives the input signal SIn. An output of logic circuitry 550 is coupled to an input of PWM output driver circuitry 510 to provide a modified input signal SIn' to PWM output driver circuitry 510 to control operation of PWM output driver circuitry 510.
The operation of the monitoring circuitry 500 will now be described with reference to the timing diagrams of fig. 6a and 6 b.
In FIG. 6a, the uppermost trace 610a shows a single pulse of the input signal SIn, and the second trace 620a shows a relatively low supply voltage VBat low The third trace 630a shows a relatively low supply voltage VBat at with a lower ramp voltage VRamp low The lower modified input signal SIn' and fourth trace 640a shows a relatively low supply voltage VBat low The lower PWM output signal PWMOut.
When a rising edge of a pulse of the input signal SIn is detected at time t0, the ramp generator circuitry 530 begins to generate a ramp voltage that increases from 0v. The rate of change of the ramp voltage Δ1 (i.e., slope 622 a) is based on the supply voltage such that at a relatively high supply voltage VBat high Under the ramp voltage VRamp increases to be higher than at the relatively lower supply voltage VBat low The ramp down, i.e., the rate of increase of the ramp voltage VRamp, is inversely proportional to the supply voltage VBat.
At a relatively low supply voltage (i.e., vbat=vbat low ) In the case of (2), the ramp voltage VRamp reaches the reference voltage VRef at time t 1. Between t0 and t1, the ramp voltage VRamp is less than the reference voltage VRef, and thus the output of the comparator circuitry 540 is low. The output of logic circuitry 550 is therefore also low and thus modified input signal SIn' is low. Thus, the PWM output signal PWMOut is low. The ramp voltage VRamp may be reset to 0v when the reference voltage VRef is reached or shortly thereafter.
At time t1, ramp voltage VRamp reaches reference voltage VRef and the output of comparator circuitry 540 therefore goes high, which in turn causes the output of logic circuitry 550 to go high and modified input signal SIn' to go high. The PWM output signal PWMOut is therefore equal to (or close to) VBat low 。
At the end of the pulse of input signal SIn (at time t 3), the output of logic circuitry 850 goes low, SIn' goes low, and PWMOut goes low again.
In FIG. 6b, the uppermost trace 610b shows a single pulse of the input signal SIn, and the second trace 620b shows a relatively high supply voltage VBat high The third trace 630b shows a relatively high supply voltage VBat at with a lower ramp voltage VRamp high The lower modified input signal SIn' and fourth trace 640b shows a relatively high supply voltage VBat high The lower PWM output signal PWMOut.
At a relatively high supply voltage (i.e., vbat=vbat high ) In the case of (a), the ramp voltage VRamp is relatively low with the supply voltage (i.e., vbat=vbat low ) The reference voltage VRef is reached later in time t2, i.e., the rate of change Δ2 of the voltage VRamp (i.e., slope 622 b) is smaller than when the supply voltage is relatively low. Between t0 and t2, the ramp voltage VRamp is less than the reference voltage VRef, and thus the output of the comparator circuitry 540 is low. The output of logic circuitry 550 is therefore also low and thus modified input signal SIn' is low. Thus, the PWM output signal PWMOut is low.
At time t2, ramp voltage VRamp reaches reference voltage VRef and the output of comparator circuitry 540 therefore goes high, which in turn causes the output of logic circuitry 550 to go high and modified input signal SIn' to go high. The PWM output signal PWMOut is therefore equal to (or close to) VBat high . The ramp voltage VRamp may be reset to 0v when the reference voltage VRef is reached or shortly thereafter.
At the end of the pulse of the input signal SIn (at time t 3), the output of logic circuitry 550 goes low, SIn' also goes low, and PWMOut goes low again.
Upon detecting the rising edge of the next pulse of the input signal SIn, the ramp signal VRamp is at 0v (or reset to 0v if not yet reset to 0 v) and begins to increase in magnitude based on the supply voltage VBat again.
As will be apparent from the traces 630a, 630b, 640a, 640b in particular, the monitoring circuit conventional 500 compensates for the relative by increasing the width (i.e., duration) of the pulse in the PWM period of the output signal PWMOutLower supply voltage VBat low In order to maintain a substantially constant average voltage per PWM period regardless of the reduced magnitude of the supply voltage.
Similarly, the monitoring circuitry 500 compensates for the relatively high supply voltage VBat by reducing the width (i.e., duration) of the pulse in the PWM period of the output signal PWMOut high In order to maintain a substantially constant average voltage per PWM period regardless of the increasing magnitude of the supply voltage.
The monitoring circuitry 500 essentially implements timer circuitry that introduces a time offset into the PWM signal generated by the PWM output driver circuitry 510 based on the magnitude of the supply voltage VBat. The introduced time offset compensates for the variation in the magnitude of the supply voltage VBat by varying the length or duration of the PWM pulse.
Although the operation of the monitoring circuitry 500 is described above in terms of generation of the ramp voltage VRamp, one of ordinary skill in the art will recognize that the waveform generator circuitry 530 need not generate a linear ramp, but may generate some other waveform having an amplitude that varies over time based on the supply voltage VBat.
Fig. 7 is a schematic representation of exemplary circuitry implementing waveform generator circuitry 530 for circuitry 500 of fig. 5. In this example, the circuitry includes ramp generator circuitry.
The ramp generator circuitry, shown generally at 700 in fig. 7, includes amplifier circuitry 710 having a first input configured to receive a voltage Vin from a bit divider comprised of a first resistor 712 and a second resistor 714 coupled in series between a positive power supply voltage rail receiving a supply voltage VBat and a reference voltage supply rail GND or another suitable reference voltage coupled to ground. A second input of the amplifier circuitry receives a feedback signal from a feedback loop comprising a transistor 720 and a third resistor 722. Thus, as will be apparent to one of ordinary skill in the art, the amplifier circuitry 710 is configured to operate as a voltage-to-current converter to generate a voltage I1 that flows through the third resistor 722, where I1 is equal to Vin/R, where R is the resistance value of the third resistor 722.
Ramp generator circuitry 700 also includes current generator circuitry 730 coupled in series with second transistor 740 between the supply voltage rail and the reference voltage rail. Capacitor 750 is coupled in parallel with transistor 740 between output node 760 of ramp generator circuitry 700 and reference voltage supply rail GND.
The current I1 is mirrored to a control terminal (e.g., gate terminal) of the second transistor 740 through the current mirror transistors 770, 780, 790.
The second transistor 740 is operable to control the flow of a portion of the constant current IConst to the reference voltage supply rail GND. Thus, based on the current I1 being proportional to the supply voltage VBat, the second transistor 740 bleeds or diverts away from the capacitor 750 the portion of the current IConst that would otherwise flow to the capacitor 750. Thus, as VBat increases, V1 increases, and current I1 also increases. This increase in I1 is mirrored to the control terminal of the second transistor 740, which thus diverts a greater portion of the constant current IConst away from the capacitor 750, which reduces the rate of increase, i.e., the slope, of the ramp voltage VRamp across the capacitor 750. Conversely, as VBat decreases, V1 decreases and current I1 also decreases. The second transistor 740 diverts a smaller portion of the constant current IConst away from the capacitor 750, thereby increasing the rate of increase of the ramp voltage VRamp. Thus, the rate of increase of the ramp voltage VRamp is inversely proportional to the supply voltage VBat.
Fig. 8 is a schematic representation of alternative exemplary circuitry implementing the monitoring circuitry 320. In the example shown in fig. 8, the monitoring circuitry (shown generally at 800) is configured to generate a modified input signal SIn 'and output the modified input signal SIn' to the PWM output driver circuitry 810 to control operation of the PWM output driver circuitry 810.
The PWM output driver circuitry 810 of fig. 8 is identical in structure and operation to the PWM output driver circuitry 110 of fig. 1, and therefore will not be described in detail herein.
The monitoring circuitry 800 includes a first resistor 822 and a second resistor 824 coupled in series between a positive supply rail receiving the supply voltage VBat and the reference supply voltage GND (or some other suitable reference voltage source) to form a bit divider. A node 826 intermediate the first resistor 822 and the second resistor 824 is coupled to an input of analog-to-digital converter (ADC) circuitry 830. The ADC circuitry 830 thus receives an input voltage indicative of the supply voltage VBat and outputs a digital signal VBat' representative of the supply voltage VBat.
An output of ADC circuitry 830 is coupled to a first input of timer circuitry 840, which receives digital signal VBat' accordingly. A second input of timer circuitry 840 receives input signal SIn.
An output of timer circuitry 840 is coupled to a first input of logic circuitry 850. A second input of the logic circuitry receives the input signal SIn. Logic circuitry 850 may include one or more flip-flops, logic gates, etc., as will be apparent to one of ordinary skill in the art, and is configured to receive the signal output by timer circuitry 840 as well as input signal SIn and to generate a modified input signal SIn' for output to PWM output driver circuitry 810.
In operation of the monitoring circuitry 800, the ADC circuitry 830 outputs a digital signal VBat' to the timer circuitry 840 indicative of the magnitude of the supply voltage VBat. Upon detecting the rising edge of a pulse of the input signal SIn, the timer circuitry 840 begins to time a time period of fixed duration. The fixed duration is based on the digital signal VBat' output by the ADC circuitry 840 such that the fixed duration d of the time period is inversely proportional to the magnitude of the supply voltage. At the end of the time period, i.e., when the fixed duration has expired, timer circuitry 840 outputs a signal to logic circuitry 850, which begins an output pulse of modified input signal SIn'. The output pulse of the modified input signal SIn' ends when the logic circuitry 850 detects a falling edge of the pulse of the input signal SIn.
The operation of the monitoring circuitry 1100 will now be described with reference to the timing diagrams of fig. 9a and 9 b.
In fig. 9a, the uppermost trace 910a shows a single pulse of the input signal SIn, and the second trace 920a shows a relatively low supply voltage VBat low Operation of the lower timer circuitry 840, the third trace 930a shows a relatively low supply voltage VBat low The lower modified input signal SIn' and fourth trace 940a shows a relatively low supply voltage VBat low The lower PWM output signal PWMOut.
When a rising edge of a pulse of the input signal SIn is detected at time t0, timer circuitry 840 begins to time a time period having a fixed duration d1, as discussed above, determined based on the value of the digital signal output by ADC circuitry 830, such that at a relatively low supply voltage VBat low The fixed duration d1 is shorter than the relatively high supply voltage VBat high A fixed duration d2 below. Thus, the fixed duration of the time period is inversely proportional to the magnitude of the supply voltage VBat.
At a relatively low supply voltage (i.e., vbat=vbat low ) In the event that the fixed duration d1 of the time period expires at time t1, timer circuitry 840 stops counting and provides a trigger signal to logic circuitry 850. Until logic circuitry 850 receives this trigger signal, the output of logic circuitry 850 is low and, therefore, modified input signal SIn' is low. Thus, the PWM output signal PWMOut is low.
At time t1, the fixed duration d1 of the time period expires and timer circuitry 840 outputs a trigger signal to logic circuitry 850, which in turn causes the output of logic circuitry 850 to go high and modified input signal SIn' to go high. The PWM output signal PWMOut is therefore equal to (or close to) VBat low 。
At the end of the pulse of input signal SIn (at time t 3), the output of logic circuitry 850 goes low, SIn' goes low, and PWMOut goes low again.
In fig. 9b, the uppermost trace 910b shows a single pulse of the input signal SIn, and the second trace 920b shows a relatively high supply powerPressing VBat high Operation of the lower timer circuitry 840, the third trace 930b shows a relatively high supply voltage VBat high The lower modified input signal SIn' and fourth trace 940b shows a relatively high supply voltage VBat high The lower PWM output signal PWMOut.
At a relatively high supply voltage (i.e., vbat=vbat high ) In the event that the fixed duration d2 of the time period of the timer circuitry 1140 is relatively low with the supply voltage (i.e., vbat=vbat) low ) Later than expiration at time t2, timer circuitry 840 outputs a trigger signal to logic circuitry 850. Until the trigger signal is received, the output of logic circuitry 850 is low and, therefore, modified input signal SIn' is low. Thus, the PWM output signal PWMOut is low.
At time t2, the fixed duration d2 of the time period expires and timer circuitry 840 outputs a trigger signal to logic circuitry 850, which in turn causes the output of logic circuitry 850 to go high and modified input signal SIn' to go high. The PWM output signal PWMOut is therefore equal to (or close to) VBat high 。
At the end of the pulse of input signal SIn (at time t 3), the output of logic circuitry 850 goes low, SIn' also goes low, and PWMOut goes low again.
Upon detection of the rising edge of the next pulse of the input signal SIn, the timer circuitry 840 resets and starts to count a new time period, the fixed duration of which is based on the then-current magnitude of the supply voltage VBat.
As will be apparent from the traces 930a, 930b, 940a, 940b in particular, the monitoring circuit conventional 800 compensates for the relatively low supply voltage VBat by increasing the width (i.e., duration) of the pulse in the PWM period of the output signal PWMOut low In order to maintain a substantially constant average voltage per PWM period regardless of the reduced magnitude of the supply voltage.
Similarly, the monitoring circuitry 800 monitors the output signal PWMOut by decreasing the width (i.e., duration) of the pulse in the PWM period of the output signal PWMOut ) To compensate for the relatively high supply voltage VBat high In order to maintain a substantially constant average voltage per PWM period regardless of the increasing magnitude of the supply voltage.
Likewise, the monitoring circuitry 800 essentially implements timer circuitry that introduces a time offset into the PWM signal generated by the PWM output driver circuitry 810 based on the magnitude of the supply voltage VBat. The introduced time offset compensates for the variation in the magnitude of the supply voltage VBat by varying the length of the PWM pulse.
Fig. 10 is a schematic representation of additional alternative exemplary circuitry implementing the monitoring circuitry 320. In the example shown in fig. 10, the monitoring circuitry (shown generally at 1000) is configured to generate a modified input signal SIn 'and output the modified input signal SIn' to the PWM output driver circuitry 1010 to control operation of the PWM output driver circuitry 1010.
The PWM output driver circuitry 1010 of fig. 10 is identical in structure and operation to the PWM output driver circuitry 110 of fig. 1, and therefore will not be described in detail herein.
Monitoring circuitry 1000 includes Voltage Controlled Oscillator (VCO) circuitry 1030 configured to receive a supply voltage VBat and output an oscillating signal SOsc having a frequency fOsc that varies according to the magnitude of supply voltage VBat. In this example, the frequency fOsc of the oscillating signal SOsc is inversely proportional to the magnitude of the supply voltage VBat, such that when the supply voltage is relatively low (i.e., vbat=vbat high ) When the fOsc is relatively high with supply voltage (i.e., vbat=vbat low ) Higher than the time.
An output of VCO circuitry 1030 is coupled to a first input of counter circuitry 1040. A second input of counter circuitry 1040 receives input signal SIn. The counter circuitry 1040 is configured to start counting cycles of the oscillation signal SOsc received at its first input upon detection of a rising edge of a pulse of the input signal SIn, and to output a trigger signal to the logic circuitry 1050 when the count value Cnt reaches the count value CntVBat representing the supply voltage VBat. As will be appreciated, the count value CntVBat representing the supply voltage VBat will be reached faster at higher values of the fossc than at lower values of the fossc, and thus the count value CntVBat representing the supply voltage VBat will be reached faster when the magnitude of the supply voltage VBat is lower.
An output of counter circuitry 1040 is coupled to a first input of logic circuitry 1050. A second input of logic circuitry 1050 receives an input signal SIn. Logic circuitry 1050 may include one or more flip-flops, logic gates, etc., as will be apparent to one of ordinary skill in the art, and is configured to receive the trigger signal output by counter circuitry 1040 and input signal SIn, and to generate a modified input signal SIn' for output to PWM output driver circuitry 1010.
In operation of monitoring circuitry 1000, VCO circuitry 1030 outputs an oscillation signal SOsc to counter circuitry 1040, the frequency fOsc of which is based on or indicative of the magnitude of supply voltage VBat. Upon detecting the rising edge of the pulse of the input signal SIn, the counter circuitry 1040 begins counting oscillations of the oscillation signal SOsc until reaching a count value CntVBat representing the supply voltage VBat, at which point the counter circuitry 1040 outputs a trigger signal to the logic circuitry 1050, which begins modifying the output pulse of the input signal SIn'. The output pulse of the modified input signal SIn' ends when the logic circuitry 1050 detects a falling edge of the pulse of the input signal SIn.
The operation of the monitoring circuitry 1000 will now be described with reference to the timing diagrams of fig. 11a and 11 b.
In FIG. 11a, the uppermost trace 1110a shows a single pulse of the input signal SIn, and the second trace 1120a shows a relatively low supply voltage VBat low Lower count Cnt, third trace 1130a shows a relatively low supply voltage VBat low The fourth trace 1140a shows a relatively low supply voltage VBat for the lower modified input signal SIn low The lower PWM output signal PWMOut.
When a rising edge of a pulse of the input signal SIn is detected at time t0, counter circuitry 1040 begins to provide a counter to the VCOThe cycles of the oscillation signal SOsc output by circuitry 1030 are counted. As discussed above, the frequency fOsc of the oscillating signal SOsc is based on the magnitude of the supply voltage VBat such that at relatively low supply voltages VBat high At a frequency fOsc and at a relatively high supply voltage VBat low The lower phase ratio is higher.
At a relatively low supply voltage (i.e., vbat=vbat low ) In the case of (2), the count value CntVBat representing the magnitude of the supply voltage VBat is reached at time t1, at which point the counter circuitry 1040 outputs a trigger signal to the logic circuitry 1050. Thus, until t1, the output of logic circuitry 1050 is low, and thus modified input signal SIn' is also low. Thus, the PWM output signal PWMOut is low.
At time t1, a count value CntVBat representing the magnitude of the supply voltage VBat is reached, and counter circuitry 1040 outputs a trigger signal to logic circuitry 1050, which in turn causes the output of logic circuitry 1050 to go high and modified input signal SIn' to go high. The PWM output signal PWMOut is therefore equal to (or close to) VBat low 。
At the end of the pulse of input signal SIn (at time t 3), the output of logic circuitry 1050 goes low, SIn' goes low, and PWMOut goes low again. The count Cnt may be reset to zero when appropriate, such as when it reaches CntVBat (or shortly thereafter) at the end of a pulse of the input signal SIn.
In FIG. 11b, the uppermost trace 1110b shows a single pulse of the input signal SIn, and the second trace 1120b shows a relatively high supply voltage VBat high Count Cnt of lower counter circuitry 1040, third trace 1130b shows a relatively high supply voltage VBat high The lower modified input signal SIn' and fourth trace 1140b shows a relatively high supply voltage VBat high The lower PWM output signal PWMOut.
At a relatively high supply voltage (i.e., vbat=vbat high ) Is relatively low compared to the supply voltage (i.e., vbat=vbat low ) At a later time than at time t2, a count value CntVBat representing the magnitude of the supply voltage VBat is reached, at which time the counter circuitThe system 1040 outputs a trigger signal to logic circuitry 1050. Thus, until t2, the output of logic circuitry 1050 is low, and thus modified input signal SIn' is also low. Thus, the PWM output signal PWMOut is low.
At time t2, a count value CntVBat representing the magnitude of the supply voltage VBat is reached, and counter circuitry 1040 outputs a trigger signal to logic circuitry 1050, which in turn causes the output of logic circuitry 1050 to go high and modified input signal SIn' to go high. The PWM output signal PWMOut is therefore equal to (or close to) VBat high 。
At the end of the pulse of input signal SIn (at time t 3), the output of logic circuitry 1050 goes low, SIn' also goes low, and PWMOut is also low. The count Cnt may be reset to zero when appropriate, such as when it reaches CntVBat (or shortly thereafter) at the end of a pulse of the input signal SIn.
Upon detection of the rising edge of the next pulse of the input signal SIn, counter circuitry 1040 resets (if it has not previously been reset) and begins to count oscillations of signal SOsc, whose frequency fOsc is based on the then-current magnitude of supply voltage VBat.
As will be apparent from the traces 1130a, 1130b, 1140a, 1140b in particular, the monitor circuit conventional 1000 compensates for the relatively low supply voltage VBat by increasing the width (i.e., duration) of the pulse in the PWM period of the output signal PWMOut low In order to maintain a substantially constant average voltage per PWM period regardless of the reduced magnitude of the supply voltage.
Similarly, the monitoring circuitry 1000 compensates for the relatively high supply voltage VBat by reducing the width (i.e., duration) of the pulse in the PWM period of the output signal PWMOut high In order to maintain a substantially constant average voltage per PWM period regardless of the increasing magnitude of the supply voltage.
Likewise, the monitoring circuitry 1000 essentially implements timer circuitry that introduces a time offset into the PWM signal generated by the PWM output driver circuitry 1010 based on the magnitude of the supply voltage VBat. The introduced time offset compensates for the variation in the magnitude of the supply voltage VBat by increasing the length of the PWM pulse.
Circuitry 300 may be incorporated into a host device, which may be a battery powered device. For example, the host device may include a computer game controller, a Virtual Reality (VR) or Augmented Reality (AR) device (such as a headset, goggles, etc.), a mobile phone, a tablet or laptop computer, or an accessory device such as an earpiece, headset, or headphones.
Fig. 12 is a schematic representation showing some elements of such a host device. The host device, shown generally at 1200 in fig. 12, includes a battery 1210, a load 120, which may be, for example, an output transducer such as a motor, LED or LED array, a haptic transducer, a resonant actuator, or a servo system, or alternatively may be electronic circuitry such as amplifier circuitry. The load 120 is controlled by the PWM output driver circuitry 310 based on the modified input signal SIn' output by the monitoring circuitry 320, as described above with reference to fig. 3-11.
The host device 1200 may further include: one or more input transducers 1220 (and associated driver circuitry) which may include, for example, a microphone, joystick, one or more buttons, switches, force sensors, touch sensors, and/or a touch screen; and one or more output transducers 1230 (and associated driver circuitry) that may include, for example, one or more haptic output transducers, one or more audio output transducers such as speakers, and one or more video output transducers such as a screen, display, etc.
Fig. 13a is a variation of fig. 1a and 1b, in which a plurality (N) of digital and/or analog output driver circuits 110-1 to 110-N are coupled to respective loads 120-1 to 120-N. Each of the loads 120-1 through 120-N may be, for example, a transducer such as: a motor; an LED (or LED array); a servo system; a speaker, a haptic transducer; resonant actuators, and the like, including various combinations thereof. Alternatively and/or additionally, one or more of the loads 120-1 to 120-N may be, for example, electronic circuitry, such as, for example, an audio amplifier.
Each of the digital and/or analog output driver circuits 110-1 through 110-N receives a supply voltage VBat from a power supply, which in this example is a battery 130, but may equally be a power supply or a power converter, regulator, etc., whose output voltage may vary due to transient loads from other components or systems of a host device incorporating the circuitry 100/100-N. For simplicity, references to digital output driver circuits 110-1 through 110-N also include references to analog output driver circuits 111-1 through 111-N (see FIG. 1 b), as well as references to any and all combinations of digital and/or analog PWM output driver circuits.
Each of the digital and/or analog output driver circuits 110-1 to 110-N includes the same or similar circuitry as shown in fig. 1a and 1b and each receives a respective input signal SIn-1 to SIn-N to drive a respective load 120-1 to 120-N.
In order to maintain a constant average voltage (and thus a consistent output to the respective loads 120-1 to 120-N, for example, a consistent motor speed in the case where the load 120 is a DC motor, or a consistent light intensity in the case where the load 120 is an LED or LED array) per respective PWM period PWMOut-1 to PWMOut-N, each respective PWM output driver circuit 110-1 to 110-N generates a respective PWM output signal PWMOut-1 to PWMOut-N having a respective constant duty cycle or mark-space ratio. This approach is effective when the supply voltage VBat is kept constant. However, if the supply voltage VBat changes, for example, due to the discharge of the battery 130 over time and/or due to other components, systems, transients, or circuitry of the host device drawing current from the battery 130, the average voltage of the respective PWM output signals PWMOut-1 through PWMOut-N over the respective PWM signal periods also decreases, as will be explained below with reference to fig. 14a and 14 b.
Fig. 13b is a variation of fig. 13a, in which a plurality (N) of digital output driver circuits 110-1 through 110-N are coupled to respective loads 120-1 through 120-N. For example, each of the loads 120-1 through 120-N may be, for example, those as described with respect to FIG. 13 a. All other relevant aspects between fig. 13a and 13b are as described above with respect to fig. 13a, as will be appreciated by one of ordinary skill in the art.
Fig. 14 shows an exemplary digital pulse 210'-250' that is primarily output by only one of the plurality of digital output driver circuits 110-1 to 110-N when the supply voltage VBat (shown in upper dashed lines in fig. 2 b) decreases over a plurality of PWM time periods P1 '-P5'.
To clearly explain this fig. 14, only PWM output driver circuit 110-1 will be mainly described, and one of ordinary skill in the art will understand that the same principles apply to any and all other output driver circuits 110-2 through 110-N.
It should be appreciated that fig. 14 is a highly simplified representation of PWM pulses 210'-250' and is for illustrative purposes only. Those of ordinary skill in the art will recognize that in practical applications, the frequency of the PWM signal will be much higher, e.g., on the order of kilohertz or megahertz.
Those of ordinary skill in the art will recognize that the average voltage (or equivalently, the average power) supplied by the PWM output driver circuitry 110-1 to its load 120-1 during the first PWM period P1 'is represented by the area of the pulse 210'. Similarly, the average voltage supplied by the modulator circuitry 110-1 to its load 120-1 during each of the PWM periods P2'-P5' is represented by the area of the pulses 220'-250', respectively.
If the supply voltage VBat is constant, the average voltage supplied by the PWM output driver circuitry 110-1 to the load 120-1 during each of the PWM periods P1'-P5' will be the same, and thus the pulses 210'-250' will all have the same area. However, in the example shown, the supply voltage VBat decreases over time, and thus, although the width of each of the pulses 210'-250' (i.e., the on-time in each PWM period) is the same, the pulses 210'-250' do not all have the same voltage magnitude (i.e., not all have the same amplitude or height), and thus the average voltage supplied to the load 120-1 per PWM period, and thus the power, is not constant. This results in non-uniformity of the output signal PWMOut-1 driving the load 120-1, which results in non-uniformity of motor speed, for example, if the transducer 120-1 is a DC motor, or in non-uniformity of light intensity, for example, if the load 120-1 is an LED or LED array.
As shown in fig. 14, there are two examples of transient events T1 and T2 occurring. These transients may occur due to the over-current requirements from any combination of loads 120-2 through 120-N and/or any combination of other components or systems of the host device and the load requirements of PWM output driver circuitry 110-1 and its load 120-1. The grey-scale portions within PWM "on" pulses 230' and 240' represent PWM ' on ' pulses from any combination of loads 120-2 through 120-N and/or any combination of other components or systems of the host device, respectively 230' T And 240' T Which happens to coincide with PWM 'on' periods 230 'and 240' of PWM output driver circuitry 110-1 and its load 120-1. This coincidence of PWM 'on' periods illustrates how such transients T1 and T2 may occur when two or more of the PWM 'on' pulses of any combination of loads 120-1 through 120-N and/or any combination of other components or systems of the host device coincide (whether fully and/or partially) and exceed the current delivery capability of the supply voltage VBat. Those of ordinary skill in the art will recognize that real-life applications may result in a much more complex situation than that shown in fig. 14.
As can be seen in fig. 14, transient T1 results in a decrease in supply voltage VBat because of the over-current demand during the P3' PWM period due to the coincidence of PWM ' on ' pulses that exceed the current delivery capability of supply voltage VBat. However, the over-current demand is insufficient to reduce the supply voltage VBat below the power-down threshold V BOT And the supply voltage VBat returns to its nominal level when the over-current demand ceases (i.e., when coincidence of the multiple PWM 'on' pulses ceases).
Similarly, transient T2 results in a decrease in supply voltage VBat because of the over-current demand during the P4' PWM period due to the coincidence of multiple PWM ' on ' pulses that exceed the current delivery capability of supply voltage VBat. However, in this T2 case, the over-current demand is far enough that when the supply voltage VBat stops at the over-current demand (i.e., at multiple PWM's)' At cessation of coincidence of on' pulses) reduces the supply voltage VBat below the power-down threshold V before returning to its nominal level BOT . However, when the supply voltage VBat is lower than the power down threshold V BOT When this triggers the PWM output driver circuits 110-1 to 110-N and/or other components or systems of the host device incorporating the PWM output driver circuits 110-1 to 110-N, for example, to power down and reset or shut down entirely.
Coincidence of PWM 'on' periods, whether or not resulting in triggering a power down condition, may also result in thermal problems that may result in other components or systems of PWM output driver circuits 110-1 through 110-N and/or host devices incorporating PWM output driver circuits 110-1 through 110-N, such as powering down and resetting or turning off entirely.
Fig. 15a is a block-level representation of elements (e.g., like hardware and/or firmware and/or software) for monitoring and controlling aspects of the digital and/or analog output driver circuits 110/1-1 to 110/1-N, including their respective signal paths and/or associated blocks and/or other components or systems of a host device incorporating the digital and/or analog output driver circuits 110/1-1 to 110/1-N, not all of which may be shown for clarity of explanation. Here, for brevity and clarity, only digital output driver circuits 110-1 through 110-N will be described, but the same or similar reasoning will apply to analog output driver circuits 111-1 through 111-N, as will be recognized and understood by those of ordinary skill in the art.
Each of the PWM output driver circuits 110-1 to 110-N drives a respective load 120-1 to 120-N (not shown) using a respective PWM output signal 120-1 to 120-N. One or more parameters, such as, for example, pulse width or pulse amplitude, of one or more of the corresponding digital pulses of the PWM output signal may be regulated, controlled, or adjusted using, for example, predictive controller 1100 to compensate for, for example, supply voltage VBat and/or "variations" in regulator supply and/or battery parameters, including, but not limited to, state of charge (SOC) of the battery, state of health, temperature, and/or parasitic elements (e.g., rtrace, rsense, rsystem), and/or temperatures of hardware, firmware, and/or other components or systems of the host device incorporating at least the hardware and/or firmware and/or software shown in the block level representation of fig. 15 a.
The advanced concept illustrated in fig. 15a is to use knowledge of the time and location at which the transient load and/or its associated effects occur or are likely to occur in order to compensate for the "variations" described above and predictively regulate, control or adjust one or more parameters of one or more of the respective PWM pulses.
Predictive controller 1100 may be, for example, a state machine that predictively regulates, controls, or adjusts one or more parameters of one or more of the respective PWM pulses PWMOut-1 through PWMOut-N to compensate for, for example, battery/regulator status, thermal information from one or more thermal monitors, and/or any combination of signals SIN-1 through SIN-N at any point in the signal path, and/or "variations" in their respective signal parameters. In addition, predictive controller 1100 may output a 'total predicted power demand' signal, or the like, based on, for example, one or more of its various inputs, which may be sent to a battery charger controller (not shown) or a portion thereof, such as a battery charger state machine, in order to allow the battery charger controller to dynamically stop or reduce battery charging current in order to avoid over-temperature or over-current events.
Thus, the method shown in fig. 15a uses knowledge of and/or associated with the system and/or transient load at a high conceptual level to control one or more parameters of the digital signal, such as the width of the PWM signal, accordingly, in order to at least mitigate or preferably prevent, for example, power down that would typically occur at T2, and/or reduce peak thermal problems that may occur in the system, and/or provide consistent drive strength or consistent output power, i.e. drive pulse area.
The host device typically includes one or more processors that control, for example, the transducer and associated power regulator and controller (including a battery charger controller). Control and/or data signals from one or more processors and/or controllers may also be observed by the controller 1100 before they are applied to the sensor outputs. Such a signal is preceded byIt may also give the opportunity to compensate for any reduction in the supply voltage VBat that may be caused by the transducer or power regulator to mitigate or avoid a power down condition by reducing the transducer output power, or to provide a consistent output level by adapting the output level to the supply level. Additionally or alternatively, the cumulative demand may also be reduced to reduce thermal heating, particularly through on-chip I 2 R loss (as in a transducer driver or regulator, for example).
The power prediction of each transducer input signal PWMOut-X, analogue-X (where X represents a number between 1 and N) may be based on one or more parameters, such as, for example: its corresponding input signal S IN-1 -to S IN-N Amplitude level of (2); known optionally programmable load characteristics; complex characteristics such as, but not limited to, transient gradients, for example, for estimating inrush current; a frequency; average power; and/or transducer efficiency.
The voltage supply information may include, for example: a voltage monitor for measuring the current battery (and, if needed), regulator supply level; and/or an impedance monitor for measuring battery impedance or estimating battery impedance based on some or all of battery characteristics (such as, for example, state of charge, state of health, current temperature, parasitic elements such as battery PCB/connector trace impedance, current sense resistance, and/or battery resistance).
The predictive signal controller 1100 may take into account the cumulative effect of each of the power predictions of the transducer inputs (or a selectable subset thereof) and in conjunction with the current voltage supply level and the predictions of the battery impedance, predictively regulate, control or adjust the transducer signals (or regulate, control or adjust the transducer drivers or regulators) before applying them to their transducer outputs, as needed, to avoid premature battery power-down and/or reduce peak thermal problems, and/or to provide consistent transducer power output levels, i.e., drive strengths, in the presence of varying supply voltages. Adjusting whether all or a subset of the transducers is optional.
Additionally and/or alternatively, the prediction signal controller 1100 may provide to respective individual power predictorsThe respective signals adjust the states to allow them to dynamically compensate for their estimates. The predictive controller 1100 may also consider the pre-conditioned but delayed corresponding transducer input signal S IN-1_DEL To S IN-N_DEL To ensure that high power demands have passed or that the delay of the corresponding power prediction can be matched to its signal path delay.
Any application of signal conditioning may be directly applied to the signal and/or to the DAC/driver of the transducer (such as when used to modulate PWM drive signals, similar to the scheme outlined in co-pending U.S. patent application No. 63/059,504).
The long-term supply voltage VBat measurement may be a short-term estimate or may optionally be filtered, delayed or averaged to account for effects such as decoupling capacitance, for example. Transducer signal monitoring may include programmability of transducer characteristics such as, for example, peak output power, aging effects, and the like. VBat estimation may include, for example, programmability including decoupling capacitors that may provide short-term charging requirements before the battery needs to be charged, which may allow for optimization by overdrinking the signal if not needed. The predictive controller 1100 may also receive temperature information from one or more thermal monitors—this information may be used with each of the power predictions of the transducer inputs and the cumulative effects of battery state to reduce transducer driver or regulator power consumption. The temperature measurements may be instantaneous or averaged over a programmable time period and considered with a programmable hysteresis threshold.
Fig. 15b is a simplified block-level representation of elements (e.g., like hardware and/or firmware and/or software) for monitoring and controlling aspects of digital and/or analog output signals for driving respective loads (not shown), including their respective signal paths and/or associated blocks and/or other components or systems of a host device incorporating digital and/or analog output driver circuits (not all of which may be shown for clarity of explanation). Fig. 15b shows circuitry for receiving voltage from a voltage supply (e.g. like a battery) for controlling one or more signal paths, the circuitry comprising a controller configured to receive voltage data and/or thermal data and/or signal data from the one or more signal paths, wherein each path comprises a respective transducer driver. The controller is further configured to output control data to one or more of the signal paths for controlling one or more characteristics of respective signals in the one or more respective signal paths. The controller is preferably a predictive controller, i.e. a look-ahead controller, for controlling one or more characteristics of the received voltage and/or heat and/or signal data based on one or more aspects of these signals before outputting the respective signals in one or more respective signal paths from their respective transducer drivers, in order to mitigate or avoid adverse voltage and/or heat and/or signal conditions associated with at least the circuitry.
Fig. 16 illustrates an exemplary transducer event (e.g., haptic output) that may require high dynamic power, which may result in a reduced or "roll-off" battery power supply. Estimating the signal power of any and each transducer by a metric based on one or more look-ahead signal and/or load characteristics and: a current battery supply level; a supply decoupling capacitor; and/or using knowledge of the battery RC dynamics (based on some or all battery parameters, such as state of charge, state of health, and temperature, etc.), the future supply voltage VBat may be predicted F . This information may be used to limit the output transducer signal power by adjusting one or more parameters of the signal (e.g., attenuating the signal level) prior to applying the signal to its respective load, for example, to avoid a power down condition, and/or to compensate for supply transients to give a consistent output power level, and/or to reduce on-chip/system thermal heating.
Referring to fig. 17, if the transducer output signal PWMOut-X, analogueOut-X is sufficiently aggressive, it may be possible to completely avoid transient events by biasing the corresponding transducer output signal PWMOut-X, analogueOut-X. In the case that the transducer output signal can be additionally adjusted, i.e. with a further delay of small duration (by adding a further waiting time to the signal) without causing any user influence or any perceptible effect When the transducer output signal coincides with one or more other transducer outputs in a lower power favorable state, there is an opportunity to output an additionally delayed signal without signal conditioning, control or adjustment. Such signal delay or skew is preferably applied before the signal is applied to the transducer rather than during the application of the signal to the transducer. If the signal deviates or delays, the deviation/delay indicates that it is necessary for an ongoing power prediction. In the example shown in fig. 17, additionally the delayed signal S IN_DEL+ The use of (C) is beneficial to S IN_DEL Because of the input signal A IN The associated transducer is in an advantageously low power state.
As will be apparent from the above discussion, the circuitry of the present disclosure provides a mechanism for dynamically compensating for variations in the supply voltage applied to the digital output driver circuitry such that for a desired operating state of a load, the average voltage (or equivalently, the average power) supplied to a load (e.g., transducer or electronic circuitry) driven by the digital output driver circuitry per cycle remains substantially constant, thereby maintaining a consistent load output. The circuitry of the present disclosure is capable of compensating for both transient changes in the available supply voltage (which may result from, for example, current drawn from the power supply by other components or subsystems of the host device incorporating digital output driver circuitry) and long-term changes in the available supply voltage (which may result from, for example, the discharge of a battery over time).
Embodiments may be implemented as integrated circuit system (e.g., an integrated circuit (e.g., a monolithic integrated circuit), or as multiple integrated circuits (e.g., multiple monolithic integrated circuits), each implementing a portion of the above circuitry or system), which in some examples may be a codec or an audio DSP or the like. Embodiments may be incorporated into an electronic device, which may be, for example, a portable device and/or a device that may be battery-powered. The device may be a communication device such as a mobile phone or a smart phone or the like. The device may be a computing device, such as a notebook, laptop, or tablet computing device. The device may be a wearable device, such as a smart watch. The device may be a device with voice control or activation functions, such as a smart speaker. In some cases, the device may be an accessory device, such as a headset, an earpiece, a headset, an earplug, etc., to be used with some other product.
The skilled person will appreciate that some aspects of the above described apparatus and methods, e.g. discovery and configuration methods, may be embodied as processor control code, e.g. on a non-volatile carrier medium such as a magnetic disk, CD-or DVD-ROM, a programmed memory such as read only memory (firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications, the implementation will be on a DSP (digital signal processor), an ASIC (application specific integrated circuit) or an FPGA (field programmable gate array). Thus, the code may comprise conventional program code or microcode, or code for example, to set up or control an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device, such as a reconfigurable array of logic gates. Similarly, code may include code for a hardware description language (such as Verilog TM Or VHDL (very high speed integrated circuit hardware description language)). The skilled person will appreciate that the code may be distributed among a plurality of coupling components in communication with each other. Implementations may also be implemented using code that runs on a field (re) programmable analog array or similar device to configure analog hardware, where appropriate.
It should be noted that the above-mentioned embodiments illustrate rather than limit the embodiments, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, and "a" or "an" does not exclude a plurality, and a single feature or other unit may fulfill the functions of several units recited in the claims; and circuitry is intended to include use of hardware, firmware, and/or software (including combinations thereof). Any reference signs or marks in the claims should not be construed as limiting their scope.

Claims (29)

1. A system, comprising:
a power regulator or controller associated with the transducer;
one or more processors or controllers for controlling the power regulator or controller; and
A look-ahead controller configured to monitor control and/or data signals from the one or more processors or controllers of the system, the look-ahead controller configured to adjust transducer output power based on supply voltage levels and the monitored control and/or data signals.
2. The system of claim 1, wherein the look-ahead controller is configured to adjust the transducer output power to:
reducing or avoiding a power down condition; and/or
Providing a consistent output level; and/or
Reducing the cumulative output power requirement.
3. A circuit system, comprising:
one or more signal paths, each of the one or more signal paths configured to carry a signal for driving a load;
controller circuitry configured to receive data from at least one of the one or more signal paths and to output control data to one or more of the one or more signal paths for controlling one or more characteristics of the signals carried by the one or more of the one or more signal paths.
4. A circuit system according to claim 3, wherein the data received by the controller circuitry from the at least one of the one or more signal paths comprises voltage data and/or thermal data and/or signal data.
5. The circuitry of claim 3 or 4, wherein the controller circuitry comprises look-ahead controller circuitry.
6. The circuitry of any of claims 3 to 5, wherein the one or more signal paths comprise an analog signal path and/or a digital signal path.
7. The circuitry of any of claims 3 to 6, wherein each of the one or more signal paths comprises transducer driver circuitry.
8. The circuitry of any of claims 3 to 7, wherein the controller circuitry is configured to output control data to limit signal power of the load associated with the one or more of the one or more signal paths.
9. The circuitry of claim 8, wherein the control data is configured to cause attenuation of the signal carried by the one or more of the one or more signal paths.
10. The circuitry of any of claims 3 to 9, wherein the controller circuitry is configured to output control data to delay signals in one or more of the one or more signal paths.
11. A circuit system, comprising:
one or more driver signal paths, each driver signal path associated with a load for providing a drive signal to the load; and
advanced circuitry configured to
Receiving signal data from a driver signal path;
estimating a power demand of a load coupled to the driver signal path based on the signal data and/or characteristics of the load;
predicting a future supply voltage based at least in part on the estimated power demand, the power supply parameter; and
parameters of signals in one or more of the driver signal paths are adjusted based on the predicted future supply voltage.
12. The circuitry of claim 11, wherein the power supply parameters comprise one or more of:
a measure of the current battery supply level;
a supply decoupling capacitor; and
the battery RC is dynamic.
13. The circuitry of claim 12, wherein the battery RC dynamics are based on battery parameters comprising one or more of:
a state of charge;
a state of health; and
temperature.
14. Circuitry to receive a voltage from a voltage supply for controlling one or more signal paths, comprising a controller configured to receive:
Voltage data relating to at least the circuitry; and/or
Thermal data relating to at least the circuitry; and/or
Signal data from the one or more signal paths, wherein each signal path includes a respective transducer driver,
wherein the circuitry is configured to output control data to the one or more signal paths to control one or more characteristics of respective signals in the one or more respective signal paths, wherein the controller is a predictive controller for controlling one or more characteristics of the respective signals in the one or more respective signal paths based on one or more of the received data before the respective signals are output from their respective transducer drivers, so as to mitigate or avoid adverse voltage and/or heat and/or signal conditions associated with at least the circuitry.
15. The circuitry of claim 14, wherein the adverse voltage condition is a voltage supply power down condition.
16. The circuitry of claim 15, wherein the adverse thermal condition is an undesirable thermal heating of the circuitry or other components or systems of a host device incorporating the circuitry.
17. The circuitry of any of claims 15 to 16, wherein the voltage data originates from a battery monitor and/or a voltage monitor.
18. The circuitry of claim 17, wherein the battery monitor is configured to monitor a battery parameter.
19. The circuitry of claim 18, wherein the battery parameter comprises one or more of a state of charge of the battery, a state of health of the battery, and/or a parasitic element of and/or associated with the battery.
20. The circuitry of any of claims 15 to 19, wherein the thermal data originates from one or more thermal monitors.
21. The circuitry of any of claims 15 to 20, wherein the signal data originates from one or more points along the one or more signal paths.
22. The circuitry of any one of claims 15 to 21, wherein the control data controls:
at least one signal parameter in a respective signal path, wherein the controlled at least one signal parameter is input to the controller; or alternatively
Gain of at least one signal in the respective signal path.
23. The circuitry of any of claims 15 to 22, wherein the circuitry provides a consistent power output.
24. The circuitry of any of claims 15 to 23, wherein the controller outputs a total predicted power demand signal.
25. The circuitry of claim 26, wherein the total predicted power demand signal is input to a battery controller.
26. A system, comprising:
a plurality of driver circuits, each configured to output a driving signal for driving a load;
a power supply for providing a supply voltage to the plurality of driver circuits; and
a predictive controller configured to regulate, control or adjust a parameter of one or more of the drive signals based on a level of the supply voltage.
27. A system, comprising:
driver circuitry for driving a first transducer and a second transducer, wherein the first transducer comprises an audio transducer and the second transducer comprises a haptic transducer;
a power supply for providing a supply voltage to the driver circuitry; and
A predictive controller configured to regulate, control, or adjust parameters of one or more drive signals output by the driver circuitry based on a level of the supply.
28. A device comprising the circuitry of any of claims 3-25 or the system of any of claims 1-2 or 26-27, wherein the device comprises a computer game controller, a Virtual Reality (VR) or Augmented Reality (AR) device, a goggle, a mobile phone, a tablet or laptop computer, an accessory device, an earpiece, an earphone, a headset, or a battery powered device.
29. An integrated circuit system comprising the system of any one of claims 3 to 25 or any one of claims 1 to 2 or 26 to 27, wherein the integrated circuit system comprises one integrated circuit or a plurality of integrated circuits.
CN202180064066.5A 2020-09-11 2021-09-10 Driver circuitry Pending CN116235130A (en)

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US6791481B2 (en) * 2000-05-18 2004-09-14 Echo Mobile Music, Llc Portable CD-ROM/ISO to HDD/MP3 recorder with simultaneous CD-Read/MP3-Encode/HDD-Write, or HDD-Read/MP3-Decode, to play, power saving buffer, and enhanced sound output
US7446822B2 (en) * 2002-05-15 2008-11-04 Symbol Technologies, Inc. High-resolution image projection
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