CN116234382A

CN116234382A - Display substrate, display panel and display device

Info

Publication number: CN116234382A
Application number: CN202310078659.8A
Authority: CN
Inventors: 卢辉; 刘珂; 张振华; 石领; 刘畅畅; 刘烺; 谢帅
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-09-16
Filing date: 2021-09-16
Publication date: 2023-06-06
Also published as: CN114823835B; CN114823835A; CN113793864A

Abstract

The display substrate comprises a first display area, wherein the first display area comprises a plurality of pixel islands and a light transmission area positioned among the pixel islands, the pixel islands comprise pixel circuits, and the pixel circuits comprise a plurality of signal lines; between the pixel islands, at least part of the signal lines are made of metal wires. The present disclosure can better realize high-frequency display.

Description

Display substrate, display panel and display device

The present application is a divisional application of patent application 202111088853.1, the application date of the original application is 2021, 9, 16 and 202111088853.1, and the invention is named as a display substrate, a preparation method thereof and a display panel.

Technical Field

The embodiment of the disclosure relates to the field of display technology, and in particular relates to a display substrate, a display panel and a display device.

Background

With the development of technology, the appearance of mobile terminals is receiving more and more attention, wherein a large screen terminal with a relatively large screen occupation ratio is gradually one of the mainstream designs of the mobile terminals. The large-screen terminal can promote game entertainment experience of a user, is favorable for split-screen display, and is higher in technological sense of the whole machine, so that stronger visual impact can be brought to the user.

Currently, full screen display has become a mainstream trend of mobile phone display. The comprehensive screen compresses the design space of devices such as a camera, an infrared sensor and a receiver, and the devices such as the camera, the infrared sensor and the like are arranged below the display screen, so that the display device has potential to be designed.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate, a display panel and a display device, which can better realize high-frequency display.

The embodiment of the disclosure provides a display substrate, which comprises a first display area, a second display area and a first display area, wherein the first display area comprises a plurality of first sub-pixels and a light transmission area positioned among the plurality of first sub-pixels, the first sub-pixels comprise pixel circuits, and the pixel circuits comprise a plurality of signal lines; in the light-transmitting area of the first display area, at least part of the signal wires are made of transparent wires, and in the area outside the light-transmitting area of the first display area, at least part of the signal wires are made of metal wires.

The embodiment of the disclosure also provides a display substrate, which comprises a first display area, wherein the first display area comprises a plurality of pixel islands and a light transmission area positioned among the pixel islands; the pixel island includes a pixel circuit including a plurality of signal lines; between the pixel islands, at least part of the signal lines are made of metal wires.

In some exemplary embodiments, the plurality of signal lines includes a scan signal line, a data signal line, a first power line, an initial signal line, and a light emitting signal line, wherein:

the scanning signal line, the data signal line, the first power line and the initial signal line are all metal wires.

In some exemplary embodiments, the display substrate includes a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate;

in the first display area, the first power line and the data signal line are located on different conductive layers, and an overlapping area exists between the orthographic projection of the first power line on the substrate and the orthographic projection of the data signal line on the substrate.

In some exemplary embodiments, the display substrate includes a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate; the scanning signal line comprises a first scanning signal line and a second scanning signal line, and the first scanning signal line and the second scanning signal line are positioned on different conductive layers;

the pixel circuit includes a drive sub-circuit, a data write sub-circuit, and a first reset sub-circuit, the drive sub-circuit configured to generate a drive current between a second node and a third node under control of a first node; the data writing sub-circuit is configured to write a data signal to a second node under the control of the first scanning signal line; the first reset sub-circuit is configured to reset the first node under the control of the second scanning signal line;

In the first display area, an overlapping area exists between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate.

In some exemplary embodiments, in the first display region, the second scan signal line extends along a first direction, the second scan signal line includes bending portions disposed at intervals, the bending portions extend along a second direction, and the first direction intersects the second direction.

In some exemplary embodiments, in the first display region, there is a region where the orthographic projection of the initial signal line on the substrate overlaps with the orthographic projection of the first scanning signal line on the substrate and/or the orthographic projection of the second scanning signal line on the substrate.

In some exemplary embodiments, the display substrate includes a base and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source drain metal layer, a first transparent conductive layer, and a second source drain metal layer sequentially disposed on the base on a plane perpendicular to the display substrate;

the semiconductor layer includes active layers of a plurality of transistors, at least one of the first and second gate metal layers includes the second scan signal line, the first source drain metal layer includes the initial signal line and the first power line, and the second source drain metal layer includes the data signal line.

In some exemplary embodiments, each of the pixel islands includes at least one first sub-pixel, and the semiconductor layer in the first sub-pixel of each column is staggered with the semiconductor layer in the first sub-pixel of an adjacent column in a row direction.

In some exemplary embodiments, in the first display region, the first scan signal line includes a plurality of branches, the first transparent conductive layer includes a fourteenth connection electrode and a fifteenth connection electrode, the first source drain metal layer includes a sixth connection electrode and a seventh connection electrode, and the first gate metal layer includes a first connection electrode;

the sixth connecting electrode and the seventh connecting electrode are respectively and electrically connected with two ends of the first connecting electrode through a via hole, the fourteenth connecting electrode is electrically connected with the seventh connecting electrode through a via hole, and the fifteenth connecting electrode is electrically connected with the sixth connecting electrode through a via hole;

each branch of the first scanning signal line is electrically connected with a fourteenth connection electrode and a fifteenth connection electrode in two adjacent first sub-pixels in the same row through a via hole respectively.

In some exemplary embodiments, in the first display region, the initial signal line includes a plurality of branches, and the second gate metal layer includes a third connection electrode;

Each branch of the initial signal line is electrically connected with the third connecting electrode in the adjacent two first sub-pixels in the same row through the via hole.

In some exemplary embodiments, in the first display region, the first power line includes a plurality of branches, the display substrate further includes an eleventh connection electrode and a twelfth connection electrode, and the second source drain metal layer includes a seventeenth connection electrode;

the seventeenth connection electrode is electrically connected with the eleventh connection electrode and the twelfth connection electrode through the through holes respectively, and each branch of the first power line is electrically connected with the eleventh connection electrode and the twelfth connection electrode in two adjacent first sub-pixels in the same column through the through holes respectively.

In some exemplary embodiments, the pixel islands include a plurality of metal layers therebetween, and an overlap region exists between at least two metal layers.

The embodiment of the disclosure also provides a display substrate, which comprises a first display area, wherein the first display area comprises a plurality of pixel units and a light transmission area positioned among the pixel units; the pixel unit includes a pixel circuit including a plurality of signal lines; and between the pixel units, at least part of the signal wires are made of metal wires.

In some exemplary embodiments, at least one of the plurality of pixel units includes a first light emitting unit emitting light of a first color, a second light emitting unit emitting light of a second color, and a third light emitting unit emitting light of a third color, the first light emitting unit, the second light emitting unit, and the third light emitting unit being arranged in a zigzagged manner.

The embodiment of the disclosure also provides a display panel, including: a display substrate as in any of the embodiments of the present disclosure.

The disclosure also provides a display device comprising a display panel according to any one of the embodiments of the disclosure and a photosensitive element overlapping the first display region.

According to the display substrate, the display panel and the display device, the high-frequency display is better realized by enabling part of signal wires of the first display area to be made of metal materials, and in addition, the occupation area of the metal wires of the first display area is effectively reduced by overlapping the wires through various signal wires, the light transmittance of the first display area is increased, and the photographing functions of the front-end camera such as self photographing and face recognition are improved. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a pixel arrangement structure of the display panel shown in FIG. 2;

fig. 4 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 4;

fig. 6a is a schematic plan view of a display substrate according to an embodiment of the disclosure;

FIG. 6b is a cross-sectional view taken along the line A-A in FIG. 6 a;

fig. 7 is a schematic structural diagram of a semiconductor layer of a display substrate according to an embodiment of the disclosure;

Fig. 8 is a schematic structural diagram of a first conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of a second conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 10 is a schematic structural diagram of a fourth insulating layer of a display substrate according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of a third conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a fifth insulating layer of a display substrate according to an embodiment of the disclosure;

fig. 13 is a schematic structural diagram of a fourth conductive layer of a display substrate according to an embodiment of the disclosure;

fig. 14 is a schematic structural diagram of a first flat layer of a display substrate according to an embodiment of the disclosure;

fig. 15 is a schematic structural diagram of a fifth conductive layer of a display substrate according to an embodiment of the disclosure.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of each constituent element, the thickness of a layer, or a region may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

Fig. 1 is a schematic structural diagram of a display panel. As shown in fig. 1, the OLED display panel may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, which may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of subpixels Pxij. In some exemplary embodiments, the timing controller may supply a gray value and a control signal suitable for a specification of the data signal driver to the data signal driver, may supply a clock signal, a scan start signal, etc. suitable for a specification of the scan signal driver to the scan signal driver, and may supply a clock signal, an emission stop signal, etc. suitable for a specification of the light emitting signal driver to the light emitting signal driver. The data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using the gray values and the control signals received from the timing controller. For example, the data signal driver may sample the gray value with a clock signal, and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register, and may generate the scan signal in such a manner that the scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, and m may be a natural number. The light emitting signal driver may generate the emission signals to be supplied to the light emitting signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emission signal driver may sequentially supply the emission signal having the off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission signal driver may be configured in the form of a shift register, and may generate the light emission signal in such a manner that the light emission stop signal supplied in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. The subpixel Pxij may refer to a subpixel in which a transistor is connected to the ith scan signal line and to the jth data signal line.

Fig. 2 is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the display panel provided in the embodiment of the invention includes a first display area 100 and a second display area 200, where the first display area 100 includes a plurality of first sub-pixels and a plurality of light-transmitting areas, and the second display area 200 includes a plurality of second sub-pixels, and the first sub-pixels satisfy at least one of the following: the distribution density of the first sub-pixel is smaller than that of the second sub-pixel, and the occupied area of the first sub-pixel is smaller than that of the second sub-pixel. The area of the light transmission area in the first display area 100 is increased by reducing the distribution density of the first sub-pixels in the first display area 100 or reducing the area occupied by the first sub-pixels, so that the imaging structure can be arranged in the light transmission area, the first display area 100 can be used for displaying, the screen occupation ratio of the display area is improved, imaging can be performed through the light transmission area, and various requirements of users are met.

In some exemplary embodiments, the relative positional relationship between the first display area 100 and the second display area 200 may be such that at least part of the sides of the first display area 100 coincides with at least part of the sides of the second display area 200, and the rest of the first display area 100 is surrounded by the second display area 200, so that the first display area 100 may be disposed at the edge of the display panel display area. In other exemplary embodiments, the relative positional relationship between the second display area 200 and the first display area 100 may be such that the second display area 200 surrounds the first display area 100, and thus, the first display area 100 may be disposed inside the display panel display area, as shown in fig. 2. For example, the first display area 100 may be disposed at the upper left corner of the second display area 200. For another example, the first display area 100 may be disposed at the upper right corner of the second display area 200. For another example, the first display area 100 may be disposed at the left side of the second display area 200. For another example, the first display area 100 may be disposed at an upper side of the second display area 200. Of course, in practical applications, the specific position of the first display area 100 may be determined according to the practical application environment, which is not limited herein.

In an actual implementation, the shape of the first display area 100 may be set to a regular shape, such as a rectangle, whose top corner may be a right angle, or whose top corner may also be an arc-shaped corner. For another example, the first display area 20 may be configured in a trapezoid shape, which may be a positive trapezoid or an inverted trapezoid. In addition, the vertex angle of the trapezoid can be a normal included angle or can also be an arc-shaped angle. For another example, the shape of the first display area 100 may be set to an irregular shape. For example, the shape of the first display area 100 may be set to a drop shape. Of course, in practical applications, the shape of the first display area 100 may be designed according to the shape of the element disposed in the first display area 100, which is not limited herein.

In some exemplary embodiments, the area of the first display area 100 is smaller than the area of the second display area 200. Of course, in practical applications, the design may be performed according to the elements disposed in the first display area 100, which is not limited herein.

Fig. 3 is a schematic diagram of an arrangement structure of a pixel array according to an exemplary embodiment of the present disclosure. As shown in fig. 3, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first light emitting unit P1 emitting light of a first color, a second light emitting unit P2 emitting light of a second color, and a third light emitting unit P3 emitting light of a third color, and each of the first, second, and third light emitting units P1, P2, and P3 includes a pixel driving circuit and a light emitting element. The pixel driving circuits in the first, second and third light emitting units P1, P2 and P3 are connected to the scan signal line, the data signal line and the light emitting signal line, respectively, and the pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light emitting element under the control of the scan signal line and the light emitting signal line. The light emitting elements in the first, second and third light emitting units P1, P2 and P3 are respectively connected to the pixel driving circuits of the light emitting units, and the light emitting elements are configured to emit light of corresponding brightness in response to the current output from the pixel driving circuits of the light emitting units.

In an exemplary embodiment, the pixel unit P may include therein a red (R), green (G) and blue (B) light emitting unit, or may include therein a red, green, blue and white light emitting unit, which is not limited herein. In an exemplary embodiment, the shape of the light emitting unit in the pixel unit may be rectangular, diamond, pentagon, or hexagon. When the pixel unit includes three light emitting units, the three light emitting units may be arranged in a horizontal parallel, vertical parallel or delta manner, and when the pixel unit includes four light emitting units, the four light emitting units may be arranged in a horizontal parallel, vertical parallel or Square (Square) manner, which is not limited herein.

In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 4 is an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 4, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and a plurality of signal lines (data signal line D, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power supply line VDD, second power supply line VSS, and emission control signal line E).

In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2. The gate electrode of the fifth transistor T5 is connected to the emission control signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the emission control signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode of the light emitting element). The gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 or the Reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. The first terminal of the storage capacitor C is connected to the first power line VDD, and the second terminal of the storage capacitor C is connected to the first node N1.

In some exemplary embodiments, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The same type of transistor is adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include a P-type transistor and an N-type transistor.

In some exemplary embodiments, the second pole of the light emitting element is connected to the second power line VSS, the signal of the second power line VSS is continuously providing a low level signal, and the signal of the first power line VDD is continuously providing a high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), and the second scanning signal line S2 of the display line and the first scanning signal line S1 in the pixel driving circuit of the previous display line may be the same signal line, so as to reduce signal lines of the display panel and realize a narrow frame of the display panel.

In some exemplary embodiments, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT all extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

In some exemplary embodiments, the light emitting element may be an Organic Light Emitting Diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

Fig. 5 is a timing diagram illustrating an operation of the pixel driving circuit shown in fig. 4. The exemplary embodiment of the present disclosure will be described below by the operation of the pixel driving circuit illustrated in fig. 5, which includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C1, and 7 signal lines (DATA signal line DATA, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power supply line VDD, second power supply line VSS, and light emitting signal line EM), and the 7 transistors are P-type transistors.

In an exemplary embodiment, the operation of the pixel driving circuit may include:

the first phase A1, referred to as a reset phase, signals of the second scanning signal line S2 are low-level signals, and signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low level signal, so that the first transistor T1 is turned on, the signal of the initial signal line INIT is provided to the first node N1, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The signals of the first scan signal line S1 and the light emitting signal line E are high level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light at this stage.

The second phase A2, called a data writing phase or a threshold compensation phase, the signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs a data voltage. At this stage, since the second terminal of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on such that the data voltage outputted from the data signal line D is supplied to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the sum of the data voltage outputted from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second end (second node N2) of the storage capacitor C is vdata+vth, vdata is the data voltage outputted from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal line INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, empty the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scanning signal line S2 is a high level signal, and turns off the first transistor T1. The signal of the light-emitting signal line E is a high level signal, and turns off the fifth transistor T5 and the sixth transistor T6.

The third stage A3 is referred to as a light-emitting stage, in which the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light emitting signal line E is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage outputted from the first power supply line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, thereby driving the OLED to emit light.

During driving of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is vdata+vth, the driving current of the third transistor T3 is:

I＝K*(Vgs-Vth) ² ＝K*[(Vdata+Vth-Vdd)-Vth] ² ＝K*[(Vdata–Vdd)] ²

where I is a driving current flowing through the third transistor T3, that is, a driving current for driving the OLED, K is a constant, vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, vth is a threshold voltage of the third transistor T3, vdata is a data voltage output from the data signal line D, and Vdd is a power supply voltage output from the first power supply line Vdd.

As can be seen from the above formula, the current I flowing through the light emitting element is independent of the threshold voltage Vth of the third transistor T3, the influence of the threshold voltage Vth of the third transistor T3 on the current I is eliminated, and the uniformity of brightness is ensured.

Based on the working time sequence, the pixel circuit eliminates residual positive charges of the light emitting element after the last light emission, realizes the compensation of the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light emitting element, and improves the uniformity of the display image and the display quality of the display panel.

In the conventional pixel circuit design, the signal lines between the pixel circuits of the first display area are connected through transparent Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) traces, but the transparent ITO or IZO traces have large resistance values, which is very unfavorable for the application of high-frequency display.

Fig. 6a is a schematic structural diagram of a display substrate in a first display area according to an embodiment of the disclosure, and fig. 6b is a cross-sectional view taken along A-A in fig. 6 a. As shown in fig. 6a and 6b, in the first display area, a plurality of first sub-pixels include pixel circuits (located in the non-light-transmitting area), the pixel circuits include a plurality of signal lines, adjacent pixel circuits are connected to each other through the signal lines, and each signal line is used for providing different signals for the pixel circuits; at least part of signal wires are transparent wires in a light-transmitting area of the first display area; at least part of the signal wires are metal wires in the area except the light-transmitting area of the first display area.

In some exemplary embodiments, the plurality of signal lines include a scan signal line, a data signal line D, a first power line VDD, an initial signal line INIT, and a light emitting signal line E. The scan signal line is used for providing a scan signal for the pixel circuit, the data signal line D is used for providing a data signal for the pixel circuit, the first power line VDD is used for providing a first power signal for the pixel circuit, the initial signal line INIT is used for providing an initial signal for the pixel circuit, and the light-emitting signal line E is used for providing a light-emitting control signal for the pixel circuit.

In some exemplary embodiments, the scan signal line, the data signal line D, the first power line VDD, and the initial signal line INIT are all metal wirings, and the light emitting signal line E is a transparent wiring.

In some exemplary embodiments, the display substrate includes a base 90 and a plurality of conductive layers on the base 90 in a plane perpendicular to the display substrate, the scan signal lines include a first scan signal line S1 and a second scan signal line S2, and the first scan signal line S1 and the second scan signal line S2 are on different conductive layers.

In some exemplary embodiments, the pixel circuit includes a drive sub-circuit, a data write sub-circuit, and a first reset sub-circuit, the drive sub-circuit configured to generate a drive current between the second node and the third node under control of the first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scanning signal line S1; the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line S2.

In some exemplary embodiments, the first scan signal line S1 and the second scan signal line S2 are both metal wirings.

Because the loads of the signal wires such as the first scanning signal wire S1, the second scanning signal wire S2, the data signal wire D, the first power wire VDD and the initial signal wire INIT have a large influence on high frequency, the display substrate of the embodiment of the disclosure changes the ITO wires of the signal wires such as the first scanning signal wire S1, the second scanning signal wire S2, the data signal wire D, the first power wire VDD and the initial signal wire INIT into conventional metal wires, and reduces the resistance of the signal wires, thereby being beneficial to better performing high frequency display in the first display area; in addition, since the light emitting signal line E has less influence on high frequency display, transparent conductive wirings such as indium tin oxide ITO or indium zinc oxide IZO are still used without modification.

In some exemplary embodiments, as shown in fig. 7 to 15, the display substrate includes a base and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source drain metal layer, a first transparent conductive layer, and a second source drain metal layer sequentially disposed on the base in a plane perpendicular to the display substrate;

The semiconductor layer includes active layers of a plurality of transistors, at least one of the first and second gate metal layers includes a second scan signal line S2, the first source drain metal layer includes an initial signal line INIT and a first power line VDD, the first transparent conductive layer includes a light emitting signal line E, and the second source drain metal layer includes a first scan signal line S1 and a data signal line D.

In some exemplary embodiments, as shown in fig. 7, the first display region includes a plurality of columns of first sub-pixels, and the semiconductor layer in the first sub-pixel of each column is staggered with the semiconductor layer in the first sub-pixel of an adjacent column in the first direction X.

In some exemplary embodiments, as shown in fig. 6a, in the first display region, there is an overlapping region between the orthographic projection of the first scan signal line S1 on the substrate and the orthographic projection of the second scan signal line S2 on the substrate. In this embodiment, by overlapping the first scan signal line S1 and the second scan signal line S2, the influence of the metal wiring on the transmittance can be reduced to the greatest extent.

In some exemplary embodiments, as shown in fig. 8, in the first display region, the second scan signal line S2 extends along a first direction X (horizontal direction), the second scan signal line S2 includes bending portions disposed at intervals, the bending portions extend along a second direction Y (vertical direction), and the first direction X and the second direction Y are orthogonal.

In some exemplary embodiments, as shown in fig. 7 to 15, in the first display region, the first scan signal line includes a plurality of branches, the first transparent conductive layer includes a fourteenth connection electrode 44 and a fifteenth connection electrode 45, the first source drain metal layer includes a sixth connection electrode 33 and a seventh connection electrode 34, and the first gate metal layer includes the first connection electrode 11;

the sixth connection electrode 33 and the seventh connection electrode 34 are electrically connected to both ends of the first connection electrode 11 through vias, respectively, the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through a via, and the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through a via;

each branch of the first scan signal line S1 is electrically connected to the fourteenth connection electrode 44 and the fifteenth connection electrode 45 in the adjacent two first sub-pixels of the same row through a via hole, respectively.

In some exemplary embodiments, as shown in fig. 7 to 15, in the first display region, there is a region where three of the front projection of the first scan signal line S1 on the substrate, the front projection of the initial signal line INIT on the substrate, and the front projection of the second scan signal line S2 on the substrate overlap. In this embodiment, in order to reduce signal crosstalk caused by the stacked signal lines of the signals of both the first scanning signal line S1 and the second scanning signal line S2, the display substrate of the embodiment of the disclosure uses the intermediate layer of the two signal lines to walk the initial signal line INIT (direct current signal), thereby shielding the influence of the crosstalk to the greatest extent.

In some exemplary embodiments, in the first display region, the initial signal line INIT includes a plurality of branches, and the second gate metal layer includes the third connection electrode 21; each branch of the initial signal line INIT is electrically connected to the third connection electrode 21 in the adjacent two first sub-pixels of the same row through the via hole, respectively.

In some exemplary embodiments, as shown in fig. 6a, in the first display region, there is an overlapping region of the front projection of the first power line VDD on the substrate and the front projection of the data signal line D on the substrate. In this embodiment, by overlapping the first power line VDD and the data signal line D, the influence of the metal wiring on the transmittance can be reduced to the greatest extent.

In some exemplary embodiments, as shown in fig. 11 to 15, in the first display region, the first power line VDD includes a plurality of branches, the first transparent conductive layer includes an eleventh connection electrode 41 and a twelfth connection electrode 42, and the second source-drain metal layer includes a seventeenth connection electrode 51;

the seventeenth connection electrode 51 is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 through vias, respectively, and each branch of the first power line VDD is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 in the adjacent two first sub-pixels of the same column through vias, respectively.

The structure of the display substrate according to the embodiment of the present disclosure is exemplified below through a process of manufacturing the display substrate. The "patterning process" referred to in this disclosure includes processes such as depositing a film, coating a photoresist, mask exposing, developing, etching, and stripping the photoresist. The deposition may be any one or more selected from sputtering, evaporation and chemical vapor deposition, the coating may be any one or more selected from spray coating and spin coating, and the etching may be any one or more selected from dry etching and wet etching. "film" refers to a layer of film made by depositing or coating a material onto a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process throughout the fabrication process. When the "thin film" is also subjected to a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The phrase "a and B are co-layer disposed" in this disclosure means that a and B are formed simultaneously by the same patterning process. "the front projection of A includes the front projection of B" means that the front projection of B falls within the front projection range of A, or that the front projection of A covers the front projection of B.

In some exemplary embodiments, the preparation process of the display substrate shown in fig. 6a and 6b may include the steps of:

(1) A semiconductor layer pattern is formed on the substrate 90. Forming the semiconductor layer pattern on the substrate 90 includes: an insulating film is deposited on the substrate 90 to form a first insulating layer 91 pattern covering the entire substrate 90. An active layer film is then deposited, and patterned by a patterning process to form a semiconductor layer pattern disposed on the first insulating layer 91, as shown in fig. 7. The semiconductor layer pattern of the first display region may include the active layer 10 of the first transistor T1, the active layer 20 of the second transistor T2, the active layer 30 of the third transistor T3, the active layer 40 of the fourth transistor T4, the active layer 50 of the fifth transistor T5, the active layer 60 of the sixth transistor T6, and the active layer 70 of the seventh transistor T7. In some exemplary embodiments, the first, second, third, fourth, fifth, sixth, and seventh

active layers

10, 20, 30, 40, 50, 60, and 70 may be an integrally connected structure.

In some exemplary embodiments, the first active layer 10 may have a shape of a door frame, and the second active layer 20 may have a shape of a door frame

The third active layer 30 may have a shape of a "several" and the fourth active layer 40 may have a shape of a "1", the fifth and sixth

active layers

50 and 60 may have a shape of an "L", and the seventh active layer 70 may have a shape of a dumbbell.

In some example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In some exemplary embodiments, the second region 102 of the first active layer 10 serves as the second region 202 of the second active layer 20 at the same time, i.e., the second region 102 of the first active layer 10 and the second region 202 of the second active layer 20 are connected to each other. The first region 301 of the third active layer 30 serves as both the second region 402 of the fourth active layer 40 and the second region 502 of the fifth active layer 50, i.e., the first region 301 of the third active layer 30, the second region 402 of the fourth active layer 40, and the second region 502 of the fifth active layer 50 are connected to each other. The second region 302 of the third active layer 30 serves as both the first region 601 of the sixth active layer 60 and the first region 201 of the second active layer 20, i.e., the second region 302 of the third active layer 30, the first region 601 of the sixth active layer 60, and the first region 201 of the second active layer 20 are connected to each other. The first region 101 of the first active layer 10 simultaneously serves as the first region 701 of the seventh active layer 70, i.e., the first region 101 of the first active layer 10 and the first region 701 of the seventh active layer 70 are connected to each other. The first region 401 of the fourth active layer 40, the first region 501 of the fifth active layer 50, the second region 602 of the sixth active layer 60, and the second region 702 of the seventh active layer 70 are separately provided.

In some exemplary embodiments, in the first display area 100, the plurality of first sub-pixels includes two or more columns, and the semiconductor layer of the first sub-pixel of each column is staggered with the semiconductor layer of the first sub-pixel of an adjacent column in the first direction. By staggering the semiconductor layers of the first sub-pixels of adjacent columns in the first direction, the pitch (Margin) of the semiconductor layers of the first sub-pixels of adjacent columns in the first direction is increased so that the light transmitting area for imaging on both sides of the first sub-pixels is larger.

In some exemplary embodiments, the semiconductor layer may employ polysilicon (p-Si), i.e., the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be LTPS thin film transistors.

After this process, the display substrate includes a first insulating layer 91 disposed on the base 90 and a semiconductor layer disposed on the first insulating layer 91, which may include active layers of a plurality of transistors.

(2) A first conductive layer pattern is formed. In some exemplary embodiments, forming the first conductive layer pattern may include: a second insulating film and a first metal film are sequentially deposited on the substrate 90 on which the foregoing patterns are formed, the first metal film is patterned by a patterning process to form a second insulating layer 92 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 92, the first conductive layer pattern of the first display region at least includes: the second scan signal line S2, the first connection electrode 11, the second connection electrode 12, and the first plate Ce1 of the storage capacitor, as shown in fig. 8. In some exemplary embodiments, the first conductive layer may be referred to as a first GATE metal (GATE 1) layer.

In the embodiment of the disclosure, the second scanning signal line S2 of the first display area is a metal wire, so that the influence of the wire load on high-frequency display can be reduced, and the first display area can better realize high-frequency display.

In some exemplary embodiments, the second scan signal line S2 is located at a side of the first connection electrode 11 away from the first plate Ce1 of the storage capacitor, and the first plate Ce1 of the storage capacitor is disposed between the first connection electrode 11 and the second connection electrode 12 within each sub-pixel.

In some exemplary embodiments, a region of the second scan signal line S2 overlapping the first active layer of the first transistor T1 serves as a gate electrode of the first transistor T1 dual gate structure.

In some exemplary embodiments, in the first display area 100, the second scan signal line S2 is of a polyline structure. Since the semiconductor layer of the first sub-pixel of each column and the semiconductor layer of the first sub-pixel of the adjacent column are staggered in the first direction in the first display area 100, and the second scan signal line S2 and the first active layer of the first transistor T1 in one row of the first sub-pixels include overlapping regions, the second scan signal line S2 has a zigzag structure.

In some exemplary embodiments, a region of the first connection electrode 11 overlapping with the fourth active layer of the fourth transistor T4 serves as a gate electrode of the fourth transistor T4. The first connection electrode 11 is provided with a gate block 11-1 protruding toward one side of the second scan signal line S2, and an overlapping region exists between the orthographic projection of the gate block 11-1 on the substrate 90 and the orthographic projection of the second active layer of the second transistor T2 on the substrate 90, and a region where the first connection electrode 11 and the gate block 11-1 overlap with the second active layer of the second transistor T2 serves as a gate electrode of the double gate structure of the second transistor T2. A region of the first connection electrode 11 overlapping with the seventh active layer of the seventh transistor T7 serves as a gate electrode of the seventh transistor T7. Namely, the gate electrode of the second transistor T2, the gate electrode of the fourth transistor T4, and the gate electrode of the seventh transistor T7 are connected to each other in an integrated structure.

In some exemplary embodiments, a region of the second connection electrode 12 overlapping the fifth active layer of the fifth transistor T5 serves as a gate electrode of the fifth transistor T5, and a region of the second connection electrode 12 overlapping the sixth active layer of the sixth transistor T6 serves as a gate electrode of the sixth transistor T6. Namely, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 are connected to each other in an integrated structure.

In some exemplary embodiments, the first plate Ce1 may have a rectangular shape, corners of the rectangular shape may be provided with chamfers, and an overlapping region exists between an orthographic projection of the first plate Ce1 on the substrate 90 and an orthographic projection of the third active layer of the third transistor T3 on the substrate 90. In some exemplary embodiments, the first plate Ce1 is simultaneously used as a gate electrode of the third transistor T3, and a region of the third transistor T3 where the third active layer overlaps with the first plate Ce1 is used as a channel region of the third transistor T3, where one end of the channel region is connected to the first region of the third active layer and the other end is connected to the second region of the third active layer.

In some exemplary embodiments, after the first conductive layer pattern is formed, the semiconductor layer may be subjected to a conductive treatment using the first conductive layer as a mask, the semiconductor layer of the region masked by the first conductive layer forms a channel region of each transistor, and the semiconductor layer of the region not masked by the first conductive layer is conductive, i.e., both the first region and the second region of each active layer are conductive.

After this process, the display substrate includes a first insulating layer 91 disposed on the base 90, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a first conductive layer disposed on the second insulating layer 92, where the first conductive layer may include a second scan signal line S2, a first connection electrode 11, a second connection electrode 12, and a first plate Ce1 of a storage capacitor.

(3) And forming a second conductive layer pattern. In some exemplary embodiments, forming the second conductive layer pattern may include: a third insulating film and a second metal film are sequentially deposited on the substrate 90 on which the foregoing patterns are formed, the second metal film is patterned by a patterning process to form a third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93, the second conductive layer pattern of the first display region at least includes: the second plate Ce2 and the third connection electrode 21 of the storage capacitor are shown in fig. 9. In some exemplary embodiments, the second conductive layer may be referred to as a second GATE metal (GATE 2) layer.

In some exemplary embodiments, in each sub-pixel, the third connection electrode 21 is located at a side of the second scan signal line S2 remote from the first connection electrode 11, and the third connection electrode 21 is used to connect the initial signal line INIT formed later.

In some exemplary embodiments, the profile of the second plate Ce2 may be rectangular with a notch H, and corners of the rectangular may be chamfered, such that there is an overlap area between the orthographic projection of the second plate Ce2 onto the substrate 90 and the orthographic projection of the first plate Ce1 onto the substrate 90. The notch H may be located at a corner of the second plate Ce 2. The notch H may be polygonal, the notch H exposes the third insulating layer covering the first plate Ce1, and the front projection of the first plate Ce1 on the substrate 90 overlaps the front projection of the notch H on the substrate 90. In some exemplary embodiments, the notch H is configured to receive a subsequently formed third via, which is located within the notch H and exposes the first plate Ce1, connecting the second pole of the subsequently formed second transistor T2 with the first plate Ce 1.

After this process, the display substrate includes a first insulating layer 91 disposed on the base 90, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, a first conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the first conductive layer, and a second conductive layer disposed on the third insulating layer 93, the second conductive layer including at least a second electrode Ce2 of the storage capacitor and a third connection electrode 21.

(4) The fourth insulating layer 94 is patterned. Forming the fourth insulating layer 94 pattern includes: on the substrate 90 having the above structure, a fourth insulating film is deposited, and patterned by a patterning process to form a fourth insulating layer 94 pattern having a plurality of via holes including: the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth vias V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, and V14 are shown in fig. 10.

In an exemplary embodiment, the fourth insulating layer within the first via hole V1 is etched away, exposing a surface of the second plate Ce2 of the storage capacitor, configured such that the second branch VDD-B2 of the subsequently formed first power line VDD is electrically connected to the second plate Ce2 of the storage capacitor through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via hole V2 are etched away to expose the surface of the first region 501 of the fifth active layer, and configured such that the second branch VDD-B2 of the first power line VDD formed later is connected to the first region 501 of the fifth active layer through the via hole.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the third via hole V3 are etched away to expose the surface of the first plate Ce1 of the storage capacitor, and the fourth connection electrode 31 formed later is configured to be electrically connected to the first plate Ce1 of the storage capacitor through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing a surface of the second region 102 of the first active layer (also the second region 202 of the second active layer), configured to connect the second pole of the subsequently formed first transistor T1 with the first active layer through the via, and to connect the second pole of the subsequently formed second transistor T2 with the second active layer through the via.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the second region 702 of the seventh active layer, configured such that the subsequently formed fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the via.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region 602 of the sixth active layer, configured to electrically connect the subsequently formed fifth connection electrode 32 with the second region 602 of the sixth active layer through the via.

In an exemplary embodiment, the fourth insulating layer within the seventh via hole V7 is etched away, exposing a surface of one end of the third connection electrode 21, configured such that the first branch INIT-B1 of the initial signal line INIT formed later is electrically connected to one end of the third connection electrode 21 through the via hole.

In an exemplary embodiment, the fourth insulating layer in the eighth via hole V8 is etched away to expose a surface of the other end of the third connection electrode 21, and the second branch INIT-B2 of the initial signal line INIT formed later is configured to be electrically connected to the other end of the third connection electrode 21 through the via hole.

In one exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the ninth via V9 are etched away, exposing the surface of the first region 101 of the first active layer (also the first region 701 of the seventh active layer), configured such that the subsequently formed initial signal line is electrically connected to the first region 101 of the first active layer (also the first region 701 of the seventh active layer) through the via.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the tenth via hole V10 are etched away, exposing a surface of one end of the first connection electrode 11, configured such that the subsequently formed sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the via hole.

In an exemplary embodiment, the fourth insulating layer within the eleventh via hole V11 is etched away to expose a surface of the other end of the first connection electrode 11, and is configured such that a seventh connection electrode 34 to be formed later is electrically connected to the other end of the first connection electrode 11 through the via hole.

In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the first region 401 of the fourth active layer, configured such that the eighth connection electrode 35 formed later is electrically connected to the first region 401 of the fourth active layer through the via.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the thirteenth via hole V13 are etched away to expose a surface of one end of the second connection electrode 12, and configured such that a ninth connection electrode 36 to be formed later is electrically connected to one end of the second connection electrode 12 through the via hole.

In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the fourteenth via hole V14 are etched away to expose a surface of the other end of the second connection electrode 12, and configured such that a tenth connection electrode 37 to be formed later is electrically connected to the other end of the second connection electrode 12 through the via hole.

(5) And forming a third conductive layer pattern. In some exemplary embodiments, forming the third conductive layer may include: on the substrate 90 on which the foregoing pattern is formed, a third metal thin film is deposited, and the third metal thin film is patterned using a patterning process to form a third conductive layer disposed on the fourth insulating layer 94. As shown in fig. 11, the third conductive layer of the first display region may include a first branch VDD-B1 of the first power line VDD, a second branch VDD-B2 of the first power line VDD, a first branch INIT-B1 of the initial signal line INIT, a second branch INIT-B2 of the initial signal line INIT, a fourth connection electrode 31, a fifth connection electrode 32, a sixth connection electrode 33, a seventh connection electrode 34, an eighth connection electrode 35, a ninth connection electrode 36, and a tenth connection electrode 37. In some example embodiments, the third conductive layer may be referred to as a first source drain metal (SD 1) layer.

In the embodiment of the disclosure, the first power line VDD and the initial signal line INIT of the first display area are made to be metal wires, so that the influence of the wire load on high-frequency display can be reduced, and the first display area can better realize high-frequency display.

In some exemplary embodiments, the first branch VDD-B1 of the first power line VDD is electrically connected to the second branch VDD-B2 of the first power line VDD through a plurality of vias and a plurality of connection electrodes (herein, the plurality of vias includes a fifteenth via V15, a sixteenth via V16, a twenty sixth via, and a twenty seventh via V27) formed later, the plurality of connection electrodes including an eleventh connection electrode 41, a twelfth connection electrode 42, and a seventeenth connection electrode 51.

In some exemplary embodiments, the second branch VDD-B2 of the first power line VDD is electrically connected to the second plate Ce2 of the storage capacitor through the first via V1 and to the first region 501 of the fifth active layer through the second via V2, so that the first pole of the fifth transistor T5 has the same potential as the first power line VDD.

In some exemplary embodiments, the first branch VDD-B1 of the first power line VDD is electrically connected to the second branch VDD-B2 of the first power line VDD in the present subpixel through a plurality of vias and a plurality of connection electrodes formed later, on the one hand, and extends toward the previous subpixel of the column in which the present subpixel is located, as the second branch VDD-B2 of the first power line VDD in the previous subpixel of the column in which the present subpixel is located, on the other hand.

In some exemplary embodiments, the second branch VDD-B2 of the first power line VDD is electrically connected to the first branch VDD-B1 of the first power line VDD in the present subpixel through a plurality of vias and a plurality of connection electrodes formed later, on the one hand, and extends to the next subpixel of the column in which the present subpixel is located, as the first branch VDD-B1 of the first power line VDD in the next subpixel of the column in which the present subpixel is located, on the other hand.

In some exemplary embodiments, the first branch INIT-B1 of the initial signal line INIT is connected to one end of the third connection electrode 21 through the seventh via hole V7, and the second branch INIT-B2 of the initial signal line INIT is connected to the other end of the third connection electrode 21 through the eighth via hole V8. In this embodiment, the electrical connection between the first branch INIT-B1 of the initial signal line INIT and the second branch INIT-B2 of the initial signal line INIT is achieved through the third connection electrode 21, the seventh via hole V7 and the eighth via hole V8.

In some exemplary embodiments, the second branch INIT-B2 of the initial signal line INIT is connected to the first region 101 of the first active layer (also the first region 701 of the seventh active layer) through the ninth via hole V9 such that the first electrode of the first transistor T1 (also the first electrode of the seventh transistor T7) has the same potential as the first initial signal line INIT 1.

In some exemplary embodiments, the first branch INIT-B1 of the initial signal line INIT is electrically connected to the second branch INIT-B2 of the initial signal line INIT within the present sub-pixel through the third connection electrode 21 on the one hand, and extends toward the previous sub-pixel of the present sub-pixel row on the other hand, as the second branch INIT-B2 of the initial signal line INIT in the previous sub-pixel of the present sub-pixel row.

In some exemplary embodiments, the second branch INIT-B2 of the initial signal line INIT is electrically connected to the first branch INIT-B1 of the initial signal line INIT within the present sub-pixel through the third connection electrode 21 on the one hand, and extends toward the next sub-pixel of the present sub-pixel row on the other hand, as the first branch INIT-B1 of the initial signal line INIT in the next sub-pixel of the present sub-pixel row.

In some exemplary embodiments, there is an overlap region between the front projection of the first branch INIT-B1 of the initial signal line INIT and the front projection of the second branch INIT-B2 of the initial signal line INIT on the substrate and the front projection of the second scan signal line S2 on the substrate.

In some exemplary embodiments, the fourth connection electrode 31 is electrically connected to the first plate Ce1 of the storage capacitor through the third via V3 and to the second region 102 of the first active layer (also the second region 202 of the second active layer) through the fourth via V4. In some exemplary embodiments, the fourth connection electrode 31 may serve as the second pole of the first transistor T1 and the second pole of the second transistor T2.

In some exemplary embodiments, the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via V5 and connected to the second region 602 of the sixth active layer through the sixth via V6. In some exemplary embodiments, the fifth connection electrode 32 may serve as the second pole of the seventh transistor T7 and the second pole of the sixth transistor T6.

In some exemplary embodiments, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via hole V10.

In some exemplary embodiments, the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through the eleventh via hole V11.

In some exemplary embodiments, the eighth connection electrode 35 is electrically connected to the first region 401 of the fourth active layer through the twelfth via V12. In some exemplary embodiments, the eighth connection electrode 35 may serve as the first pole of the fourth transistor T4.

In some exemplary embodiments, the ninth connection electrode 36 is electrically connected to one end of the second connection electrode 12 through a thirteenth via hole V13.

In some exemplary embodiments, the tenth connection electrode 37 is electrically connected to the other end of the second connection electrode 12 through a fourteenth via hole V14.

(6) A fifth insulating layer 95 pattern is formed. Forming the fifth insulating layer 95 pattern includes: a fifth insulating film is coated on the substrate 90 on which the foregoing patterns are formed, and a fifth insulating layer 95 pattern covering the third conductive layer is formed through a photolithography process of mask exposure and development, and the fifth insulating layer 95 of the first display region is opened with a tenth fifth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty first via V21, and a twenty second via V22, as shown in fig. 12.

In some exemplary embodiments, the fifth insulating layer within the fifteenth via hole V15 is etched away, exposing a surface of the second branch VDD-B2 of the first power line VDD, configured such that the eleventh connection electrode 41 formed later is electrically connected to the second branch VDD-B2 of the first power line VDD through the via hole.

In some exemplary embodiments, the fifth insulating layer within the sixteenth via hole V16 is etched away, exposing a surface of the first branch VDD-B1 of the first power line VDD, configured to electrically connect the twelfth connection electrode 42 formed later to the first branch VDD-B1 of the first power line VDD through the via hole.

In some exemplary embodiments, the fifth insulating layer within the seventeenth via hole V17 is etched away, exposing a surface of the ninth connection electrode 36, configured to electrically connect the first branch E-B1 of the light emitting signal line E formed later with the ninth connection electrode 36 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the eighteenth via hole V18 is etched away, exposing a surface of the tenth connection electrode 37, configured to electrically connect the second branch E-B2 of the light emitting signal line E formed later with the tenth connection electrode 37 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the nineteenth via V19 is etched away exposing a surface of the fifth connection electrode 32 configured to electrically connect a thirteenth connection electrode 43 to be formed later with the fifth connection electrode 32 through the via.

In some exemplary embodiments, the fifth insulating layer within the twentieth via V20 is etched away exposing a surface of the seventh connection electrode 34, configured to electrically connect the fourteenth connection electrode 44 formed later with the seventh connection electrode 34 through the via.

In some exemplary embodiments, the fifth insulating layer within the twenty-first via hole V21 is etched away, exposing a surface of the sixth connection electrode 33, configured to electrically connect the fifteenth connection electrode 45 formed later with the sixth connection electrode 33 through the via hole.

In some exemplary embodiments, the fifth insulating layer within the twenty-second via V22 is etched away, exposing a surface of the eighth connection electrode 35, configured to electrically connect the sixteenth connection electrode 46 formed later with the eighth connection electrode 35 through the via.

(7) And forming a fourth conductive layer pattern. In some example embodiments, forming the fourth conductive layer may include: on the substrate 90 on which the foregoing pattern is formed, a first transparent conductive film is deposited, and the first transparent conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer 95. As shown in fig. 13, the fourth conductive layer of the first display region may include a first branch E-B1 of the light emitting signal line E, a second branch E-B2 of the light emitting signal line E, an eleventh connection electrode 41, a twelfth connection electrode 42, a thirteenth connection electrode 43, a fourteenth connection electrode 44, a fifteenth connection electrode 45, and a sixteenth connection electrode 46. In some exemplary embodiments, the fourth conductive layer may be referred to as a first transparent conductive layer.

In the embodiment of the disclosure, the light transmittance of the camera area is increased and the imaging effect is improved by using the transparent conductive material for the light-emitting signal line E of the first display area; meanwhile, the signal load of the light-emitting signal line E has small influence on high-frequency display, so that the light-emitting signal line E adopts transparent conductive materials and does not influence the effect of high-frequency display.

In some exemplary embodiments, the first branch E-B1 of the light emitting signal line E is electrically connected to one end of the second connection electrode 12 within the present subpixel through the seventeenth via V17, and extends to the previous subpixel of the present subpixel row, and is electrically connected to the other end of the second connection electrode 12 in the previous subpixel of the present subpixel through the eighteenth via V18 in the previous subpixel of the present subpixel row.

In some exemplary embodiments, the second branch E-B2 of the light emitting signal line E is electrically connected to the other end of the second connection electrode 12 within the present subpixel through the eighteenth via V18 on the one hand, and extends to the next subpixel of the present subpixel row on the other hand, and is electrically connected to one end of the second connection electrode 12 in the next subpixel of the present subpixel row through the seventeenth via V17 in the next subpixel of the present subpixel row.

In the present embodiment, the electrical connection of the first branch E-B1 of the light emitting signal line E and the second branch E-B2 of the light emitting signal line E is achieved through the second connection electrode 12, the seventeenth via hole V17, and the eighteenth via hole V18.

In some exemplary embodiments, the eleventh connection electrode 41 is electrically connected to the second branch VDD-B2 of the first power line VDD through the fifteenth via hole V15.

In some exemplary embodiments, the twelfth connection electrode 42 is electrically connected to the first branch VDD-B1 of the first power line VDD through the sixteenth via V16.

In some exemplary embodiments, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through a nineteenth via V19.

In some exemplary embodiments, the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via V20.

In some exemplary embodiments, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via hole V21.

In some exemplary embodiments, the sixteenth connection electrode 46 is electrically connected to the eighth connection electrode 35 through a twenty-second via V22.

(8) A first planarization layer 96 pattern is formed. Forming the first planarization layer 96 pattern includes: a first flat film is deposited on the substrate 90 on which the foregoing pattern is formed, and patterned by a patterning process to form a first flat layer 96 disposed on the fourth conductive layer, where the first flat layer 96 is provided with a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27, and a twenty-eighth via V28, the thirteenth via V13 exposes the fourth connection line L4, and the fourteenth via V14 exposes the seventh connection line L7, as shown in fig. 14.

In some exemplary embodiments, the first planarization layer within the twenty-third via hole V23 is etched away, exposing a surface of the fourteenth connection electrode 44, configured such that the first branch S1-B1 of the first scan signal line S1 formed later is electrically connected to the fourteenth connection electrode 44 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-fourth via hole V24 is etched away, exposing a surface of the fifteenth connection electrode 45, configured such that the second branch S1-B2 of the first scan signal line S1 formed later is electrically connected to the fifteenth connection electrode 45 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-fifth via hole V25 is etched away, exposing a surface of the sixteenth connection electrode 46, configured to electrically connect the data signal line D formed later to the sixteenth connection electrode 46 through the via hole.

In some exemplary embodiments, the first planarization layer within the twenty-sixth via V26 is etched away, exposing a surface of the twelfth connection electrode 42, configured to electrically connect the seventeenth connection electrode 51 formed later with the twelfth connection electrode 42 through the via.

In some exemplary embodiments, the first planarization layer within the twenty-seventh via hole V27 is etched away, exposing a surface of the eleventh connection electrode 41, configured to electrically connect the seventeenth connection electrode 51 formed later with the eleventh connection electrode 41 therethrough.

In some exemplary embodiments, the first planarization layer within the twenty-eighth via V28 is etched away, exposing a surface of the thirteenth connection electrode 43, configured to electrically connect the eighteenth connection electrode 52 formed later with the thirteenth connection electrode 43 through the via.

(9) And forming a fifth conductive layer pattern. Forming the fifth conductive layer may include: on the substrate 90 on which the foregoing pattern is formed, a fifth metal film is deposited, and the fifth metal film is patterned using a patterning process to form a fifth conductive layer disposed on the first planarization layer. As shown in fig. 15, the fifth conductive layer of the first display region may include a first branch S1-B1 of the first scan signal line S1, a second branch S1-B2 of the first scan signal line S1, a data signal line D, a seventeenth connection electrode 51, and an eighteenth connection electrode 52. In some example embodiments, the fifth conductive layer may be referred to as a second source drain metal (SD 2) layer.

In the embodiment of the disclosure, the first scanning signal line S1 and the data signal line D of the first display area are made to be metal wires, so that the influence of the wire load on high-frequency display can be reduced, and the first display area can better realize high-frequency display.

In some exemplary embodiments, the first branch S1-B1 of the first scan signal line S1 is electrically connected to the fourteenth connection electrode 44 in the present subpixel through the twenty-third via V23 on the one hand, and extends to the previous subpixel in the present subpixel row on the other hand, and is electrically connected to the fifteenth connection electrode 45 in the previous subpixel in the present subpixel row through the twenty-fourth via V24 in the previous subpixel in the present subpixel row.

In some exemplary embodiments, the second branch S1-B2 of the first scan signal line S1 is electrically connected to the fifteenth connection electrode 45 within the present subpixel through the twenty-fourth via V24 on the one hand, and extends to the next subpixel of the present subpixel row on the other hand, and is electrically connected to the fourteenth connection electrode 44 in the next subpixel of the present subpixel row through the twenty-third via V23 in the next subpixel of the present subpixel row.

Since the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via hole V20, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via hole V21, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via hole V10, and the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through the eleventh via hole V11, the electrical connection between the first branch S1-B1 of the first scan signal line S1 and the second branch S1-B2 of the first scan signal line S1 is achieved.

In some exemplary embodiments, there is an overlap region of the front projection of the first branch S1-B1 of the first scan signal line S1 on the substrate 90 and the front projection of the first branch INIT-B1 of the initial signal line INIT on the substrate 90, and there is an overlap region of the front projection of the second branch S1-B2 of the first scan signal line S1 on the substrate 90 and the front projection of the second branch INIT-B2 of the initial signal line INIT on the substrate 90.

In some exemplary embodiments, there is an overlap region between the front projection of the first branch S1-B1 of the first scan signal line S1 and the second branch S1-B2 of the first scan signal line S1 on the substrate 90 and the front projection of the second scan signal line S2 on the substrate 90.

In some exemplary embodiments, there is an overlapping region of the front projections of the first branch S1-B1 of the first scan signal line S1, the first branch INIT-B1 of the initial signal line INIT, and the second scan signal line S2 on the substrate 90, and there is an overlapping region of the front projections of the second branch S1-B2 of the first scan signal line S1, the second branch INIT-B2 of the initial signal line INIT, and the second scan signal line S2 on the substrate 90.

In the embodiment of the disclosure, by making the orthographic projections of both the first scanning signal line S1 and the second scanning signal line S2 on the substrate 90 have an overlapping region, the influence of the metal wiring on the transmittance can be reduced to the greatest extent, the transmittance of the first display area is higher, and the shooting performance is better. By arranging the initial signal line INIT between the first scanning signal line S1 and the second scanning signal line S2, signal crosstalk between the first scanning signal line S1 and the second scanning signal line S2 can be reduced, and further, high-frequency display can be better realized in the first display area, and display quality is greatly improved.

In some exemplary embodiments, the data signal line D is electrically connected to the sixteenth connection electrode 46 through a twenty-fifth via V25. Since the sixteenth connection electrode 46 is electrically connected to the eighth connection electrode 35 through the twenty-second via hole V22, the eighth connection electrode 35 is electrically connected to the first region 401 of the fourth active layer through the twelfth via hole V12, thereby achieving an electrical connection of the data signal line to the first pole of the fourth transistor, so that the data signal transmitted by the data signal line D can be written into the fourth transistor.

In some exemplary embodiments, there is an overlapping area of orthographic projections of the data signal line D, the first branch VDD-B1 of the first power line VDD, and the second branch VDD-B2 of the first power line VDD on the substrate 90.

In the embodiment of the disclosure, by enabling the orthographic projections of the data signal line D and the first power line VDD on the substrate to have an overlapping region, the influence of the metal wiring on the transmittance can be reduced to the greatest extent, the transmittance of the first display area is higher, and the shooting performance is better. In addition, the first power line VDD can shield signal crosstalk generated by the metal wiring below the third conductive layer to the data signal line D, so that the first display area can better realize high-frequency display, and display quality is greatly improved.

In some exemplary embodiments, the seventeenth connection electrode 51 is electrically connected to the twelfth connection electrode 42 through the twenty-sixth via V26 on the one hand, and to the eleventh connection electrode 41 through the twenty-seventh via V27 on the other hand. Since the twelfth connection electrode 42 is electrically connected to the first branch VDD-B1 of the first power line VDD through the sixteenth via hole V16, the eleventh connection electrode 41 is electrically connected to the second branch VDD-B2 of the first power line VDD through the fifteenth via hole V15, and thus, the electrical connection of the first branch VDD-B1 of the first power line VDD and the second branch VDD-B2 of the first power line VDD is achieved.

In some exemplary embodiments, the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through the twenty eighth via V28.

(10) The second flat layer 97 is patterned. In some exemplary embodiments, forming the second planarization layer 97 pattern may include: on the substrate 90 with the above pattern, a second flat film is coated, and the second flat film is patterned by a patterning process to form a second flat layer 97 covering the fifth conductive layer, and at least twenty-nine vias V29 are disposed on the second flat layer 97 of the first display area, as shown in fig. 6 a.

In some exemplary embodiments, the twenty-ninth via V29 is located in the region of the eighteenth connection electrode 52, the second planarization layer within the twenty-ninth via V29 is removed, exposing the surface of the eighteenth connection electrode 52, and the twenty-ninth via V29 is configured to electrically connect a subsequently formed anode to the eighteenth connection electrode 52 therethrough.

(11) In some exemplary embodiments, forming the anode pattern may include: on the substrate 90 on which the foregoing pattern is formed, a transparent conductive film is deposited, and the transparent conductive film is patterned using a patterning process to form an anode electrode disposed on the second planarization layer 97.

In some exemplary embodiments, in the first display region, the anode is connected to the eighteenth connection electrode 52 through a twenty-ninth via V29. Since the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through the twenty-eighth via hole V28, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through the nineteenth via hole V19, the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via hole V5, and is connected to the second region 602 of the sixth active layer through the sixth via hole V6, it is realized that the pixel circuit can drive the light emitting element to emit light.

In some exemplary embodiments, the subsequent preparation process may include: the pixel definition film is coated, the pixel definition film is patterned by a patterning process to form a Pixel Definition Layer (PDL), and the pixel definition layer of each sub-pixel is provided with a sub-pixel opening (Subpixel Apertures, SA) exposing the anode. An organic light-emitting layer is formed by vapor deposition or an inkjet printing process, and a cathode is formed on the organic light-emitting layer. The packaging layer is formed, the packaging layer can comprise a first packaging layer, a second packaging layer and a third packaging layer which are stacked, the first packaging layer and the third packaging layer can be made of inorganic materials, the second packaging layer can be made of organic materials, the second packaging layer is arranged between the first packaging layer and the third packaging layer, and external water vapor can not enter the light-emitting structure layer.

In some exemplary embodiments, the substrate 90 may be a flexible substrate, or may be a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass, quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In some exemplary embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, the first flexible material layer and the second flexible material layer may be made of Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like, for improving the water-oxygen resistance of the substrate, and the semiconductor layer may be made of amorphous silicon (a-si).

In some exemplary embodiments, the first, second, third, and fifth conductive layers may be made of a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may be a single-layer structure, or a multi-layer composite structure such as Mo/Cu/Mo, or the like. The fourth conductive layer and the anode can be made of transparent conductive materials such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The first, second, third, fourth and fifth insulating layers may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer is called a Buffer (BUF) layer for improving the water-oxygen resistance of the substrate, the second insulating layer is called a first gate insulating (GI 1) layer, the third insulating layer is called a second gate insulating (GI 2) layer, the fourth insulating layer is called an interlayer Insulating (ILD) layer, and the fifth insulating layer is called a Passivation (PVX) layer. The first planar (PLN 1) layer and the second planar (PLN 2) layer may be made of an organic material. The semiconductor layer may be polysilicon (p-Si) or oxide.

According to the display substrate, the ITO wiring of the signal wiring such as the first scanning signal line S1, the second scanning signal line S2, the data signal line D, the first power line VDD and the initial signal line INIT is changed into the conventional metal wiring, so that the resistance of the signal wiring is reduced, the high-frequency display of the first display area is facilitated, in addition, the metal wiring occupation area of the first display area is effectively reduced through the overlapping wiring of various signal lines, the light transmittance of the first display area is increased, and the shooting functions such as self-timer, face recognition and the like of the front-end camera are improved. In addition, the preparation process disclosed by the invention can be well compatible with the existing preparation process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost and high in yield.

The structure of the display substrate and the manufacturing process thereof shown in the present disclosure are merely exemplary, and in some exemplary embodiments, the corresponding structure may be changed and patterning processes may be added or subtracted according to actual needs, which is not limited herein. The structure of the display substrate and the manufacturing process thereof shown in the present disclosure are described by taking the pixel circuit of 8T1C shown in fig. 3 as an example, and in other exemplary embodiments, the pixel circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, or 7T1C structure, which is not limited in the present disclosure.

The disclosure further provides a method for manufacturing a display substrate, where the display substrate includes a first display area, the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels, the first sub-pixels include pixel circuits, and the pixel circuits include a plurality of signal lines. In some exemplary embodiments, the method of manufacturing a display substrate may include the steps of:

forming a semiconductor layer on a substrate;

forming a first gate metal layer on the semiconductor layer;

forming a second gate metal layer on the first gate metal layer;

forming a first source drain metal layer on the second gate metal layer;

forming a first transparent conductive layer on the first source drain metal layer;

forming a second source drain metal layer on the first transparent conductive layer; in the light-transmitting area of the first display area, the first transparent conductive layer is used for routing at least part of signal lines; and at least one layer of the first gate metal layer, the second gate metal layer, the first source drain metal layer and the second source drain metal layer is used for routing at least part of the signal lines in the area outside the light transmission area of the first display area.

The display substrate prepared by the preparation method of the display substrate provided by the disclosure has similar implementation principle and implementation effect as those of the display substrate, and is not described herein again.

The display panel comprises the display substrate, the polaroid arranged on the light emitting side of the display substrate, the cover plate, the supporting layer arranged on the backlight side of the display substrate, the heat dissipation layer and the like. The display panel may be used to: the embodiment of the invention is not limited to any product or component with display function such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

While the embodiments disclosed in this disclosure are described above, the embodiments are only used for facilitating understanding of the disclosure, and are not intended to limit the present invention. Any person skilled in the art will recognize that any modifications and variations can be made in the form and detail of the present disclosure without departing from the spirit and scope of the disclosure, which is defined by the appended claims.

Claims

1. A display substrate, comprising a first display region, wherein the first display region comprises a plurality of pixel islands and a light-transmitting region positioned between the plurality of pixel islands;

The pixel island includes a pixel circuit including a plurality of signal lines;

between the pixel islands, at least part of the signal lines are made of metal wires.

2. The display substrate according to claim 1, wherein the plurality of signal lines include a scan signal line, a data signal line, a first power line, an initial signal line, and a light emitting signal line, wherein:

3. The display substrate according to claim 2, wherein the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate;

4. The display substrate according to claim 2, wherein the display substrate comprises a base and a plurality of conductive layers on the base in a plane perpendicular to the display substrate; the scanning signal line comprises a first scanning signal line and a second scanning signal line, and the first scanning signal line and the second scanning signal line are positioned on different conductive layers;

5. The display substrate according to claim 4, wherein in the first display region, the second scan signal lines extend along a first direction, the second scan signal lines include bending portions disposed at intervals, the bending portions extend along a second direction, and the first direction intersects the second direction.

6. The display substrate according to claim 4, wherein in the first display region, there is a region where the orthographic projection of the initial signal line on the substrate overlaps with the orthographic projection of the first scanning signal line on the substrate and/or the orthographic projection of the second scanning signal line on the substrate.

7. The display substrate according to claim 4, wherein the display substrate comprises a base and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source drain metal layer, and a second source drain metal layer sequentially disposed on the base on a plane perpendicular to the display substrate;

8. The display substrate of claim 7, wherein each of the pixel islands comprises at least one first subpixel, and the semiconductor layers in the first subpixel of each column are staggered with the semiconductor layers in the first subpixel of an adjacent column in a row direction.

9. The display substrate according to claim 7, wherein in the first display region, the initial signal line includes a plurality of branches, and the second gate metal layer includes a third connection electrode;

10. The display substrate according to claim 7, wherein in the first display region, the first power line includes a plurality of branches, the display substrate further includes an eleventh connection electrode and a twelfth connection electrode, and the second source drain metal layer includes a seventeenth connection electrode; the seventeenth connection electrode is electrically connected with the eleventh connection electrode and the twelfth connection electrode through the through holes respectively, and each branch of the first power line is electrically connected with the eleventh connection electrode and the twelfth connection electrode in two adjacent first sub-pixels in the same column through the through holes respectively.

11. The display substrate of claim 1, wherein the pixel islands comprise a plurality of metal layers therebetween, and wherein an overlap region exists between at least two metal layers.

12. A display substrate, comprising a first display region, wherein the first display region comprises a plurality of pixel units and a light transmission area positioned among the pixel units;

the pixel unit includes a pixel circuit including a plurality of signal lines;

and between the pixel units, at least part of the signal wires are made of metal wires.

13. The display substrate according to claim 12, wherein at least one of the plurality of pixel units includes a first light emitting unit emitting light of a first color, a second light emitting unit emitting light of a second color, and a third light emitting unit emitting light of a third color, the first light emitting unit, the second light emitting unit, and the third light emitting unit being arranged in a zigzagged manner.

14. A display panel, comprising: a display substrate according to any one of claims 1 to 13.

15. A display device comprising the display panel of claim 14 and a photosensitive element overlapping the first display region.