CN116230747A

CN116230747A - Semiconductor structure

Info

Publication number: CN116230747A
Application number: CN202111476083.8A
Authority: CN
Inventors: 陈志谚; 钒达·卢; 孙健仁; 连羿韦; 王端玮; 陈俊扬
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2021-12-06
Filing date: 2021-12-06
Publication date: 2023-06-06

Abstract

A semiconductor structure includes a substrate, a seed layer, an epitaxially grown layer, and a superlattice structure. The seed layer is disposed on the substrate, the epitaxial growth layer is disposed over the seed layer, and the superlattice structure is disposed between the seed layer and the epitaxial growth layer. The superlattice structure comprises a plurality of superlattice units stacked in a staggered manner, and two adjacent superlattice units comprise a first superlattice unit and a second superlattice unit, wherein the first superlattice unit comprises a first superlattice layer and a second superlattice layer stacked on the first superlattice unit, the second superlattice unit comprises a third superlattice layer and a fourth superlattice layer stacked on the third superlattice layer, the first superlattice layer comprises a (1-1) th sublayer and a (1-2) th sublayer in a plurality of pairs, and the second superlattice layer comprises a (2-1) th sublayer and a (2-2) th sublayer in a plurality of pairs.

Description

Semiconductor structure

Technical Field

The present invention relates to the field of semiconductor devices, and more particularly to a semiconductor structure including a superlattice structure.

Background

In semiconductor technology, group III-V compound semiconductors may be used to form a variety of integrated circuit devices, such as: high power field effect transistors, high frequency transistors or high electron mobility transistors (high electron mobility transistor, HEMT). HEMTs are a type of transistor with two-dimensional electron gas (two dimensional electron gas, 2-DEG) that is adjacent to the junction between two materials that differ in energy gap (i.e., the heterojunction). Since HEMTs do not use doped regions as the carrier channel of the transistor, but rather use 2-DEG as the carrier channel of the transistor, HEMTs have a variety of attractive characteristics compared to existing Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as: high electron mobility and the ability to transmit signals at high frequencies.

The conventional HEMT may include a channel layer, a barrier layer, a compound semiconductor cap layer, and a gate electrode stacked in this order. The grid electrode is utilized to apply bias to the compound semiconductor cover layer, so that the two-dimensional electron gas concentration in the channel layer below the compound semiconductor cover layer can be regulated and controlled, and further the switching of the HEMT can be regulated and controlled.

The stress generated by lattice mismatch is usually avoided between the HEMT stack and the substrate by the superlattice layer, however, the conventional superlattice layer still cannot meet the requirement of stress control, so that the substrate and the HEMT stack warp, and the degree of the warp changes correspondingly with the thickness of the superlattice layer, which not only increases the difficulty of the manufacturing process, but also reduces the electrical performance of the HEMT.

Disclosure of Invention

In view of the foregoing, there is a need for a semiconductor structure including an improved superlattice structure to enhance the stress control effect of the superlattice structure, thereby improving the electrical performance and the manufacturing yield of HEMTs.

According to one embodiment of the present invention, a semiconductor structure is provided that includes a substrate, a seed layer, an epitaxially grown layer, and a superlattice structure. The seed layer is arranged on the substrate, the epitaxial growth layer is arranged above the seed layer, and the superlattice structure is arranged between the seed layer and the epitaxial growth layer, wherein the superlattice structure comprises a plurality of superlattice units which are stacked in a staggered manner, and two adjacent superlattice units comprise a first superlattice unit and a second superlattice unit, and the second superlattice unit is stacked on the first superlattice unit. The first superlattice unit comprises a first superlattice layer and a second superlattice layer, wherein the first superlattice layer comprises a plurality of pairs of (1-1) th sub-layers and (1-2) th sub-layers, and the second superlattice layer is stacked on the first superlattice layer and comprises a plurality of pairs of (2-1) th sub-layers and (2-2) th sub-layers. The second superlattice unit includes a third superlattice layer and a fourth superlattice layer, wherein the fourth superlattice layer is stacked on the third superlattice layer. The third superlattice layer includes a plurality of pairs of (3-1) th and (3-2) th sublayers, and the fourth superlattice layer includes a plurality of pairs of (4-1) th and (4-2) th sublayers. Wherein the aluminum atom concentration of the (2-2) th sub-layer is higher than that of the (1-2) th sub-layer.

In order to make the features of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

For easier understanding, reference is made to the drawings and their detailed description when reading the present invention. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the various features of the invention. Moreover, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and thus the dimensions of some features in some of the drawings may be exaggerated or reduced on purpose.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a superlattice structure in accordance with an embodiment of the invention.

Fig. 3 is a schematic cross-sectional view of a superlattice repeating unit in accordance with an embodiment of the invention.

Fig. 4 is a schematic cross-sectional view of a superlattice structure in accordance with another embodiment of the invention.

Fig. 5 is a schematic cross-sectional view of a superlattice repeating unit in accordance with another embodiment of the invention.

Fig. 6 is a schematic cross-sectional view of a superlattice structure in accordance with yet another embodiment of the invention.

Fig. 7 is a graph showing the curvature of a semiconductor structure according to a comparative example and two embodiments of the present invention as a function of time for different processes.

Fig. 8 is a graph showing the variation of warpage of semiconductor structures according to a comparative example and two embodiments of the present invention with thickness of different superlattice structures.

FIG. 9 is a schematic cross-sectional view of a substrate according to an embodiment of the invention.

Fig. 10 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to one embodiment of the invention.

100 … semiconductor structure

101 … substrate

101C … core substrate

101M … composite layer

103 … seed layer

105 … superlattice structure

105RU … superlattice repeat units

105U-1 … first superlattice unit

105U-2 … second superlattice cell

105U-n … nth superlattice cell

106 … electrical isolation layer

107 … channel layer

108 … barrier layer

109 … doped semiconductor cap layer

110 … epitaxial growth layer

112. 116 … insulating material layer

114 … semiconductor material layer

SL1 … first superlattice layer

SL1-1 … (1-1) th sublayer

SL1-2 … (1-2) sub-layer

SL2 … second superlattice layer

SL2-1 … (2-1) th sublayer

SL2-2 … (2-2) sub-layer

SL3 … third superlattice layer

SL3-1 … (3-1) th sublayer

SL3-2 … (3-2) th sublayer

SLA … first superlattice layer

SLB … second superlattice layer

SLC … third superlattice layer

SLD … fourth superlattice layer

SLM … Mth superlattice layer

SLN … N superlattice layer

120 … gate electrode

122 … source electrode

124 … drain electrode

2DEG … two-dimensional electron gas region

200 … high electron mobility transistor

701. 702, 703 … curve

801. 802, 803 … curve

a1, a2, a3, b1, b2, b3 … thickness

Detailed Description

The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to the first feature being in direct contact with the second feature, or may refer to other features being present between the first and second features, such that the first and second features are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.

In addition, for the spatially related narrative terms mentioned in the present invention, for example: when "under", "low", "lower", "upper", "lower", "top", "bottom" and the like, for ease of description, the description is used to describe one element or feature's relative relationship to another element(s) or feature(s) in the figures. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.

Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself imply any preceding ordinal number or order of arrangement or method of manufacture of the element. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the embodiments of the present invention.

The terms "about" or "substantially" as referred to herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," the meaning of "about" or "substantially" may still be implied.

In the present invention, the term "group III-V semiconductor" refers to a compound semiconductor including at least one group III element and at least one group V element. Among them, the group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Further, "iii-v semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor, or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (inaias), gallium indium arsenide (InGaAs), the like, or a combination of the above compounds, but is not limited thereto. In addition, the III-V semiconductor may also include dopants therein, as desired, to be III-V semiconductor having a specific conductivity type, such as an n-type or p-type III-V semiconductor. Hereinafter, the III-V semiconductor may also be referred to as a III-V semiconductor.

While the invention is described in terms of specific embodiments, the principles of the invention are applicable to other embodiments as well. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and such details are within the knowledge of those of ordinary skill in the art.

The invention relates to a semiconductor structure comprising a superlattice structure and a manufacturing method thereof, wherein the superlattice structure of the semiconductor structure increases in thickness along with the accumulation of a plurality of superlattice layers, but the curvature of the superlattice structure is maintained at a fixed degree (namely, the curvature of the whole substrate cannot be greatly increased or reduced along with the increase of the thickness of the superlattice layers on the substrate), so that good stress control can be achieved, and the requirement of small warping variation can be met for various thickness requirements of different semiconductor devices. For example, for a high power Radio Frequency (RF) gallium nitride high electron mobility transistor (GaN based HEMT), a superlattice layer with a relatively thin thickness and small warpage variation is generally required to enhance RF characteristics, and the superlattice structure of the semiconductor structure of the present invention can be applied to various superlattice structure thicknesses of any high electron mobility transistor to achieve good stress control, device electrical properties (e.g., breakdown voltage), or manufacturing yield, thereby enhancing the application of the semiconductor structure to semiconductor devices in different fields.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. As shown in fig. 1, in one embodiment, a semiconductor structure 100 includes a substrate 101, a seed layer (layer) 103, a Superlattice (SL) structure 105, and an epitaxial growth layer 110 sequentially disposed from bottom to top. According to one embodiment, the epitaxially grown layer 110 may include an electrical isolation layer (electrical isolation layer) 106, a channel layer (channel layer) 107, a barrier layer (barrier layer) 108, and a doped semiconductor cap layer 109, which are stacked sequentially from bottom to top. The materials of the seed layer 103, the superlattice structure 105, and the epitaxial growth layer 110 are III-V semiconductor materials, and in one embodiment, the seed layer 103 is, for example, an aluminum nitride (AlN) layer, the electrical isolation layer 106 is, for example, a carbon-doped gallium nitride (c-GaN) layer, the channel layer 107 is, for example, an undoped gallium nitride (u-GaN) layer, the barrier layer 108 is, for example, an aluminum gallium nitride (AlGaN) layer, and the doped semiconductor cap layer 109 is, for example, a p-type gallium nitride (p-GaN) layer, but not limited thereto, and the composition and structural arrangement of the layers of the epitaxial growth layer 110 may be determined according to the requirements of various semiconductor devices.

Fig. 2 is a schematic cross-sectional view of a superlattice structure in accordance with an embodiment of the invention. As shown in fig. 2, in one embodiment, the superlattice structure 105 includes a stack of a plurality of superlattice repeat units 105RU (105U-1,105U-2, …, 105U-n), and for simplicity of illustration, only 3 superlattice repeat units 105RU are depicted in fig. 2, and in practice the superlattice structure 105 may include 5, 10, or other numbers of superlattice repeat units 105RU. In one embodiment, as shown in fig. 2, each superlattice repeat unit 105RU includes a first superlattice layer SL1 and a second superlattice layer SL2, and the second superlattice layer SL2 is stacked on the first superlattice layer SL1.

Fig. 3 is a schematic cross-sectional view of a superlattice repeating unit in accordance with an embodiment of the invention. As shown in fig. 3, in this embodiment, the first superlattice layer SL1 of the superlattice repeating unit 105RU includes a stacked plurality of pairs of (1-1) th and (1-2) th sublayers SL1-1 and SL1-2, wherein the (1-2) th sublayer SL1-2 is disposed on the (1-1) th sublayer SL 1-1. In addition, the second superlattice layer SL2 of the superlattice repeating unit 105RU also includes a stacked plurality of pairs of (2-1) th and (2-2) th sublayers SL2-1 and SL2-2, wherein the (2-2) th sublayer SL2-2 is disposed on the (2-1) th sublayer SL 2-1. In an embodiment, the first superlattice layer SL1 of each superlattice repeat unit 105RU may include, for example, 12 pairs of (1-1) th and (1-2) th sublayers SL1-1 and SL1-2, the second superlattice layer SL2 of each superlattice repeat unit 105RU may include, for example, 18 pairs of (2-1) th and (2-2) th sublayers SL2-1 and SL2-2, and the superlattice structure 105 may include, for example, 5 of the above-described superlattice repeat units 105RU. In another embodiment, the first superlattice layer SL1 of each superlattice repeat unit 105RU may include, for example, 6 pairs of (1-1) th and (1-2) th sublayers SL1-1 and SL1-2, the second superlattice layer SL2 of each superlattice repeat unit 105RU may include, for example, 9 pairs of (2-1) th and (2-2) th sublayers SL2-1 and SL2-2, and the superlattice structure 105 may include, for example, 10 of the superlattice repeat units 105RU described above. The above is illustrative, and the number of superlattice repeating units 105RU, the number of pairs of sub-layers in the first superlattice layer SL1, and the number of pairs of sub-layers in the second superlattice layer SL2 may be varied according to practical requirements.

According to an embodiment of the present invention, the (1-1) th sub-layer SL1-1, the (1-2) th sub-layer SL1-2, the (2-1) th sub-layer SL2-1 and the (2-2) th sub-layer SL2-2 are a plurality of AlGaN layers each having a different composition, for example, the (1-1) th sub-layer SL1-1 is composed of AlGaN (Al) _x1 Ga _1-x1 N), the (1-2) th sub-layer SL1-2 is composed of aluminum gallium nitride (Al) _y1 Ga _1-y1 N), the (2-1) th sublayer SL2-1 is composed of aluminum gallium nitride (Al) _x2 Ga _1-x2 N), the (2-2) th sublayer SL2-2 is composed of aluminum gallium nitride (Al) _y2 Ga _1-y2 N), wherein the aluminum atom concentration x2 of the (2-1) th sub-layer SL2-1 is greater than the aluminum atom concentration x1 of the (1-1) th sub-layer SL1-1, and the aluminum atom concentration y2 of the (2-2) th sub-layer SL2-2 is greater than the aluminum atom concentration y1 of the (1-2) th sub-layer SL 1-2. Further, as shown in FIG. 3, the (1-1) th sub-layer SL1-1 has a thickness of a1, the (1-2) th sub-layer SL1-2 has a thickness of b1, the (2-1) th sub-layer SL2-1 has a thickness of a2, and the (2-2) th sub-layer SL2-2 has a thickness of b2. At the position ofIn one embodiment, the thickness a1 of the (1-1) th sub-layer SL1-1 is smaller than the thickness a2 of the (2-1) th sub-layer SL2-1, and the thickness b1 of the (1-2) th sub-layer SL1-2 is larger than the thickness b2 of the (2-2) th sub-layer SL 2-2. In addition, in one embodiment, the aluminum atom concentration x1 of the (1-1) th sub-layer SL1-1 is greater than the aluminum atom concentration y1 of the (1-2) th sub-layer SL1-2, and the thickness a1 of the (1-1) th sub-layer SL1-1 is less than the thickness b1 of the (1-2) th sub-layer SL 1-2. The (2-1) th sub-layer SL2-1 has an aluminum atom concentration x2 that is greater than an aluminum atom concentration y2 of the (2-2) th sub-layer SL2-2, and the (2-1) th sub-layer SL2-1 has a thickness a2 that is less than a thickness b2 of the (2-2) th sub-layer SL 2-2. The concentration and thickness relationships between the layers are merely exemplary and may be adjusted according to actual requirements.

According to an embodiment of the present invention, the average aluminum atom concentration of the second superlattice layer SL2 is greater than the average aluminum atom concentration of the first superlattice layer SL1, that is, the average aluminum atom concentration of the superlattice layer stacked above is higher in each superlattice repeating unit 105RU, and the superlattice layer (e.g., the second superlattice layer SL 2) having the higher average aluminum atom concentration and the superlattice layer (e.g., the first superlattice layer SL 1) having the lower average aluminum atom concentration in the superlattice structure 105 exhibit periodic alternating stacks. Furthermore, in one embodiment, the thickness a1 of each (1-1) th sub-layer SL1-1 and the thickness a2 of each (2-1) th sub-layer SL2-1, which have a higher aluminum atom concentration, are both less than 10 nanometers (nm), preferably more than 1 nanometer (nm) and less than 10 nanometers (nm), such as 3nm, 3.5nm, 8nm or other thicknesses less than 10 nanometers (nm), and the thickness b1 of each (1-2) th sub-layer SL1-2 and the thickness b2 of each (2-2) th sub-layer SL2-2, which have a lower aluminum atom concentration, are both greater than or equal to 10 nanometers (nm) and less than 50 nanometers (nm), such as 10nm, 15nm, 20nm, 36nm or other thicknesses greater than 10 nanometers (nm). By adjusting the thickness, cracking or stress defects of each (1-1) th sub-layer SL1-1 and each (1-2) th sub-layer SL1-2 can be avoided.

Fig. 4 is a schematic cross-sectional view of a superlattice structure in accordance with another embodiment of the invention. As shown in fig. 4, in this embodiment, each superlattice repeat unit 105RU of the superlattice structure 105 includes not only the first superlattice layer SL1 and the second superlattice layer SL2, but also the third superlattice layer SL3 to stack the third superlattice layer SL3 on the second superlattice layer SL 2. Although 3 superlattice repeat units 105RU are depicted in fig. 4, in practice the superlattice structure 105 may include 2, 5, or other numbers of superlattice repeat units 105RU, depending upon the requirements of the semiconductor device being utilized, according to various embodiments.

Fig. 5 is a schematic cross-sectional view of a superlattice repeating unit in accordance with another embodiment of the invention. As shown in fig. 5, in this embodiment, each superlattice repeating unit 105RU includes a first superlattice layer SL1, a second superlattice layer SL2, and a third superlattice layer SL3 sequentially stacked from bottom to top, wherein the composition, thickness, and configuration relationship of each sub-layer of the first superlattice layer SL1 and the second superlattice layer SL2 may be referred to the foregoing description of fig. 3, and will not be repeated here. In this embodiment, the third superlattice layer SL3 includes a plurality of stacked pairs of (3-1) th and (3-2) th sublayers SL3-1 and SL3-2, the composition of these sublayers of the third superlattice layer SL3 is different from the composition of each of the sublayers of the first and second superlattice layers SL1 and SL2, for example, the composition of the (3-1) th sublayer SL3-1 is aluminum gallium nitride (Al _x3 Ga _1-x3 N), the (3-2) th sublayer SL3-2 is composed of aluminum gallium nitride (Al) _y3 Ga _1-y3 N), the (3-1) th sub-layer SL3-1 has a thickness a3, and the (3-2) th sub-layer SL3-2 has a thickness b3. In one embodiment, the (3-1) th sub-layer SL3-1 has an aluminum atom concentration x3 that is greater than the (2-1) th sub-layer SL2-1 and the (3-2) th sub-layer SL3-2 has an aluminum atom concentration y3 that is greater than the (2-2) th sub-layer SL 2-2. In this embodiment, the average aluminum atom concentration of the third superlattice layer SL3 is greater than the average aluminum atom concentration of the second superlattice layer SL 2. In addition, the thickness a3 of the (3-1) th sub-layer SL3-1 is greater than the thickness a2 of the (2-1) th sub-layer SL2-1, and the thickness b3 of the (3-2) th sub-layer SL3-2 is less than the thickness b2 of the (2-2) th sub-layer SL 2-2. In addition, the aluminum atom concentration x3 of the (3-1) th sub-layer SL3-1 is greater than the aluminum atom concentration y3 of the (3-2) th sub-layer SL3-2, and the thickness a3 of the (3-1) th sub-layer SL3-1 is less than the thickness b3 of the (3-2) th sub-layer SL 3-2. According to the embodiment of the invention, among the paired sublayers of each superlattice layer, the sublayers with higher aluminum atom concentration are thinner, and the sublayers with lower aluminum atom concentration are thicker.

Fig. 6 is a schematic cross-sectional view of a superlattice structure in accordance with yet another embodiment of the invention. As shown in FIG. 6, in this embodiment, the superlattice structure 105 includes a stack of a plurality of superlattice cells, such as a first superlattice cell 105U-1, a second superlattice cell 105U-2, and an nth superlattice cell 105U-n, in fact the superlattice structure 105 may include 2, 5, 8, 10, or other numbers of superlattice cells, where n is preferably 3 or greater, and the compositions of these superlattice cells 105U-1,105U-2, 105U-n may be the same or each different. The first superlattice cell 105U-1 may include a first superlattice layer SLA and a second superlattice layer SLB, wherein the second superlattice layer SLB is stacked on the first superlattice layer SLA. Referring to the description of fig. 3, as such, the first superlattice layer SLA may include a plurality of stacked pairs of sub-layers, the second superlattice layer SLB may also include a plurality of stacked pairs of sub-layers, and the composition, thickness, and configuration of these pairs of sub-layers of the first superlattice layer SLA and the second superlattice layer SLB may be referred to the description of those sub-layers SL1-1, SL1-2, SL2-1, SL2-2 of the first superlattice layer SL1 and the second superlattice layer SL2 of fig. 3, which is not repeated herein.

The second superlattice cell 105U-2 may include a third superlattice layer SLC and a fourth superlattice layer SLD, wherein the fourth superlattice layer SLD is stacked on the third superlattice layer SLC. Likewise, the third superlattice layer SLC may include stacked plural pairs of sub-layers, the fourth superlattice layer SLD may also include stacked plural pairs of sub-layers, and the composition, thickness, and configuration of these pairs of sub-layers of the third superlattice layer SLC and the fourth superlattice layer SLD may also be referred to in the foregoing description of the sub-layers SL1-1, SL1-2, SL2-1, SL2-2 of the first superlattice layer SL1 and the second superlattice layer SL2 of FIG. 3. Similarly, the nth superlattice cell 105U-N may include an mth superlattice layer SLM and an nth superlattice layer SLN, where the nth superlattice layer SLN is stacked on the mth superlattice layer SLM. Likewise, the nth superlattice layer SLN may include stacked plural pairs of sub-layers, the mth superlattice layer SLM may also include stacked plural pairs of sub-layers, and the composition, thickness, and configuration of these pairs of sub-layers of the mth superlattice layer SLM and the nth superlattice layer SLN may also be referred to as those sub-layers SL1-1, SL1-2, SL2-1, SL2-2 of the first superlattice layer SL1 and the second superlattice layer SL2 of fig. 3, the description of which is not repeated herein.

According to an embodiment of the present invention, the average aluminum atom concentration of the second superlattice layer SLB in the superlattice structure 105 of fig. 6 is higher than the average aluminum atom concentration of the first superlattice layer SLA, the average aluminum atom concentration of the fourth superlattice layer SLD is higher than the average aluminum atom concentration of the third superlattice layer SLC, the average aluminum atom concentration of the nth superlattice layer SLN is higher than the average aluminum atom concentration of the mth superlattice layer SLM, and the average aluminum atom concentrations of the first superlattice layer SLA, the third superlattice layer SLC, and the mth superlattice layer SLM may be equal.

According to an embodiment of the present invention, the respective thicknesses or atomic compositions of the first superlattice layer SLA, the third superlattice layer SLC, and the mth superlattice layer SLM (abbreviated as the first group) of fig. 6 are not identical, for example, the thickness differences of the plurality of superlattice layers of the first group may be less than about 5%, and the atomic compositions of the plurality of superlattice layers of the first group may be identical, but the atomic composition ratios may be different, while the respective thicknesses or atomic compositions of the second superlattice layer SLB, the fourth superlattice layer SLD, and the nth superlattice layer SLN (abbreviated as the second group) are not identical, for example, the thickness differences of the plurality of superlattice layers of the second group may be less than about 5%, and the atomic compositions of the plurality of superlattice layers of the second group may be identical, but the atomic composition ratios may be different. In contrast, the thickness or atomic composition similarity between the superlattice layers in the first group and the superlattice layers in the second group is lower than the thickness or atomic composition similarity of the superlattice layers in the first group, or is lower than the thickness or atomic composition similarity of the superlattice layers in the second group, but the invention is not limited thereto.

In addition, in another embodiment, the first superlattice unit 105U-1 may further include a fifth superlattice layer (not shown in fig. 6) stacked on the second superlattice layer SLB, the fifth superlattice layer may include stacked plural pairs of sublayers, and the relationship between the composition, thickness, and configuration of the pairs of sublayers of the fifth superlattice layer and the composition, thickness, and configuration of the pairs of sublayers of the second superlattice layer SLB may refer to the description of each pair of sublayers of the third superlattice layer SL3 and each pair of sublayers of the second superlattice layer SL2 in fig. 5. Likewise, another superlattice layer may also be stacked on the fourth superlattice layer SLD of the second superlattice cell 105U-2, and/or on the nth superlattice layer SLN of the nth superlattice cell 105U-N. The embodiments of the present invention are not limited to the above-described configuration of the superlattice structures of fig. 2 to 6, and a part of the structures of the embodiments of fig. 2 to 6 may be mixed, replaced or combined as other embodiments according to practical requirements.

In addition, according to an embodiment of the present invention, the method for fabricating the semiconductor structure 100 of fig. 1 includes the following steps: first, a substrate 101 is provided, a seed layer 103 is formed on the substrate 101, and the material of the seed layer 103 includes silicon, gallium nitride, ceramic, silicon carbide, aluminum nitride, aluminum oxide, or a combination thereof, which can be used as a nucleation layer for forming a superlattice structure 105 later, but the invention is not limited thereto. An atomic layer deposition (atomic layer deposition, ALD) process is then performed to form the superlattice structure 105 on the seed layer 103, wherein the atomic layer deposition process includes a plurality of atomic layer deposition cycles (ALD loops). Referring to fig. 3, each atomic layer deposition cycle includes depositing a plurality of pairs of (1-1) th and (1-2) th sublayers SL1-1 and SL1-2 to form a first superlattice layer SL1, and depositing a plurality of pairs of (2-1) th and (2-2) th sublayers SL2-1 and SL2-2 to form a second superlattice layer SL2 on the first superlattice layer SL1. The atomic layer deposition cycle described above is repeated a plurality of times to complete the fabrication of the superlattice structure 105. The (1-1) th sub-layer SL1-1 and the (2-1) th sub-layer SL2-1, which are initially formed in the atomic layer deposition process, are, for example, aluminum nitride (AlN) layers, the (1-2) th sub-layer SL1-2 and the (2-2) th sub-layer SL2-2, which are initially formed, are, for example, aluminum gallium nitride (AlGaN) layers, gallium atoms in the aluminum gallium nitride (AlGaN) layers diffuse into adjacent aluminum nitride (AlN) layers during the atomic layer deposition process, and thus the last (1-1) th sub-layer SL1-1 and the (2-1) th sub-layer SL2-1 become aluminum gallium nitride (AlGaN) layers containing a small amount of gallium atoms, wherein the aluminum atom concentration of the (1-1) th sub-layer SL1 is higher than the aluminum atom concentration of the (1-2) th sub-layer SL1-2, the aluminum atom concentration of the (2-1) th sub-layer SL2-1 is higher than the aluminum atom concentration of the (2-2) th sub-layer SL2-2, and the aluminum atom concentration of the (2-2) th sub-layer SL 2-1-n) is higher than the aluminum atom concentration of the (1-2) th sub-layer SL 2-1-n) sub-n. Continuing with fig. 1, an epitaxially grown layer 110 is formed on the superlattice structure 105. The detailed composition and structural arrangement of the layers of the superlattice structure 105 and the epitaxial growth layer 110 described above may be referred to in the description of fig. 1 to 6, and will not be repeated here.

Fig. 7 shows curves of curvature of semiconductor structures according to a comparative example and two embodiments of the present invention as a function of different process time points, wherein

curves

701, 702, 703 are curvature changes of semiconductor structures of comparative example, embodiment a, and embodiment B, respectively, and fig. 7 shows curvature changes of semiconductor structures at different time points (e.g., corresponding to the time point of providing the substrate 101, the time point of forming the seed layer 103, and the time point of forming the superlattice structure 105). The difference between the comparative example, example a, and example B of fig. 7 is that the first superlattice layer and the second superlattice layer of the superlattice structure 105 are arranged differently, wherein the superlattice structure of the comparative example is composed of the first superlattice layer and the second superlattice layer, the second superlattice layer is stacked on the first superlattice layer and has no repeating superlattice unit, the first superlattice layer of the comparative example is composed of 60 pairs of the (1-1) th sublayer and the (1-2) th sublayer, and the second superlattice layer of the comparative example is composed of 90 pairs of the (2-1) th sublayer and the (2-2) th sublayer.

The superlattice structure of embodiment a is formed by stacking 5 repeating superlattice units, each superlattice repeating unit is composed of a first superlattice layer and a second superlattice layer, the second superlattice layer is stacked on the first superlattice layer, the first superlattice layer of embodiment a is formed by stacking 12 pairs of paired (1-1) th and (1-2) th sublayers, and the second superlattice layer of embodiment a is formed by stacking 18 pairs of paired (2-1) th and (2-2) th sublayers.

The superlattice structure of example B is formed by stacking 10 repeating superlattice units, each superlattice repeating unit is composed of a first superlattice layer and a second superlattice layer, the second superlattice layer is stacked on the first superlattice layer, the first superlattice layer of example B is formed by stacking 6 pairs of paired (1-1) th and (1-2) th sublayers, and the second superlattice layer of example B is formed by stacking 9 pairs of paired (2-1) th and (2-2) th sublayers. The total thickness of the superlattice structures of the above-described comparative examples, example a, and example B are approximately the same, and the compositions of the (1-1) th, the (1-2) th, the (2-1) th, and the (2-2) th sublayers of the comparative examples, example a, and example B are the same.

As can be seen from curve 701 of fig. 7, the curvature of the superlattice structure of the comparative example changes sharply as the deposited thickness of the superlattice structure increases, the curvature following the intermediate deposited section of the superlattice structure being from about-40 km ^-1 Start to increase to about-100 km ^-1 . In addition, as can be seen from curve 702 of fig. 7, the curvature of the superlattice structure of example a does not substantially change much as the deposited thickness of the superlattice structure increases, and can be maintained at about-40 km ^-1 To a degree of (3). As can be seen from the graph 703 of fig. 7, the curvature of the superlattice structure of example B does not substantially change much as the deposited thickness of the superlattice structure increases, and can be maintained at about-35 km ^-1 To a degree of (3). As can be seen from the curvature change curves 701, 702, 703 of fig. 7, the superlattice structure (corresponding to the curves 702, 703) according to the embodiments of the invention can maintain the curvature at a substantially constant level without significant change as the deposited thickness of the superlattice structure increases.

Fig. 8 shows curves of the warp variation of the semiconductor structures according to the comparative example and the two embodiments according to the present invention with different superlattice structure thickness, wherein

curves

801, 802, 803 are curves of the warp variation of the semiconductor structures according to the comparative example, the embodiment a, and the embodiment B with different superlattice structure thickness, respectively, and the warp variation (Δbow) is a difference value between the measured bending degree of the substrate taken out from the atomic layer deposition chamber and the bending degree of the original substrate (before the superlattice structure is not formed) when the substrate is cooled to room temperature during the fabrication of the superlattice structure, so that the warp variation is affected by the lattice constant matching and the thermal expansion coefficient. The superlattice structures of the comparative example, example a, and example B of fig. 8 may be described with reference to fig. 7 above.

As can be seen from the graph 801 of fig. 8, the warp variation of the comparative example drastically decreases as the superlattice structure thickness increases, and thus the slope of the graph 801 is large, and the warp variation of the semiconductor structure is largest when the superlattice structure thickness of the comparative example is thin, for example, 2 micrometers (μm). In contrast, as can be seen from the curve 802 of fig. 8, the amount of warpage change in embodiment a does not change much with increasing superlattice structure thickness, and can be maintained at a substantially constant level, so the slope of the curve 802 is smaller. In addition, as can be seen from the curve 803 of fig. 8, the warp variation of the embodiment B does not change much with the thickness of the superlattice structure, can be maintained at a substantially constant level, the slope of the curve 803 is also small, and the warp variation of the curve 803 is smaller than that of the curve 802.

As can be seen from the

curves

801, 802, 803 of the warp variation of the comparative example, example a, and example B of fig. 8, with the superlattice structure of the present invention, the warp variation can be maintained at a substantially constant level as the thickness of the superlattice structure increases, and the number of superlattice repeating units of the superlattice structure of example B can be greatly reduced from the range of about 50 μm to 60 μm to the range of about 20 μm to 30 μm as compared with the number of superlattice repeating units of example a. It can be seen that according to the embodiments of the present invention, good stress control can be achieved without changing the composition of the pairs of sublayers in the superlattice structure, but by changing the arrangement order of the plurality of superlattice layers in the superlattice structure. Further, as can be seen from the warp variation curves 802, 803 of the embodiment a and the embodiment B of fig. 8, when the number of superlattice repeating units of the superlattice structure is larger, that is, the number of atomic layer deposition cycles is larger, the warp variation is lower, which means that the effect of stress control on the superlattice structure is better when the number of atomic layer deposition cycles is larger.

FIG. 9 is a schematic cross-sectional view of a substrate according to an embodiment of the invention. The substrate 101 of fig. 1 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or a composite substrate as shown in fig. 9, which includes a core substrate 101C and a composite layer 101M surrounding the top, bottom and side surfaces of the core substrate 101C, according to an embodiment of the present invention. The material of the core substrate 101C may be a material that matches the thermal expansion coefficients of the superlattice structure 105 and the epitaxial growth layer 110 subsequently formed on the substrate 101, such as ceramic, silicon carbide, aluminum nitride, or sapphire, and the core substrate 101C may be a harder material selected to provide sufficient mechanical strength to the substrate 101. According to an embodiment of the present invention, the composite material layer 101M may include insulating material layers 112, 116 and a semiconductor material layer 114, wherein the semiconductor material layer 114 is sandwiched between the insulating material layer 112 and the insulating material layer 116. The insulating material layer 112 may be an oxide, such as silicon oxide; the insulating material layer 116 may be a nitride, an oxide, an oxynitride, or a combination of the foregoing, for example, the insulating material layer 116 may be composed of silicon nitride, silicon oxide, and silicon nitride; the layer of semiconductor material 114 may be a layer of silicon or a layer of polysilicon. In addition, according to various requirements, after the semiconductor structure shown in fig. 1 is formed, a thinning process may be performed on the substrate 101, for example, polishing the back side of the substrate 101, so that the core substrate 101C of the composite structure substrate is exposed.

Fig. 10 is a schematic cross-sectional view of a High Electron Mobility Transistor (HEMT) according to one embodiment of the invention. As shown in fig. 10, the semiconductor structure 100 of fig. 1 may be applied to a High Electron Mobility Transistor (HEMT) 200, after the semiconductor structure 100 is fabricated, the doped semiconductor cap layer 109 of the epitaxial growth layer 110 is patterned, then the gate electrode 120 is formed on the patterned doped semiconductor cap layer 109, and the source electrode 122 and the drain electrode 124 are formed on two sides of the gate electrode 120, respectively, and the source electrode 122 and the drain electrode 124 may penetrate the barrier layer 108 or further extend down to a depth position of the channel layer 107. Since the channel layer 107 and the barrier layer 108 of the epitaxial growth layer 110 have discontinuous energy gaps, electrons are accumulated at the heterojunction between the channel layer 107 and the barrier layer 108 due to the piezoelectric effect by stacking the channel layer 107 and the barrier layer 108 on each other, thereby generating a thin layer with high electron mobility, i.e., a two-dimensional electron gas region 2DEG. For normally off (normally off) devices, when no voltage is applied to the gate electrode 120, the region covered by the doped semiconductor cap layer 109 does not form a two-dimensional electron gas (as shown in fig. 10), which can be considered as a 2DEG cut-off region, and the source electrode 122 and the drain electrode 124 are not conductive. When a positive voltage is applied to the gate electrode 120, the region covered by the doped semiconductor cap layer 109 forms a two-dimensional electron gas, so that a continuous two-dimensional electron gas region is generated between the source electrode 122 and the drain electrode 124, and conduction is achieved between the source electrode 122 and the drain electrode 124.

According to an embodiment of the invention, when the semiconductor structure is applied to a high power radio frequency gallium nitride high electron mobility transistor (highpower RF GaN based HEMT), the requirement of thinner superlattice structure thickness can be met, and good stress control is achieved, thereby improving the radio frequency characteristics of the HEMT. In addition, since the superlattice structure of the embodiment of the invention can avoid the substrate from warping when the thickness is changed, the superlattice structure can be suitable for thickness requirements of various superlattice structures, and the possibility of generating cracks due to stress is reduced, so that the reliability of the semiconductor device and the application range of products can be improved.

The above description is only of the preferred embodiments of the present invention, and all the equivalent changes and modifications according to the claims should be considered as falling within the scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a seed crystal layer arranged on a substrate;

an epitaxial growth layer disposed over the seed layer; and

a superlattice structure disposed between the seed layer and the epitaxial growth layer, wherein the superlattice structure comprises a plurality of superlattice cells stacked in a staggered manner, and two adjacent superlattice cells comprise:

a first superlattice unit including a first superlattice layer and a second superlattice layer stacked on the first superlattice layer, wherein the first superlattice layer includes a plurality of pairs of (1-1) th and (1-2) th sublayers, and the second superlattice layer includes a plurality of pairs of (2-1) th and (2-2) th sublayers; and

the second superlattice unit is arranged on the first superlattice unit and comprises a third superlattice layer and a fourth superlattice layer stacked on the third superlattice layer, wherein the third superlattice layer comprises a plurality of pairs of (3-1) th sublayers and (3-2) th sublayers, and the fourth superlattice layer comprises a plurality of pairs of (4-1) th sublayers and (4-2) th sublayers.

2. The semiconductor structure of claim 1, wherein the first superlattice cell and the second superlattice cell are repeating cells.

3. The semiconductor structure of claim 1, wherein a thickness of the (1-1) th sub-layer is less than a thickness of the (1-2) th sub-layer, and an aluminum atomic concentration of the (1-1) th sub-layer is higher than an aluminum atomic concentration of the (1-2) th sub-layer.

4. The semiconductor structure of claim 1, wherein the (2-1) th sub-layer has an aluminum atomic concentration higher than that of the (1-1) th sub-layer, and wherein the (4-1) th sub-layer has an aluminum atomic concentration higher than that of the (3-1) th sub-layer.

5. The semiconductor structure of claim 1, wherein the (2-2) th sub-layer has an aluminum atomic concentration higher than that of the (1-2) th sub-layer, and wherein the (4-2) th sub-layer has an aluminum atomic concentration higher than that of the (3-2) th sub-layer.

6. The semiconductor structure of claim 1, wherein a thickness of the (2-1) th sub-layer is greater than a thickness of the (1-1) th sub-layer, the thickness of the (2-2) th sub-layer being less than a thickness of the (1-2) th sub-layer.

7. The semiconductor structure of claim 1, wherein an average aluminum atom concentration of the second superlattice layer is higher than an average aluminum atom concentration of the first superlattice layer, an average aluminum atom concentration of the fourth superlattice layer is higher than an average aluminum atom concentration of the third superlattice layer, and the average aluminum atom concentration of the first superlattice layer is equal to the average aluminum atom concentration of the third superlattice layer.

8. The semiconductor structure of claim 1, wherein the first superlattice cell further comprises a fifth superlattice layer stacked on the second superlattice layer, the fifth superlattice layer comprising a plurality of pairs of (5-1) th and (5-2) th sublayers.

9. The semiconductor structure of claim 1, wherein the base comprises a silicon-containing substrate or a composite substrate comprising a core substrate and a composite layer surrounding the core substrate, the core substrate comprising ceramic, silicon carbide, aluminum nitride, or sapphire, and the composite layer comprising a layer of insulating material and a layer of semiconductor material.

10. The semiconductor structure of claim 1, wherein a thickness of each of the (1-1) th sub-layers, a thickness of each of the (2-1) th sub-layers, a thickness of each of the (3-1) th sub-layers, and a thickness of each of the (4-1) th sub-layers are each less than 10 nanometers (nm).