CN116230711A - Monolithic integrated device of HEMT and LED and preparation method thereof - Google Patents

Monolithic integrated device of HEMT and LED and preparation method thereof Download PDF

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CN116230711A
CN116230711A CN202310508633.2A CN202310508633A CN116230711A CN 116230711 A CN116230711 A CN 116230711A CN 202310508633 A CN202310508633 A CN 202310508633A CN 116230711 A CN116230711 A CN 116230711A
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layer
led
hemt
laminated structure
electrode
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CN116230711B (en
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王阳
王国斌
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Jiangsu Third Generation Semiconductor Research Institute Co Ltd
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Jiangsu Third Generation Semiconductor Research Institute Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Abstract

The invention discloses a monolithic integrated device of HEMT and LED and a preparation method thereof, wherein the monolithic integrated device comprises: the LED comprises a substrate, a HEMT laminated structure and an LED laminated structure, wherein the HEMT laminated structure and the LED laminated structure are arranged on one side of the substrate; the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of a substrate, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transport layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transport layer. By adopting the technical scheme, electrons can be provided for the LED laminated structure by utilizing the two-dimensional electron gas layer, the thickness of the electron transmission layer in the LED laminated structure is reduced or the electron transmission layer is not arranged any more, so that the preparation process of the monolithic integrated device is simplified, and the preparation difficulty of the monolithic integrated device is reduced.

Description

Monolithic integrated device of HEMT and LED and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a monolithic integrated device of HEMT and LED and a preparation method thereof.
Background
Silicon nitride (GaN) -based III-nitride materials have extremely high application value in the field of optoelectronic devices due to their excellent characteristics of direct band gap, high electron mobility, high electron saturation rate, and the like. GaN-based devices have two main applications: a Light emitting device represented by a Light-emitting diode (LED), which is mainly applied to the fields of solid-state lighting, flat panel display, visible Light communication, and the like; secondly, electronic devices represented by high electron mobility transistors (High electron mobility transistor, HEMT) are mainly applied to the fields of radio frequency devices, 5G communication and the like. Because the two device process platforms are compatible, the monolithic integration of the LED and the HEMT can be realized, the LED is driven by the HEMT, the device volume can be effectively reduced, the parasitic capacitance of an external circuit is reduced, and the device reliability is improved. In the prior art, the structure and the preparation process of the monolithic integrated device of the LED and the HEMT are complex, and the application of the monolithic integrated device is limited.
Disclosure of Invention
The invention provides a monolithic integrated device of HEMT and LED and a preparation method thereof, which are used for simplifying the structure of the integrated device and reducing the preparation difficulty of the integrated device.
In a first aspect, the present invention provides a method for manufacturing a monolithic integrated device of a HEMT and an LED, including:
a substrate;
a HEMT laminated structure and an LED laminated structure arranged on one side of the substrate;
the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of the substrate, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transmission layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transmission layer.
In a second aspect, the present invention provides a method for manufacturing a monolithic integrated device of HEMT and LED, comprising:
providing a substrate;
preparing a HEMT laminated structure and an LED laminated structure on one side surface of the substrate; the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of a substrate, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transmission layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transmission layer.
The monolithic integrated device of HEMT and LED that this application embodiment provided includes: the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of the substrate, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transport layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transport layer. By adopting the technical scheme, electrons can be provided for the LED laminated structure by utilizing the two-dimensional electron gas layer, the thickness of the electron transmission layer in the LED laminated structure is reduced or the electron transmission layer is not arranged any more, so that the preparation process of the monolithic integrated device is simplified, and the preparation difficulty of the monolithic integrated device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a monolithic integrated device of HEMT and LED provided by the present invention;
FIG. 2 is a schematic top view of an electrode according to the present invention;
FIG. 3 is a schematic top view of another electrode according to the present invention;
fig. 4 is a schematic structural diagram of another monolithic integrated device of HEMT and LED provided by the present invention;
FIG. 5 is a schematic diagram of a portion of a monolithically integrated device of the HEMT and the LED of FIG. 4;
Fig. 6 is a schematic structural diagram of a monolithic integrated device of HEMT and LED according to another embodiment of the present invention;
fig. 7 is a flowchart of a method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention;
FIG. 8 is a schematic illustration of the preparation process of FIG. 7;
fig. 9 is a flowchart of a method for manufacturing another monolithic integrated device of HEMT and LED provided by the invention;
FIG. 10 is a schematic diagram of the preparation method shown in FIG. 9;
fig. 11 is a flowchart of a method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention;
FIG. 12 is a schematic illustration of the preparation process of FIG. 11;
fig. 13 is a schematic diagram of a method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention;
fig. 14 is a schematic diagram of a method for manufacturing another monolithic integrated device of HEMT and LED according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Currently, there are two main methods for monolithic integration of an LED and a HEMT: the method comprises the steps of firstly epitaxially growing an LED (or HEMT) structure, then selectively etching the epitaxial structure to a GaN buffer layer or a substrate layer, and epitaxially growing the HEMT (or LED) structure on the GaN buffer layer or the substrate in the etched area, thereby realizing a HEMT-LED monolithic integrated structure in transverse arrangement; the method needs multiple etching and secondary epitaxy, the preparation process is complex, and the side wall of the HEMT (or the LED) is easily damaged in the secondary epitaxy process of the HEMT (or the LED), so that the performance of the integrated device is affected. Another method is to stack and grow HEMT and LED structure (HEMT under, LED over, or LED under, HEMT over), form HEMT and LED two areas by etching, deposit LED electrode and HEMT electrode separately, LED electrode and HEMT electrode connect through the way of the metal lead wire; however, this method requires the deposition of a thicker electron transport layer (typically in the range of 500-5 um) for the LED structure, and also requires the preparation of more complex metal leads to achieve the interconnection of the two devices.
Based on the above-mentioned related art defect, the present application provides a monolithic integrated device of HEMT and LED, including:
a substrate;
A HEMT laminated structure and an LED laminated structure arranged on one side of the substrate;
the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of a substrate, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transport layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transport layer.
In the technical scheme, electrons are provided for the LED laminated structure by utilizing the two-dimensional electron gas layer, so that the thickness of the electron transmission layer in the LED laminated structure is reduced or the electron transmission layer is not arranged any more, the preparation process of the monolithic integrated device is simplified, and the preparation difficulty of the monolithic integrated device is reduced.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a monolithic integrated device of HEMT and LED according to the present invention, where the monolithic integrated device includes: a substrate 1, a HEMT laminated structure 2 and an LED laminated structure 3 provided on one side of the substrate 1.
The substrate 1 may be sapphire (Al 2 O 3 ) A substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a GaN substrate, or the like, but is not limited thereto; the film layers grown on the surface of the substrate 1 are epitaxial layers.
The HEMT stack structure 2 includes a channel layer 20 and a barrier layer 21 stacked in this order on the surface of the substrate 1, with a two-dimensional electron gas layer 22 formed between the channel layer 20 and the barrier layer 21. The LED stack 3 includes an electron transport layer 30, and the two-dimensional electron gas layer 22 is multiplexed into at least part of the electron transport layer 30. Specifically, the HEMT laminated structure 2 can be understood as a HEMT device in a monolithically integrated device, the LED laminated structure 3 can be understood as an LED device in a monolithically integrated device, and the HEMT laminated structure 2 drives the LED laminated structure 3 to emit light; the LED laminated structure 3 can be a common LED laminated structure, or a Micro-LED laminated structure or a Mini-LED laminated structure.
The HEMT stack structure 2 includes a channel layer 20 and a barrier layer 21, the channel layer 20 being located on the surface of the substrate 1, the barrier layer 21 being located on a side surface of the channel layer 20 facing away from the barrier layer 21. In this arrangement, since the channel layer 20 is located below the barrier layer 21, a two-dimensional electron gas layer 22 is formed between the channel layer 20 and the barrier layer 21. It should be noted that the two-dimensional electron gas layer 22 refers to a thin layer with high-speed movement and high concentration of electrons generated at the heterojunction between different group III nitrides, and the area of the two-dimensional electron gas layer 22 has lower resistivity and better electron transmission condition.
Alternatively, the channel layer 20 may be made of GaN material, and the barrier layer 21 may be made of aluminum gallium nitride (AlGaN) material, but is not limited thereto. The channel layer 20 and the barrier layer 21 are selected from different group III nitrides. The thickness of the channel layer 20 may be 300 to 1000nm, and the thickness of the barrier layer 21 may be 20 to 30nm, but is not limited thereto.
Further, with continued reference to fig. 1, the LED stack structure 3 may be disposed on a side of the barrier layer 21 away from the channel layer 20, where a surface of the barrier layer 21 on a side away from the channel layer 20 may be defined as a surface of the barrier layer 21, and the LED stack structure 3 may be located in a partial area of the surface of the barrier layer 21, so as to implement monolithic integration of the HEMT stack structure 2 and the LED stack structure 3, and drive the LED with the LEMT stack structure, thereby simplifying a driving circuit of the device and improving reliability of device control.
In addition, the LED stacked structure 3 includes an electron transport layer 30, and the electron transport layer 30 is used for providing electrons, which is worth mentioning that in the embodiment of the present invention, the two-dimensional electron gas layer 22 may be multiplexed into at least part of the electron transport layer 30, and the two-dimensional electron gas layer 22 is used for providing electrons for the LED stacked structure 3. Therefore, the thickness of the electron transport layer 30 in the LED laminated structure 3 can be set thinner, or the electron transport layer 30 can be omitted, so that the preparation process of the monolithic integrated device is simplified, the preparation difficulty of the device is reduced, meanwhile, the epitaxial growth time of the LED laminated structure 3 can be reduced, the consumption of raw materials is reduced, and the preparation cost of the device is reduced.
Optionally, in the embodiment shown in fig. 1, a buffer layer 4 may be further disposed between the substrate 1 and the channel layer 20, where the buffer layer 4 may reduce the defect density in the epitaxial layer and improve the crystal quality of the epitaxial layer. For example, in an alternative embodiment, the buffer layer 4 may be high-resistance GaN, but is not limited thereto, and the thickness of the buffer layer 4 may be controlled within a range of 100-500 nm. Of course, in other possible embodiments, direct contact between the substrate 1 and the channel layer 20 may be possible, in which case the substrate 1 may be made of a semi-insulating or high-resistance material.
Optionally, the monolithically integrated device of HEMT and LED provided in the embodiments of the present application may further include any film layer structure known to those skilled in the art, which is not limited in this application. Illustratively, in other embodiments not shown, an AlN layer or the like is also included between the channel layer and the barrier layer to improve HEMT performance.
The embodiment provides a monolithic integrated device integrating a HEMT and an LED, the monolithic integrated device comprising: the substrate, the HEMT laminated structure and the LED laminated structure, the HEMT laminated structure comprises a channel layer and a barrier layer which are laminated on the surface of the substrate in sequence, a two-dimensional electron gas layer is formed between the channel layer and the barrier layer, the two-dimensional electron gas layer is used as at least one part of an electron transmission layer in the LED laminated structure, electrons are provided for the LED laminated structure by utilizing the two-dimensional electron gas layer, the thickness of the electron transmission layer in the LED laminated structure is reduced or the electron transmission layer is not arranged any more, and therefore the preparation process of the monolithic integrated device is simplified, and the preparation difficulty of the monolithic integrated device is reduced.
Alternatively, with continued reference to fig. 1, in a possible embodiment, the HEMT stack structure 2 may further comprise a first electrode 23, the first electrode 23 being located on the side of the LED stack structure 3 facing away from the barrier layer 21, the first electrode 23 forming an ohmic contact with the upper epitaxial layer in the LED stack structure 3, the first electrode 23 multiplexing as an anode of the LED stack structure 3.
Specifically, the first electrode 23 is in contact with a side surface of the LED stack structure 3 facing away from the two-dimensional electron gas layer 22, and the first electrode 23 may serve as a drain (or source) of the HEMT stack structure 2, that is, the anode of the LED stack structure 3 and the drain (or source) of the HEMT stack structure 2 share one electrode. Under the arrangement mode, the LED laminated structure 3 and the HEMT laminated structure 2 are communicated without additionally arranging metal leads, and the LED laminated structure 3 and the HEMT laminated structure 2 in the monolithic integrated device can be electrically connected without the metal leads, so that the preparation process difficulty of the monolithic integrated device is further reduced, the integration level is improved, and the whole volume of the device is reduced.
Further, the first electrode 23 may be made of a metal conductive material such as nickel (Ni), platinum (Pt), titanium (Ti), or aluminum (Al), or a transparent conductive material such as Indium Tin Oxide (ITO), but is not limited thereto. The transparent conductive material is used for preparing the first electrode 23, so that the light transmittance of the first electrode 23 can be improved, and the luminous efficiency of the LED can be ensured.
It is understood that any film layer structure known to those skilled in the art may be further included in the HEMT stack structure 2 and the LED stack structure 3, which is not limited in this embodiment.
Illustratively, in a possible embodiment, the LED stacked structure 3 may further include an active layer 31 and a hole transport layer 32 stacked along a plane direction perpendicular to the substrate 1, where the active layer 31 is located on a surface of a side of the barrier layer 21 facing away from the channel layer 20, and the hole transport layer 32 is located on a side of the active layer 31 facing away from the barrier layer 21. The HEMT stack structure 2 further includes a second electrode 24 and a gate electrode 25, both the second electrode 24 and the gate electrode 25 being located on a side of the barrier layer 21 facing away from the channel layer 20; the orthographic projection of the second electrode 24 and the grid electrode 25 on the plane of the substrate 1 is not overlapped with the orthographic projection of the LED laminated structure 3 on the plane of the substrate 1, and the second electrode 24 is multiplexed as the cathode of the LED laminated structure 3.
Further, the active layer 31 may be an InGaN/GaN quantum well active layer, but is not limited thereto; the hole transport layer 32 may be a p-type GaN layer, but is not limited thereto, and may be any film layer capable of providing holes. In this embodiment, the two-dimensional electron gas layer 22 can be multiplexed into all the electron transport layers 30 of the LED stacked structure 3, i.e. no electron transport layer 30 is disposed in the LED stacked structure 3, electrons required for LED light emission are provided by the two-dimensional electron gas layer 22, and electrons in the two-dimensional electron gas layer 22 and holes in the hole transport layer 32 are combined in the active layer 31 and emit light.
Alternatively, the thickness of the active layer 31 and the hole transport layer 32 in the LED stack structure 3 is not limited in the present invention, and may be set by those skilled in the art according to actual circumstances. For example, in an alternative embodiment, the active layer 31 may be a 1-10 period InGaN/GaN quantum well active layer, where the InGaN layer has a thickness in the range of 2-3 nm and the GaN layer has a thickness in the range of 8-15 nm; the thickness of the hole transport layer 32 is in the range of 100 to 500nm, but is not limited thereto.
Further, with continued reference to fig. 1, the HEMT stack structure 2 further includes a second electrode 24 and a gate 25, where the second electrode 24 may be the source (or drain) of the HEMT device, i.e., when the first electrode 23 is the source, the second electrode 24 is the drain; when the first electrode 23 is a drain electrode, the second electrode 24 is a source electrode. The second electrode 24 and the gate electrode 25 may be disposed on a side of the barrier layer 21 facing away from the channel layer 20, and projections of the second electrode 24 and the gate electrode 25 do not overlap with projections of the LED stack structure 3 in a thickness direction of the monolithically integrated device. In other words, the second electrode 24 and the gate electrode 25 are both located in a region on the surface of the barrier layer 21 where the active layer 31 is not provided. Specifically, the second electrode 24 and the gate electrode 25 may be made of a metal conductive material or a transparent conductive material, but are not limited thereto, and the description thereof is omitted in this embodiment.
Since the second electrode 24 of the HEMT stack structure 2 is directly in contact with the two-dimensional electron gas layer 22, the two-dimensional electron gas layer 22 is directly in contact with the active layer 31 of the LED stack structure 3, and the second electrode 24 can be directly multiplexed as the cathode of the LED device. The operation of a monolithically integrated device is generally described as follows: the gate 25 of the HEMT device receives a gate control signal, and when the gate control signal is an active enable signal, the HEMT device is in an on state, and a voltage applied to the source may be transferred to the drain, or a voltage applied to the drain (i.e., the cathode of the LED device) may be transferred to the source (i.e., the anode of the LED device). At this time, electrons in the two-dimensional electron gas layer 22 formed between the channel layer 20 and the barrier layer 21 may be transferred to the active layer 31 of the LED device (the moving direction of the electrons in the two-dimensional electron gas layer 22 is indicated by a dotted arrow in the drawing), holes in the hole transport layer 32 of the LED device may be transferred to the active layer 31, and the holes and electrons are recombined in the active layer 31 to emit light.
In this embodiment, the cathode of the LED lamination structure 3 and the source (or drain) of the HEMT lamination structure 2 share one electrode, so that no additional metal lead is required, and the manufacturing difficulty of the monolithically integrated device can be further reduced.
Alternatively, the pattern shape of each electrode of the HEMT stacked structure 2 is not limited, and a person skilled in the art may set the pattern shape according to actual needs, and fig. 2 and 3 are schematic top view structures of the electrodes provided by the present invention, and the gate 25, the first electrode 23 (e.g., drain) and the second electrode 24 (e.g., source) of the HEMT stacked structure 2 may be any shape in fig. 2 or 3, but are not limited thereto.
In other not shown embodiments, a stress relief layer (not shown in the figure), such as an InGaN/GaN superlattice stress relief layer, may be further provided between the electron transport layer 30 and/or the hole transport layer 32 and the active layer 31 in the LED stack structure 3, but is not limited thereto.
Referring to fig. 4, fig. 4 is a schematic structural diagram of another monolithic integrated device of HEMT and LED according to the present invention. For the same technical content as in the embodiment shown in fig. 1, the description of this embodiment is omitted; in the present embodiment, the electron transport layer 30 includes a first electron transport layer 301 and a second electron transport layer 302; the LED stack structure 3 further includes an active layer 31 and a hole transport layer 32 stacked in a direction perpendicular to the plane of the substrate 1, the active layer 31 being located between the second electron transport layer 30 and the hole transport layer 32.
The two-dimensional electron gas layer 22 is multiplexed into the first electron transport layer 301, that is, in this embodiment, the two-dimensional electron gas layer 22 may be multiplexed into a part of the electron transport layer 30 (i.e., the first electron transport layer 301) of the LED stack structure 3, while the electron transport layer 30 (i.e., the second electron transport layer 302) having a certain thickness is retained in the LED stack structure 3. The second electron transport layer 302 is located on a surface of the barrier layer 21 facing away from the channel layer 20, and the second electron transport layer 302 may be an n-type GaN layer, but is not limited thereto, and may be any film layer capable of providing electrons.
In this arrangement, the second electron transport layer 302 is located in a partial region of the surface of the barrier layer 21. The active layer 31 is located at a side of the second electron transport layer 302 facing away from the channel layer 20, the hole transport layer 32 is located at a side of the active layer 31 facing away from the second electron transport layer 302, and the hole transport layer 32 is disposed between the active layer 31 and the first electrode 23. The two-dimensional electron gas layer 22 and the second electron transport layer 302 simultaneously provide electrons for the active layer 31, so as to ensure sufficient supply of electrons. The active layer 31 and the hole transport layer 32 are the same as those in the above embodiments, and will not be described here again.
The second electron transport layer 302 may not only function to provide electrons, but also provide a certain growth platform for the growth of the active layer 31, and improve the growth quality of the active layer 31.
It should be noted that, unlike the related art, in this embodiment, since the second electron transporting layer 302 is not the only source of electrons, a thicker second electron transporting layer 302 is not required. The second electron transport layer 302 may be provided thinner to ensure that the monolithic integrated device has a thinner overall thickness.
It is understood that the thickness of the second electron transport layer 302 is not limited in this embodiment, and may be set by those skilled in the art according to practical situations. For example, in an alternative embodiment, the thickness of the second electron transport layer 302 may be set in the range of 10-50 nm, which is much lower than the set thickness of 500-5 um in the related art.
Optionally, referring to fig. 4 and fig. 5 in combination, fig. 5 is a schematic view of a part of a monolithic integrated device of the HEMT and the LED shown in fig. 4, where the monolithic integrated device may further include a dielectric layer 5, and the dielectric layer 5 is located on a surface of a side of the barrier layer 21 facing away from the channel layer 20.
The dielectric layer 5 includes a first opening 51, and the dielectric layer 5 is not disposed at the first opening 51, so that a portion of the surface of the barrier layer 21 is exposed from the first opening 51; at least a portion of the second electron transport layer 302 fills in the first opening 51 and contacts the barrier layer 21; wherein a side surface of the second electron transport layer 302 facing away from the barrier layer 21 is higher than a side surface of the dielectric layer 5 facing away from the barrier layer 21. In fig. 5, only the dielectric layer 5 on the surface of the barrier layer 21 is shown, and the LED stack structure 3 is not shown.
In this arrangement, the second electron transport layer 302 may be filled in the first opening 51, the lower surface of the second electron transport layer 302 is in contact with the barrier layer 21, and the projection of the LED stack structure 3 overlaps with the projection of the first opening 51 in the thickness direction of the monolithically integrated device. The dielectric layer 5 can provide a mask for the growth of the LED laminated structure 3, provide a better growth space for the LED laminated structure 3, and promote the uniformity of the LED laminated structure 3 in the thickness direction.
In addition, in the present embodiment, the thickness of the second electron transport layer 302 may be set to be greater than the thickness of the dielectric layer 5, so that the upper surface of the second electron transport layer 302 is higher than the upper surface of the dielectric layer 5. Facilitating the subsequent growth of the active layer 31 on the upper surface of the second electron transport layer 302.
For example, the thickness of the dielectric layer 5 may be in the range of 2-20 nm, but is not limited thereto, and in the practical application process, a person skilled in the art may adaptively adjust the thickness of the dielectric layer 5 according to the thickness of the second electron transport layer 302. Alternatively, the dielectric layer 5 may be SiN x 、SiO 2 Or Al 2 O 3 Etc., but is not limited thereto.
Alternatively, referring to fig. 4 and fig. 5 in combination, in a possible embodiment, the dielectric layer 5 may further include a second opening 52, where an orthographic projection of the second opening 52 on the plane of the substrate 1 does not overlap with an orthographic projection of the first opening 51 on the plane of the substrate 1.
Specifically, the dielectric layer 5 is not disposed at the second opening 52; the first opening 51 and the second opening 52 are independent of each other, i.e. the projection of the second opening 52 in the thickness direction of the monolithically integrated device does not overlap with the projection of the first opening 51 in this direction.
The second electrode 24 is filled in the second opening 52 and contacts the barrier layer 21, the second electrode 24 forms ohmic contact with the barrier layer 21, and the second electrode 24 is multiplexed as a cathode of the LED stack structure 3.
The gate electrode 25 may be disposed on a side surface of the dielectric layer 5 facing away from the channel layer 20, i.e., in the thickness direction of the monolithically integrated device, with the gate electrode 25 being spaced from the barrier layer 21 by the dielectric layer 5. In this arrangement, the gate 25 and the barrier layer 21 form schottky contact, the dielectric layer 5 is used as a gate dielectric layer to form an MIS-HEMT structure, and the MIS is a metal-insulating layer-semiconductor structure, so that the leakage of the gate 25 can be effectively reduced.
Of course, in other embodiments, when the second electron transport layer 302 is disposed in the LED stack structure, the dielectric layer 5 may not be disposed in the monolithically integrated device, and in this case, the first electrode 23, the second electrode 24, and the gate electrode 25 in the HEMT stack structure 2 may be disposed in the same manner as in the embodiment shown in fig. 1.
Referring to fig. 6, fig. 6 is a schematic structural diagram of another monolithic integrated device of HEMT and LED provided by the present invention, and the technical content of the monolithic integrated device is the same as that of the embodiment shown in fig. 4, and the description of the embodiment is omitted herein; in this embodiment, the monolithically integrated device may further be provided with a protective layer 6, where the protective layer 6 is located on a side of the dielectric layer 5 away from the barrier layer 21, and the protective layer 6 wraps at least a portion of the side wall of the LED laminated structure 3, and the protective layer 6 may protect the LED laminated structure 3, so as to avoid damage to the side wall of the LED laminated structure 3 in the etching process, and improve the reliability of the device.
It will be appreciated that the protective layer 6 is exemplarily shown in fig. 6 to completely encapsulate the sidewalls of the LED stack 3, and that the upper surface of the protective layer 6 is slightly higher than the upper surface of the hollow transmission layer 32 in the LED stack 3, which may be, in practice, not limited thereto, and may be adapted to the specific application requirements.
Alternatively, referring to fig. 4 or 6, in a possible embodiment, the LED stack structure 3 may further include an electron blocking layer 33, where the electron blocking layer 33 is located between the active layer 31 and the hole transport layer 32, and the presence of the electron blocking layer 33 may block the reverse leakage current, thereby improving the light emitting efficiency of the LED device. Illustratively, the electron blocking layer 33 may be selected from AlGaN material, alInN, alInGaN, alGaN/GaN superlattice, alInN/GaN superlattice, etc., but is not limited thereto; the thickness of the electron blocking layer 33 may be set in the range of 10 to 30nm, but is not limited thereto.
Based on the same conception, the application also provides a preparation method of the monolithic integrated device of the HEMT and the LED, which is used for preparing the monolithic integrated device of the HEMT and the LED provided by any embodiment of the invention. Referring to fig. 7 and fig. 8 in combination, fig. 7 is a flowchart of a method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention, and fig. 8 is a schematic diagram of the method for manufacturing shown in fig. 7, where the method for manufacturing includes:
S110, providing a substrate.
The arrangement of the substrate 1 may refer to the above embodiment, and will not be described herein.
S120, preparing a HEMT laminated structure and an LED laminated structure on one side surface of a substrate; the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of a substrate, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transport layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transport layer.
As shown in fig. 8 (b) and 8 (c), an entire channel layer 20 may be grown on one side of the substrate 1, then an entire barrier layer 21 may be grown on a side surface of the channel layer 20 facing away from the substrate 1, and then the LED stack 3 may be prepared on a side surface of the barrier layer 21 facing away from the substrate 1 such that a lower surface of the LED stack 3 is in contact with the barrier layer 21 to multiplex a two-dimensional electron gas layer 22 formed between the channel layer 20 and the barrier layer 21 into at least a portion of the electron transport layer 30 of the LED stack 3. It will be appreciated that in the embodiment shown in fig. 7 and 8, the buffer layer 4 is grown first on the surface of the substrate 1 before the channel layer 20 is grown, but is not limited thereto in practice.
According to the preparation method provided by the invention, electrons are provided for the LED laminated structure 3 by utilizing the two-dimensional electron gas layer 22, so that the thickness of the electron transmission layer 30 in the LED laminated structure 3 is reduced or the electron transmission layer 30 is not arranged any more, the preparation process of the monolithic integrated device is simplified, and the preparation difficulty of the monolithic integrated device is reduced.
Alternatively, in a possible embodiment, with continued reference to fig. 8 (c), the channel layer 20 and the barrier layer 21 are sequentially prepared on the surface of the substrate 1; preparing an LED laminated structure 3 on the side of the barrier layer 21 facing away from the channel layer 20; after the preparation of the LED stack 3, a first electrode 23 of the HEMT stack 2 is prepared on the side of the LED stack 3 facing away from the barrier layer 21, the first electrode 23 being multiplexed as the anode of the LED stack 3. Specifically, the metal first electrode 23 may be deposited using photolithography and electron beam evaporation processes, but is not limited thereto. A first electrode window (not shown) may be etched using standard photolithographic techniques followed by deposition of the first electrode 23 within the first electrode window using an electron beam evaporation process.
Alternatively, with continued reference to fig. 8 (c), a buffer layer 4, such as a high-resistance GaN layer, may be grown on the surface of the substrate 1 before the channel layer 20 is formed, and the high-resistance GaN layer may be formed by a Metal-organic chemical vapor deposition (Metal-Organic Chemical Vapor Deposition, MOCVD) process, but is not limited thereto. The specific process parameters can be as follows: the temperature is 950-1100 ℃; the pressure is100-400 mbar; the V-III ratio (the mol ratio of the V group source and the III group source which are introduced into the reaction chamber) is 100-1000; the carrier gas being H 2 Or H 2 And N 2 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the high-resistance GaN layer is 100-500 nm.
Alternatively, the channel layer 20 may be a GaN channel layer, and the GaN channel layer may be prepared by using an MOCVD process, and specific process parameters may be: the temperature is 1000-1100 ℃; the pressure is 100-400 mbar, and the V-III ratio is 500-3000; the carrier gas being H 2， Or H 2 And N 2 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the GaN channel layer is 300-1000 nm.
Alternatively, the barrier layer 21 may be an AlGaN barrier layer, and the AlGaN barrier layer may be prepared by using an MOCVD process, and specific process parameters may be: the temperature is 1050-1200 ℃; the pressure is 100-200 mbar; al component accounts for 0.2-0.3; the V-III ratio is 500-3000; the carrier gas being H 2 Or H 2 And N 2 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the AlGaN barrier layer is 20-30 nm.
Alternatively, the present invention is not limited to a specific manufacturing process of the LED stack structure 3, and a person skilled in the art may set the present invention according to actual needs. By way of example, several possible fabrication processes for monolithically integrated devices are described below.
Alternatively, in a possible embodiment, the two-dimensional electron gas layer 22 may be multiplexed into the electron transport layer 30, the led stack structure 3 further includes an active layer 31 and a hole transport layer 32 stacked along a plane direction perpendicular to the substrate 1, and the hemt stack structure 2 further includes the second electrode 24 and the gate electrode 25; a channel layer 20 and a barrier layer 21 may be sequentially prepared on the surface of the substrate 1; sequentially preparing an active layer 31 to be processed and a hole transport layer 32 to be processed on one side of the barrier layer 21 away from the channel layer 20; etching the active layer to be treated 31 and the hole transport layer to be treated 32 to remove at least a portion of the active layer to be treated 31 and the hole transport layer to be treated 32, forming an active layer 31 and a hole transport layer 32; and preparing a second electrode 24 and a grid electrode 25 respectively on one side of the barrier layer 21 away from the channel layer 20, wherein the orthographic projection of the second electrode 24 and the grid electrode 25 on the plane of the substrate 1 is not overlapped with the orthographic projection of the LED laminated structure 3 on the plane of the substrate 1, and the second electrode 24 is multiplexed into a cathode of the LED laminated structure 3.
Referring to fig. 9 and 10, fig. 9 is a flowchart of another method for manufacturing a monolithically integrated device of HEMT and LED according to the present invention, fig. 10 is a schematic diagram of the manufacturing method shown in fig. 9, and the embodiment shown in fig. 9 is further refined based on the above embodiment, where the manufacturing method includes:
s210, providing a substrate.
S220, sequentially preparing a channel layer and a barrier layer on the surface of the substrate.
As shown in fig. 10 (b), the channel layer 20 and the barrier layer 21 are prepared in the same manner as in the above embodiment, and will not be described again here.
S230, sequentially preparing an active layer to be processed and a hole transport layer to be processed on one side of the barrier layer, which is away from the channel layer.
Referring to fig. 10 (c), an entire layer of the active layer to be treated 34 and the hole transport layer to be treated 35 may be sequentially grown on the side of the barrier layer 21 facing away from the channel layer 20. The active layer 34 to be processed may be an InGaN/GaN quantum well active layer of a whole layer, the InGaN/GaN quantum well active layer may be prepared by using an MOCVD process, the number of periods of the InGaN/GaN quantum well active layer is 1-5, and specific process parameters of the InGaN layer may be: the temperature is 700-800 ℃, the pressure is 200-600 mbar, the V-III ratio is 10000-40000, and the carrier gas is N 2 The thickness of each InGaN layer is 2-3 nm; the specific process parameters of the GaN layer can be as follows: the temperature is 830-950 ℃, the pressure is 200-600 mbar, the V-III ratio is 5000-20000, and the carrier gas is N 2 The thickness of each GaN layer is 8-15 nm.
The hole transport layer 35 to be treated may be a p-type GaN layer, and may be prepared by using an MOCVD process, and specific process parameters may be: the temperature is 950-1100 ℃; the pressure is 100-400 mbar; the V-III ratio is 500-3000; the carrier gas being H 2 Or H 2 And N 2 The thickness of the p-type GaN layer is 100-500 nm.
It should be noted that, the specific preparation process parameters of the film provided in the embodiments of the present application are merely examples, and are not limiting to the preparation process, and in the practical application process, a person skilled in the art may adjust each process parameter according to the actual requirement.
And S240, etching the active layer to be processed and the hole transport layer to be processed to remove at least part of the active layer to be processed and the hole transport layer to be processed, so as to form the active layer and the hole transport layer.
Referring to fig. 10 (d), the active layer 34 to be treated and the hole transport layer 35 to be treated may be selectively removed in a partial region using photolithography and etching processes or the like. The removed region exposes the barrier layer 21, and the remaining region forms the active layer 31 and the hole transport layer 32 of the LED stack structure 3.
Further, the photoetching process can comprise the processes of gluing, exposing, developing, photoresist removing and the like; the etching process may be a dry etching process, such as an inductively coupled plasma dry etching (Inductively Couple Plasma, ICP) process, but is not limited thereto. The specific parameters of the above process can be set by those skilled in the art according to actual requirements, and the present invention is not described in detail herein.
S250, preparing a second electrode and a grid electrode respectively on one side of the barrier layer, which is far away from the channel layer, wherein the orthographic projection of the second electrode and the grid electrode on the plane of the substrate is not overlapped with the orthographic projection of the LED laminated structure on the plane of the substrate, and the second electrode is multiplexed to be a cathode of the LED laminated structure.
Referring to fig. 10 (e), the second electrode 24 and the gate electrode 25 may be deposited using photolithography and an electron beam evaporation process. Specifically, the second electrode window (not shown) and the gate window (not shown) may be etched by standard photolithography techniques, and then the second electrode 24 may be deposited in the second electrode window and the gate 25 may be deposited in the gate window using an electron beam evaporation process. Before the second electrode 24 and the gate electrode 25 are prepared, the first electrode 23 of the HEMT stack structure 2 may also be prepared on the side of the LED stack structure 3 facing away from the barrier layer 21, and the preparation manner of the first electrode 23 is the same as that in the above embodiment, which is not repeated here. The first electrode 23 is multiplexed as an anode of the LED stack structure, and the second electrode 24 is multiplexed as a cathode of the LED stack structure 3.
Further, after the first electrode 23 and the second electrode 24 are deposited by the electron beam evaporation process, the first electrode 23 and the second electrode 24 may be annealed, and the annealed first electrode 23 and second electrode 24 may form a better ohmic contact with the adjacent semiconductor material layer. Optionally, the annealing temperature in the annealing process can be 750-900 ℃, and the annealing time can be 30-60 s, but is not limited to the above.
Alternatively, in other possible embodiments, the electron transport layer 30 may include a first electron transport layer 301 and a second electron transport layer 302, the two-dimensional electron gas layer 22 is multiplexed into the first electron transport layer 301, and the led stack structure 3 further includes an active layer 31 and a hole transport layer 32 stacked along a plane direction perpendicular to the substrate 1; preparing HEMT stacked structure 2 and LED stacked structure 3 on one side surface of substrate 1 can be further refined to: sequentially preparing a channel layer 20 and a barrier layer 21 on the surface of a substrate 1; preparing a second electron transport layer 302 in a partial region of the barrier layer 21 on the side facing away from the channel layer 20; an active layer 31 is prepared on the side of the second electron transport layer 302 facing away from the barrier layer 21; a hole transport layer 32 is prepared on the side of the active layer 31 facing away from the second electron transport layer 302.
Referring to fig. 11 and 12, fig. 11 is a flowchart of a method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention, and fig. 12 is a schematic diagram of the method for manufacturing fig. 11, where the method for manufacturing the monolithic integrated device includes:
s310, providing a substrate.
S320, sequentially preparing a channel layer and a barrier layer on the surface of the substrate.
The preparation methods of the channel layer 20 and the barrier layer 21 are the same as those in the above embodiments, and will not be repeated here.
S330, preparing a second electron transport layer in a partial area of one side of the barrier layer, which is away from the channel layer.
Referring to fig. 12 (c), the second electron transport layer 302 may be an n-type GaN layer, which may be prepared by using an MOCVD process, and specific process parameters may be: the temperature is 1000-1100 ℃; the pressure is 100-400 mbar; the V-III ratio is 10-1000; the carrier gas being N 2 Or H 2 And N 2 The method comprises the steps of carrying out a first treatment on the surface of the The thickness of the n-type GaN layer is 20-50 nm. The second electron transport layer 302 may provide a growth platform for other film layers of the subsequent LED stack structure 3.
S340, preparing an active layer on one side of the second electron transport layer, which is away from the barrier layer.
Referring to fig. 12 (d), unlike the embodiment shown in fig. 10, in the embodiment shown in fig. 11, the active layer 31 may be grown on the surface of the second electron transport layer 302 only by using a mask, the active layer 31 may be an InGaN/GaN quantum well active layer, and the number of periods of the InGaN/GaN quantum well active layer may be 1-10, where specific process parameters of the InGaN layer and GaN layer are the same as those in the embodiment shown in fig. 8, and are not repeated here.
And S350, preparing a hole transport layer on one side of the active layer, which is away from the second electron transport layer.
Referring to fig. 12 (e), a hole transport layer 32 is grown on a side of the active layer 31 away from the second electron transport layer 302 by using a mask, the hole transport layer 32 may be a p-type GaN layer, the p-type GaN layer may be prepared by using an MOCVD process, specific process parameters may be the same as those in the embodiment shown in fig. 10, and the thickness of the p-type GaN layer may be in the range of 50-300 nm.
Optionally, before the hole transport layer 32 is grown, an electron blocking layer 33 may be further prepared on a side of the active layer 31 facing away from the second electron transport layer 302, for example, an AlGaN electron blocking layer may be prepared by using an MOCVD process, and specific process parameters may be: the temperature is 950-1100 ℃; the pressure is 100-200 mbar; the V-III ratio is 500-3000; the carrier gas being H 2 Or H 2 And N 2 The thickness of the AlGaN electron blocking layer is about 10-30 nm.
After the hole transport layer 32 is prepared, the first electrode 23 may be prepared on the side of the hole transport layer 32 facing away from the electron blocking layer 33, and the second electrode 24 and the gate electrode 25 may be prepared on the side of the barrier layer 21 facing away from the channel layer 20.
The embodiment shown in fig. 12 has the advantage that the LED laminated structure 3 is prepared by adopting a bottom-up growth mode, and the LED laminated structure 3 does not need to be etched, so that the problem of reduced luminous efficiency caused by side wall damage due to etching can be effectively solved.
Optionally, referring to fig. 13, fig. 13 is a schematic diagram of a method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention, where the method for manufacturing fig. 13 is further refined on the basis of the above embodiment, before the second electron transport layer 302 is manufactured in a partial area of the barrier layer 21 on the side facing away from the channel layer 20, the method may further include: preparing a dielectric layer 5 on the surface of one side of the barrier layer 21 away from the channel layer 20; etching the dielectric layer 5 to form a first opening 51 in the dielectric layer 5; preparing the second electron transport layer 302 in a partial region of the barrier layer 21 on the side facing away from the channel layer 20 may include: a second electron transport layer 302 is deposited within the first opening 51 such that at least a portion of the second electron transport layer 302 fills within the first opening 51 and contacts the barrier layer 21.
Specifically, in this embodiment, as shown in fig. 13 (b), after the preparation of the barrier layer 21 is completed, the entire dielectric layer 5 may be prepared on the surface of the barrier layer 21, and the dielectric layer 5 may be prepared by using processes such as plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), atomic layer deposition (Atomiclayer Deposition, ALD), or magnetron sputtering.
As shown in fig. 13 (c), the dielectric layer 5 in a partial region is removed by using photolithography and etching processes, so as to form a first opening 51, where the first opening 51 is used as a growth window of the subsequent LED stacked structure 3, and the length and width of the first opening 51 in the plane direction where the dielectric layer 5 is located may be within a range of 50-600 nm, and the distance between any two adjacent first openings 51 may be within a range of 500 nm-5 um, but is not limited thereto.
As shown in fig. 13 (d), the second electron transport layer 302 may be grown in the first opening 51 by using an MOCVD process, and the preparation process of the second electron transport layer 302 is the same as that of the above embodiment, and will not be repeated here. The thickness of the second electron transport layer 302 may be controlled within a range of 20-50 nm, such that the upper surface of the second electron transport layer 302 is higher than the upper surface of the dielectric layer 5.
Referring to fig. 13 (e), an active layer 31, an electron blocking layer 33 and a hole transporting layer 32 are sequentially grown on the side of the second electron transporting layer 302 facing away from the barrier layer 21, and the preparation process of the above-mentioned film layer may refer to any of the above-mentioned embodiments, which are not repeated here.
Optionally, in a possible embodiment, the HEMT stacked structure 2 further includes the second electrode 24 and the gate electrode 25, and after the hole transport layer 32 is prepared on the side of the active layer 31 facing away from the second electron transport layer 302, further includes: etching the dielectric layer 5 again to form a second opening 52 in the dielectric layer 5, wherein the orthographic projection of the second opening 52 on the plane of the substrate 1 is not overlapped with the orthographic projection of the first opening 51 on the plane of the substrate 1; preparing a second electrode 24 in the second opening 52, wherein the second electrode 24 is filled in the second opening 52 and is in contact with the barrier layer 21, and the second electrode 24 is multiplexed into a cathode of the LED laminated structure 3; a gate electrode 25 is provided on the side surface of the dielectric layer 5 facing away from the barrier layer 21.
Specifically, referring to fig. 13 (f), after the hole transport layer 32 is prepared, a part of the dielectric layer 5 may be removed again by photolithography and etching processes to form the second opening 52 in the dielectric layer 5. The second opening 52 is an electrode window, and as shown in fig. 13 (g), the electron beam evaporation process may be used to deposit the second electrode 24 in the second opening 52, deposit the first electrode 23 on the hole transport layer 32 side facing away from the active layer 31, and deposit the gate electrode 25 on the dielectric layer 5 side facing away from the barrier layer 21. The first electrode 23 and the second electrode 24 form ohmic contact with the semiconductor material layer after annealing, and the gate electrode 25 forms schottky contact with the barrier layer 21.
Optionally, before the dielectric layer 5 is etched to form the second opening 52 in other alternative embodiments, a protective layer may be further deposited on the dielectric layer 5 and the hole transport layer 32 of the LED stack 3, where the protective layer covers the dielectric layer 5, the upper surface of the LED stack 3, and the sidewalls of the LED stack 3. Subsequently, the protective layer and the dielectric layer 5 may be etched simultaneously to remove a part of the protective layer and the dielectric layer 5, forming a second opening 52 in the dielectric layer 5, and forming a third opening and a fourth opening in the protective layer. The third opening communicates with the second opening 52 and the fourth opening is located between the second opening 52 and the third opening. The third opening and the second opening 52 are second electrode windows, and the second electrode 24 is deposited within the second opening 52 and a portion of the third opening; the fourth opening is a gate window, and a gate 25 is deposited in a portion of the fourth opening.
Specifically, the flow of the preparation method provided by the invention is described in detail below by way of a specific example. Referring to fig. 14, fig. 14 is a schematic diagram of another method for manufacturing a monolithic integrated device of HEMT and LED according to the present invention, the method includes:
1) As shown in fig. 14 (a), a buffer layer 4, a channel layer 20, and a barrier layer 21 are sequentially prepared on the surface of a substrate 1.
2) As shown in fig. 14 (b), a dielectric layer 5 is prepared on the surface of the barrier layer 21 on the side facing away from the channel layer 20.
3) As shown in fig. 14 (c), the dielectric layer 5 is etched to form a first opening 51 in the dielectric layer 5.
4) As shown in fig. 14 (d), a second electron transport layer 302, an active layer 31, an electron blocking layer 33, and a hole transport layer 32 are sequentially deposited within the first opening 51 to form the LED stack structure 3.
5) As shown in fig. 14 (e) and 14 (f), a protective layer 6 is deposited on the surfaces of the dielectric layer 5 and the hole transport layer 32 of the LED stack structure 3, the protective layer 6 and the dielectric layer 5 are etched, the protective layer 6 and the dielectric layer 5 in a partial region are removed, a second opening 52 is formed in the dielectric layer 5, and a third opening 61 and a fourth opening 62 are formed in the protective layer 6.
6) As shown in fig. 14 (f) and 14 (g), the first electrode 23 is deposited on the side of the hole transport layer 32 facing away from the electron blocking layer 33, the second electrode 24 is deposited in the second opening 52 and part of the third opening 61, and the gate electrode 25 is deposited in part of the fourth opening 62, forming a complete monolithically integrated device.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (12)

1. A monolithically integrated device of a HEMT and an LED, comprising:
a substrate;
a HEMT laminated structure and an LED laminated structure arranged on one side of the substrate;
the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of the substrate, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transmission layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transmission layer.
2. The HEMT and LED monolithically integrated device of claim 1, wherein the HEMT stack structure further comprises a first electrode, the first electrode being located on a side of the LED stack structure facing away from the barrier layer, the first electrode being multiplexed as an anode of the LED stack structure.
3. The HEMT and LED monolithically integrated device of claim 1, wherein the LED stack structure further comprises an active layer and a hole transport layer stacked in a direction perpendicular to the plane of the substrate, the active layer being on a surface of the barrier layer on a side facing away from the channel layer, the hole transport layer being on a side of the active layer facing away from the barrier layer;
The HEMT laminated structure further comprises a second electrode and a grid electrode, wherein the second electrode and the grid electrode are positioned on one side of the barrier layer, which is away from the channel layer; the orthographic projection of the second electrode and the grid electrode on the plane of the substrate is not overlapped with the orthographic projection of the LED laminated structure on the plane of the substrate, and the second electrode is multiplexed to be a cathode of the LED laminated structure.
4. The HEMT and LED monolithically integrated device of claim 1, wherein the electron transport layer comprises a first electron transport layer and a second electron transport layer, the two-dimensional electron gas layer being multiplexed into the first electron transport layer, the second electron transport layer being located on a side surface of the barrier layer facing away from the channel layer;
the LED laminated structure further comprises an active layer and a hole transport layer which are laminated along the direction vertical to the plane of the substrate; the active layer is located between the second electron transport layer and the hole transport layer.
5. The HEMT and LED monolithically integrated device of claim 4, further comprising a dielectric layer on a side surface of the barrier layer facing away from the channel layer; the dielectric layer comprises a first opening, and at least part of the second electron transport layer is filled in the first opening and is in contact with the barrier layer;
And the surface of one side of the second electron transmission layer, which is away from the barrier layer, is higher than the surface of one side of the dielectric layer, which is away from the barrier layer.
6. The HEMT and LED monolithically integrated device of claim 5, wherein the dielectric layer further comprises a second opening, the orthographic projection of the second opening on the plane of the substrate does not overlap with the orthographic projection of the first opening on the plane of the substrate;
the HEMT laminated structure further comprises a second electrode and a grid electrode, wherein the second electrode is filled in the second opening and is in contact with the barrier layer, and the second electrode is multiplexed to be a cathode of the LED laminated structure; the grid electrode is positioned on one side surface of the dielectric layer, which is away from the barrier layer.
7. A preparation method of a monolithic integrated device of HEMT and LED is characterized by comprising the following steps:
providing a substrate;
preparing a HEMT laminated structure and an LED laminated structure on one side surface of the substrate; the HEMT laminated structure comprises a channel layer and a barrier layer which are sequentially laminated on the surface of a substrate, wherein a two-dimensional electron gas layer is formed between the channel layer and the barrier layer; the LED laminated structure comprises an electron transmission layer, and the two-dimensional electron gas layer is multiplexed into at least part of the electron transmission layer.
8. The method for manufacturing a monolithically integrated device of HEMT and LED according to claim 7, wherein manufacturing a HEMT stack structure and an LED stack structure on one side surface of the substrate comprises:
sequentially preparing the channel layer and the barrier layer on the surface of the substrate;
preparing the LED laminated structure on one side of the barrier layer away from the channel layer;
and preparing a first electrode of the HEMT laminated structure on one side of the LED laminated structure, which is far away from the barrier layer, wherein the first electrode is multiplexed to be an anode of the LED laminated structure.
9. The method for manufacturing a monolithically integrated device of HEMT and LED according to claim 7, wherein said two-dimensional electron gas layer is multiplexed into said electron transport layer, and said LED stack structure further comprises an active layer and a hole transport layer stacked in a direction perpendicular to a plane in which said substrate is located;
preparing a HEMT laminated structure and an LED laminated structure on one side surface of the substrate, wherein the HEMT laminated structure and the LED laminated structure comprise:
sequentially preparing the channel layer and the barrier layer on the surface of the substrate;
sequentially preparing an active layer to be treated and a hole transport layer to be treated on one side of the barrier layer, which is away from the channel layer;
etching the active layer to be treated and the hole transport layer to be treated to remove at least part of the active layer to be treated and the hole transport layer to be treated, so as to form the active layer and the hole transport layer;
The HEMT laminated structure further comprises a second electrode and a grid electrode, and the HEMT laminated structure and the LED laminated structure are prepared on one side surface of the substrate, and the HEMT laminated structure further comprises:
preparing a second electrode and a grid electrode respectively on one side of the barrier layer, which is far away from the channel layer, wherein orthographic projections of the second electrode and the grid electrode on a plane where the substrate is located are not overlapped with orthographic projections of the LED laminated structure on the plane where the substrate is located, and the second electrode is multiplexed to be a cathode of the LED laminated structure.
10. The method for manufacturing a monolithically integrated device of a HEMT and an LED according to claim 7, wherein the electron transport layer comprises a first electron transport layer and a second electron transport layer, the two-dimensional electron gas layer is multiplexed to the first electron transport layer, and the LED stack structure further comprises an active layer and a hole transport layer stacked in a direction perpendicular to a plane of the substrate;
preparing a HEMT laminated structure and an LED laminated structure on one side surface of the substrate, wherein the HEMT laminated structure and the LED laminated structure comprise:
sequentially preparing the channel layer and the barrier layer on the surface of the substrate;
preparing the second electron transport layer in a partial region of one side of the barrier layer, which is away from the channel layer;
Preparing the active layer on one side of the second electron transport layer away from the barrier layer;
and preparing the hole transport layer on one side of the active layer, which is away from the second electron transport layer.
11. The method of manufacturing a monolithically integrated device of a HEMT and an LED according to claim 10, further comprising, before the second electron transport layer is manufactured in the partial region of the barrier layer on the side facing away from the channel layer:
preparing a dielectric layer on the surface of one side of the barrier layer, which is away from the channel layer;
etching the dielectric layer to form a first opening in the dielectric layer;
preparing the second electron transport layer in a partial region of the barrier layer on the side facing away from the channel layer, wherein the second electron transport layer comprises:
the second electron transport layer is deposited within the first opening such that at least a portion of the second electron transport layer fills within the first opening and contacts the barrier layer.
12. The method of manufacturing a monolithically integrated device of a HEMT and an LED of claim 11, wherein the HEMT stack structure further comprises a second electrode and a gate electrode, and wherein after the hole transport layer is manufactured on a side of the active layer facing away from the second electron transport layer, further comprising:
Etching the dielectric layer again to form a second opening in the dielectric layer, wherein the orthographic projection of the second opening on the plane of the substrate is not overlapped with the orthographic projection of the first opening on the plane of the substrate;
preparing the second electrode in the second opening, wherein the second electrode is filled in the second opening and is in contact with the barrier layer, and the second electrode is multiplexed to be a cathode of the LED laminated structure;
and preparing the grid electrode on the surface of one side of the dielectric layer, which is away from the barrier layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810707A (en) * 2014-12-31 2016-07-27 黄智方 Structure of high-electron-mobility light-emitting transistor
CN108847419A (en) * 2018-07-10 2018-11-20 南方科技大学 A kind of single-slice integrated semiconductor array device and preparation method thereof
CN115064563A (en) * 2022-06-28 2022-09-16 天津工业大学 HEMT and blue light LED monolithic integrated chip and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810707A (en) * 2014-12-31 2016-07-27 黄智方 Structure of high-electron-mobility light-emitting transistor
CN108847419A (en) * 2018-07-10 2018-11-20 南方科技大学 A kind of single-slice integrated semiconductor array device and preparation method thereof
CN115064563A (en) * 2022-06-28 2022-09-16 天津工业大学 HEMT and blue light LED monolithic integrated chip and preparation method thereof

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