CN116225977B - Memory address determining method and circuit system - Google Patents
Memory address determining method and circuit system Download PDFInfo
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- CN116225977B CN116225977B CN202310511226.7A CN202310511226A CN116225977B CN 116225977 B CN116225977 B CN 116225977B CN 202310511226 A CN202310511226 A CN 202310511226A CN 116225977 B CN116225977 B CN 116225977B
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- G06F12/02—Addressing or allocation; Relocation
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Abstract
The embodiment of the invention provides a memory address determining method and a circuit system, which relate to the technical field of data storage, wherein the circuit system comprises: the method comprises the steps of connecting a first register, comparators, second registers, third registers and a conversion circuit, wherein the first register is connected with the comparators, each second register is connected with one comparator, each second register is used for storing a security code, and each comparator is respectively connected with one pin of the third register, and the method comprises the following steps: the first register obtains a target security code of the target security and sends the code to the comparator; the comparator compares the target security code with the security code stored in the second register, and stores the comparison result into a bit corresponding to a pin connected with the comparator in the third register; the conversion circuit determines a storage address for storing security information of the target security based on the data in the third register. By applying the scheme provided by the embodiment of the invention, the efficiency of stock information storage can be improved.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a method and a circuit system for determining a storage address.
Background
The securities information of securities has an important reference function for traders, for example, information such as trade prices contained in the securities information affects the traders to buy or sell securities. For this reason, it is necessary to store the ticket information.
In the prior art, when storing the ticket information, the storage address of the ticket information of the security is generally determined based on the hash value of the security code of the security, and then the ticket information of the security is stored based on the determined storage address.
However, the hash values of different security codes may have collision problems, that is, the hash values of the security codes of a plurality of different securities may be the same, so that when determining a storage address for storing security information of the securities, the plurality of securities are mapped to the same storage address, and thus the storage address needs to be determined again for the securities to solve the hash collision problems, and the time required for determining the storage address again is long, resulting in slow speed and low efficiency of determining the storage address, and thus the storage efficiency of the security information is low.
Disclosure of Invention
The embodiment of the invention aims to provide a storage address determining method and a circuit system so as to improve the efficiency of stock information storage. The specific technical scheme is as follows:
The embodiment of the invention provides a memory address determining method which is applied to a circuit system, wherein the circuit system comprises the following components: the method comprises the steps of connecting a first register with comparators, wherein the number of the second registers is equal to that of the comparators, each second register is connected with one comparator, each second register is used for storing one security code in a preset security code sequence, and each comparator is respectively connected with one pin of the third register, and the method comprises the following steps:
the first register obtains a target security code of a target security and sends the target security code to the comparator;
the comparator compares the received target security code with the security code stored in the second register connected with the comparator to obtain a comparison result, and stores the comparison result into a bit corresponding to the target sequence number in the third register, wherein the target sequence number is: a serial number of a pin connected with the comparator in the third register;
the conversion circuit determines a storage address for storing security information of the target security based on the bit stored in the third register, and outputs the storage address.
The embodiment of the invention also provides a circuit system, which comprises: the device comprises a first register, comparators, second registers, third registers and a conversion circuit, wherein the first registers are connected with the comparators, the second registers are equal to the comparators in number, each second register is connected with one comparator, each second register is used for storing one security code in a preset security code sequence, and each comparator is respectively connected with one pin of the third register;
the first register is used for obtaining a target security code of a target security and sending the target security code to a comparator corresponding to the first register;
the comparator is configured to compare the received target security code with the security code stored in the second register connected to the comparator, obtain a comparison result, and store the comparison result to a bit corresponding to the target sequence number in the third register, where the target sequence number is: a serial number of a pin connected with the comparator in the third register;
the conversion circuit is configured to determine a storage address for storing security information of the target security based on the bit stored in the third register, and output the storage address.
The embodiment of the invention has the beneficial effects that:
in the scheme provided by the embodiment of the invention, the security codes in the second register are compared with the target security codes to obtain the comparison results of the target security codes and the security codes in each second register, and as each bit in the third register respectively stores the comparison results output by each comparator, each bit in the third register reflects the matching condition of the target security codes and the security codes in the security code sequence, and the bit stored in the third register changes along with the change of the matching condition of the target security codes and the security codes in the security code sequence, different storage addresses can be determined based on the bit stored in the third register for different target security codes, namely, different storage addresses can be obtained for different target security codes under the condition that the target security codes are matched with the security codes in different second registers, namely, different storage addresses are allocated for different security codes. In this way, the security information of different security codes can be stored in different storage addresses, and the problem of hash collision can not occur in the process of determining the storage addresses, so that the delay and jitter generated in the process of determining the storage addresses for the security codes due to the problem of hash collision are avoided. The time required for determining the memory address is reduced, and the efficiency of determining the memory address is improved.
Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.
Fig. 1 is a schematic structural diagram of a circuit system according to an embodiment of the present application;
FIG. 2 is a flowchart of a method for determining a memory address according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another circuit system according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of still another circuit system according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.
The application scenario of the embodiment of the present invention is described below.
In the field of securities trading, high frequency traders are often required to rapidly buy and sell securities in the financial market. For accurate buying and selling of securities, high frequency traders are often required to reference securities information, for which the trading platform is required to store a large amount of trading information. In addition, since the market information of securities changes rapidly, a quick trade is required for accurately buying and selling securities, and further, a trading platform is required to quickly store or read securities information to locally generate an order book of securities, and the order book of securities needs to be continuously and quickly updated with the time and market change. Thus, the high-frequency trader can extract and analyze the security information of the order book of the certificate, and further determine the trading time, the security position and the like.
For example, when the transaction software obtains the most current information for a security, a memory address for storing information for the security may be determined based on the designated addressing scheme. For another example, if information specifying a security is to be obtained from an order book, a storage address for storing information of the security may be determined based on the specified addressing mode.
The embodiment of the invention provides a storage address determining method which can be applied to hardware such as an ASIC (Application Specific Integrated Circuit ) and an FPGA (field programmable gate array, programmable gate array) and can also be applied to hardware equipment capable of realizing the circuit system provided by the embodiment of the invention.
From the above, the method for determining the storage address provided by the embodiment of the invention can be applied to the process of storing the information of the specified securities, and can also be applied to the process of acquiring the information of the specified securities.
In order to improve the efficiency of determining a storage address in the security information storage process, the embodiment of the invention provides a storage address determining method and a circuit system, and the storage address determining method provided by the embodiment of the invention is described in detail below with reference to the specific embodiment.
The embodiment of the invention provides a memory address determining method, which is applied to a circuit system, wherein the circuit system comprises: the device comprises first registers, comparators, second registers, third registers and a conversion circuit, wherein the first registers are connected with the comparators, the second registers are equal to the comparators in number, each second register is connected with one comparator, each second register is used for storing one security code in a preset security code sequence, and each comparator is respectively connected with one pin of the third register.
The concepts involved in the embodiments of the present invention are described below.
The first register is a register for acquiring the target security code and transmitting the target security code to the comparator. The second register is a register for storing security codes in a preset security code sequence. The third register is a register for storing the output result of the comparator. The first, second and third registers may each be any type of arbitrary bit number registers, such as EAX registers, EBX registers, etc.
The conversion circuit is a combinational logic circuit, and the combinational logic of the combinational logic circuit represents the corresponding relation between input data and output data, and specifically, the conversion circuit can be a lookup table circuit. Circuitry: the system is formed by connecting the first register, the comparator, the second register, the third register and the conversion circuit by circuits. Specific connection mode referring to the schematic structural diagram of a circuit system provided in fig. 1, the first register is connected to the comparator 1 and the comparator 2. The number of second registers is equal to the number of comparators, and each second register is connected to one comparator, for example, the second register 1 is connected to the comparator 1, the second register 2 is connected to the comparator 2, and the … … second register K is connected to the comparator K. Each comparator is connected with one pin of a third register, and the third register is connected with the conversion circuit. The connected components can communicate by sending and receiving binary data.
The security code sequence is a set formed by arranging all security codes according to a preset sequence. For example, security codes of securities in an order book may be arranged according to a preset order to obtain a security code sequence. The securities in the order book may refer to securities to which the securities information to be recorded in the order book to be synthesized belongs, or may refer to securities to which the securities information to be continuously updated in the order book belongs, or may refer to securities to which the securities information to be obtained from the order book belongs, which is not limited in the embodiment of the present invention.
The security code is a unique identifier of the security, and may be a 4-bit number identifier, a 6-bit number identifier, or an 8-bit identifier, which is not limited in the embodiment of the present invention.
As described above, each comparator corresponds to one second register, and in the case where one security code in the security code sequence is stored in the second register, each comparator can be implemented to correspond to one security code in the security code sequence, so that when the comparator receives the target security code and performs comparison, the corresponding security code can be acquired from the second register for comparison.
In one embodiment of the present invention, referring to fig. 2, fig. 2 provides a flow chart of a memory address determining method, which includes the following steps S201-S203.
Step S201: the first register obtains a target security code of the target security and sends the target security code to the comparator.
Where the target security is the security for which a storage address is currently required to be found. The target securities may be: the securities to which the stored securities information belongs or the securities to which the read securities information belongs, and the like.
An implementation of the first register to obtain the target security code of the target security is described below.
In one implementation, the first register may receive binary data transmitted by the circuit that characterizes the target security code.
Specifically, the transaction software may control an electronic system such as a single chip microcomputer or a microcontroller with a specified function, and the electronic system is connected to the first register, so that the transaction software may control the electronic system to send binary data representing the target security code into the first register. For example, after the transaction software obtains the target security information, the software may generate binary data representing the target security code based on the target security code of the target security to which the target security information belongs, and control the electronic system to send the binary data representing the target security code to the first register. For another example, when target security information needs to be obtained from the local order book, binary data characterizing the target security code may also be sent to the first register in the manner described above.
An implementation of the first register sending the target security code to the comparator is described below.
The first register can send binary data representing the target security code to the K comparators through a data transmission line connected with the comparators, namely, the process of sending the target security code to the comparators is realized. Where K may characterize the number of comparators and second registers.
Other implementations of step S201 of sending the target security code to the comparator are described in the embodiments below and are not described in detail herein.
Step S202: the comparator compares the received target security code with the security code stored in the second register connected with the comparator to obtain a comparison result, and stores the comparison result into the bit corresponding to the target serial number in the third register.
Wherein, the target sequence number is: and the serial number of the pin connected with the comparator in the third register.
The implementation of the comparator to compare the received target security code with the security code stored in the second register to which the comparator is connected is described below.
The comparator can obtain the security code from a second register connected with the comparator, if the security code is the same as the target security code, the comparison result representing that the security code is the same as the target security code is output, and if the security code is different from the target security code, the comparison result representing that the security code is different from the target security code is output. For example, the comparison result may be characterized by a binary value, the security code may be the same as the target security code by outputting a "1", and the security code may be different from the target security code by outputting a "0". In addition, the security code may be the same as the target security code by outputting "0", and different from the target security code by outputting "1", which is not limited in the embodiment of the present invention.
The connection relation between the pins of the third register and the comparators, the explanation of the target sequence numbers, and the implementation manner of storing the comparison result in the bit corresponding to the target sequence number in the third register are described below.
The third register may be a register including parallel input pins. Data is input to a designated parallel input pin in the third register, and data may be stored to designated bits stored in the third register. For example, when data is input to an 8-bit register, the 8 parallel input pins of the register are PL0-PL7, respectively, and it is assumed that the data to be input is: 11001100. then, 1 may be input to the PL0 pin of the register, then bit 0 of the register may record store 1, 1 may be input to the PL1 pin of the register, then bit 1 of the register may record store 1, 0 may be input to the PL2 pin of the register, then bit 2 of the register may record store 0, and so on, after corresponding data is input to all PL0-PL7 pins of the register, the register may record store data: 11001100. therefore, no matter the sequence of the input data, the specified data is input to the parallel input pin of the register, and the register can record and store the specified data.
In one implementation, each comparator may be connected to a parallel input pin designated by a third register. After the comparator obtains the comparison result, the comparison result can be input to a pin appointed by a third register connected with the comparator, so that bits corresponding to the target serial number in the third register can record and store the comparison result. For example, referring to FIG. 1, assume that the third register is an 8-bit register, the 8 parallel input pins of the third register are PL0-PL7, respectively, and K in FIG. 1 is 8. Then comparator 1 may be connected to PL7 of the third register, comparator 2 may be connected to PL6 of the third register, and so on, comparator 8 may be connected to PL0 of the third register. Then, the target sequence number corresponding to the comparator 1 may be 7, and after the comparator 1 obtains the comparison result, the comparator 1 may store the comparison result to the 7 th bit in the third register. Similarly, the comparator 2 may store the comparison result obtained by the comparator into the 6 th bit in the third register, and the comparator 8 may store the comparison result obtained by the comparator into the 0 th bit in the third register. Then, in the case where the output "1" indicates that the security code is the same as the target security code, and the output "0" indicates that the security code is different from the target security code, if only the comparison result of the comparator 2 is 1, the data stored in the third register may be: 00000010.
For another example, if comparator 1 is connected to PL0 of the third register, comparator 2 is connected to PL1 of the third register, and so on, comparator 8 is connected to PL7 of the third register. In the case where the output "1" indicates that the security code is the same as the target security code, and the output "0" indicates that the security code is different from the target security code, if only the comparison result of the comparator 2 is 1, the data stored in the third register may be: 01000000. based on the above example, if the connection mode between the comparator and the pin of the third register is unchanged, if only the comparison result of the comparator 1 is 1, the data stored in the third register may be: 10000000; if only the comparison result of the comparator 3 is 1, the data stored in the third register may be: 00100000; if only the comparison result of the comparator 8 is 1, the data stored in the third register may be: 00000001. then, based on the above example, if the connection manner of the pins of the comparator and the third register is unchanged, if only the comparison result of the comparator 1 is 1, the data stored in the third register may be: 10000000; if only the comparison result of the comparator 3 is 1, the data stored in the third register may be: 00100000; if only the comparison result of the comparator 8 is 1, the data stored in the third register may be: 00000001. in addition, the embodiment of the invention is not limited to the specific connection relation between the comparator and the pins of the third register.
It can be seen that, in the case that the connection manner of each comparator and the pin of the third register is determined, the comparison result of each comparator is stored in the bit of the target sequence number corresponding to the comparator in the third register, regardless of the comparison result of each comparator, so that each comparison result does not affect the bit of the other comparison results in the third register, and the bit in the third register is only affected by the comparator connected to the bit.
For another example, referring to fig. 1, a first security code in a security code sequence may be stored in the second register 1, a second security code in a security code sequence may be stored in the second register 2, and so on, a kth security code in a security code sequence may be stored in the second register K. In this case, the comparison result obtained at the comparator 1 characterizes whether the target security code matches a first security code in the security code sequence, the comparison result obtained at the comparator 2 characterizes whether the target security code matches a second security code in the security code sequence, and so on, the comparison result obtained at the comparator K characterizes whether the target security code matches a kth security code in the security code sequence. For another example, the K-th security code in the security code sequence may be stored in the second register 1, the K-1 st security code in the security code sequence may be stored in the second register 2, and so on, the 1 st security code in the security code sequence may be stored in the second register K. In this case, the comparison result obtained at the comparator 1 characterizes whether the target security code matches the kth security code in the security code sequence, the comparison result obtained at the comparator 2 characterizes whether the target security code matches the kth-1 security code in the security code sequence, and so on, the comparison result obtained at the comparator K characterizes whether the target security code matches the first security code in the security code sequence.
From the above, it can be seen that the comparison result of the comparator indicates that the meaning changes with the security code stored in the second register connected to the comparator, that is, in the case where the security code stored in the second register is determined, the comparison result by the comparator connected to the second register indicates that the meaning is unchanged, and that in the case where the connection of each comparator to the pins of the third register is determined, each comparison result does not affect a bit representing the other comparison result in the third register, and the bit in the third register is only affected by the comparator connected to the bit, so that in the case where the security code in the security code sequence is not repeated, the security code stored in the second register is determined, and the connection of each comparator to the pins of the third register is determined, if the target security code can be matched with the security code in the security code sequence, only one fixed bit in the third register indicates that the target security code is matched with the security code in the security code sequence, and thus the corresponding third stored security code in the third register is different.
That is, in the case where the obtained target security code is actually the same security code, the data stored in the third register record is the same. For example, if the target security code is actually the same security code, the target security code is only matched with the same security code in the second register in each process of determining the storage address, that is, only the same comparator can obtain a comparison result indicating that the target security code is matched with the security code in the security code sequence, and only the same pin in the third register can receive the comparison result, so that the bits stored in the third register are the same for each case that the target security code is actually the same security code.
Step S203: the conversion circuit determines a storage address for storing security information of the target security based on the bit stored in the third register, and outputs the storage address.
In one implementation, the pre-designed conversion circuit may obtain the bit sequence in the third register based on the bit stored in the third register according to a preset relationship between the bit sequence and the storage address, and determine the storage address for storing the security information of the target security according to the bit sequence.
For example, the above-described conversion circuit may be designed using a case statement in Verilog (a hardware description language), where the case statement may be used for multi-branch condition judgment. The case statement may execute different branches according to the corresponding variable values. That is, in the case where the conversion circuit is designed based on a Verilog case statement, the conversion circuit may execute different branches according to different bit sequences, and the different branches may be set to output different memory addresses. In this way the conversion circuit can be implemented to determine different memory addresses based on different bit sequences.
Other implementations of step S203 to determine the memory address are described in the embodiments below and are not described in detail herein.
In the scheme provided by the embodiment of the invention, the security codes in the second register are compared with the target security codes to obtain the comparison results of the target security codes and the security codes in each second register, and as each bit in the third register respectively stores the comparison results output by each comparator, each bit in the third register reflects the matching condition of the target security codes and the security codes in the security code sequence, and the bit stored in the third register changes along with the change of the matching condition of the target security codes and the security codes in the security code sequence, different storage addresses can be determined based on the bit stored in the third register for different target security codes, namely, different storage addresses can be obtained for different target security codes under the condition that the target security codes are matched with the security codes in different second registers, namely, different storage addresses are allocated for different security codes. In this way, the security information of different security codes can be stored in different storage addresses, and the problem of hash collision can not occur in the process of determining the storage addresses, so that the delay and jitter generated in the process of determining the storage addresses for the security codes due to the problem of hash collision are avoided. The time required for determining the memory address is reduced, and the efficiency of determining the memory address is improved.
In one embodiment of the present invention, in the case that the number of the first registers is equal to the number of comparators, and each first register is connected to one comparator, the implementation manner of sending the target security code to the comparator in step S201 may further be implemented by: the first register sends the target security code to the comparator connected thereto.
Referring to fig. 3, fig. 3 provides a schematic structural diagram of another circuit system, and the circuit system provided in fig. 3 is different from the circuit system provided in fig. 1 in that: each comparator in the circuitry provided in fig. 3 is coupled to a first register. For example, the first register 1 is connected to the comparator 1, the first register 2 is connected to the comparator 2, and the … … first register K is connected to the comparator K. In this implementation, each first register may store the same target security code, so that each comparator has an independent first register connected to it, and when each comparator performs comparison, the parallelism of the comparators can be improved, the comparison speed is improved, and the efficiency of determining the storage address is improved.
In one embodiment of the present invention, in a case where the number of comparators is greater than the number of security codes in the security code sequence, the storage address determining method further includes: if a new security code is added to the security code sequence, the new security code is stored in a second register in which no security code is stored.
Wherein, the security codes in the security code sequence are prestored in the second register, and in the case that the number of the comparators is larger than the number of the security codes in the security code sequence, the number of the second registers is also larger than the number of the security codes in the security code sequence, and then the registers without the security codes are stored in the second registers. When the user wishes to store information of a new security, a new security code may be directly added to any one of the second registers in which no security code is stored. Therefore, when the securities with the storage addresses to be determined are expanded, the circuit system can be directly input the securities codes needing to be expanded into the second register which does not store the securities codes, and the expansion can be realized, so that the operation of personnel is facilitated.
In one embodiment of the present invention, the process of determining the storage address in step S203 may be implemented in the following manner: the conversion circuit determines a first bit of the bits stored in the third register, the value of the first bit representing the matching of the target security with the security code in the security code sequence, obtains the bit sequence based on the serial number of the bit of the first bit stored in the third register, and determines a storage address for storing security information of the target security based on the bit sequence.
An implementation of determining the first bit is described below.
In one implementation, if each comparator outputs a "1" to indicate that the target security matches the security code in the security code sequence, a bit having a value of "1" in the bits stored in the third register may be determined as the first bit.
An implementation of obtaining the bit sequence based on the sequence number of the bit stored in the third register by the first bit will be described below.
In one implementation, the conversion circuit obtains a binary representation of the sequence number of the bits stored in the third register as the bit sequence. For example, if the first bit is 3 in the sequence number of the bit stored in the third register, a binary representation value of 3 may be obtained: 11 as a bit sequence. Therefore, different bit sequences can be determined according to different sequence numbers, the bit sequences are not repeated, the numerical value represented by the bit sequences is continuous, the storage addresses determined based on the continuous bit sequences can be continuous, the waste of the storage space can be reduced by the continuous storage addresses, and the utilization rate of the storage space is improved.
In another implementation manner, a correspondence between the sequence number of the bit stored in the third register by the first bit and the bit sequence may be preset, and the bit sequence is obtained according to the correspondence and the sequence number. For example, when the above sequence number is 1, 0000 may be determined as the bit sequence; when the above sequence number is 2, 0001 can be determined as a bit sequence; when the above sequence number is 3, 0010 can be determined as a bit sequence. The embodiment of the present disclosure does not limit the manner in which the bit sequence is obtained, but it is necessary to secure the sequence numbers of the bits stored in the third register for the different first bits, and it is possible to determine the different bit sequences.
An implementation of determining the memory address based on the bit sequence is described below.
In one implementation, the conversion circuit determines the value of each bit in [ the highest bit, the second bit ] in the memory address based on the bit sequence, and sets the value of each bit in [ the second bit-1, the lowest bit ] in the memory address to 0, where the sequence number of the second bit in the memory address is preset.
The memory address may be a memory base address, and may be divided into a higher address and a lower address. A storage base address for storing information of the target securities may be determined based on the higher order address. The low order address may characterize an offset for specific content in the information used to store the target securities. For example, assume that the memory address includes 8 bits in total, the upper address is 4 bits, and the lower address is 4 bits. If the higher address is 0001, 00010000 can be considered as the storage base address of the information of the target securities, then 00010001 may be an address storing the name information of the target securities, 00010010 may be an address storing the price information of the target securities, or the like.
The second bit may be used to distinguish between a higher order address and a lower order address in the memory address, e.g., [ the highest order bit, the second order bit ] in the memory address may be considered a higher order address and [ the second order bit-1, the lowest order bit ] may be considered a lower order address. And the number of bits in the [ most significant bit, second bit ] should ensure that the high order address can characterize each security code in the security code sequence. For example, if the number of individual security codes in the security code sequence is 8, the preset second bit should ensure that the number of bits in [ the highest bit, the second bit ] is 3 or more. In this way, the high-order address and the low-order address in the storage address for storing the information of the target securities can be adjusted through the second bit, namely, the high-order address with preset digits is reserved for each securities code, so that the allocated storage address can store the securities information of each securities, and the low-order address with preset digits is reserved, so that enough offset can be provided for storing the detailed content in the securities information of each securities, and the error rate for determining the Chuncheng address is reduced.
In another implementation manner, the value of any one section of bit of the preset number of bits in the storage address can be determined based on the bit sequence, that is, the bit sequence can be mapped into any one section of bit of the preset number of bits in the storage address, and other bits in the storage address can be set to 0. For example, if the memory address is 8 bits and the bit sequence is 1111, then the determined memory address may include any one of the following addresses: 11110000, 01111000, 00111100, 00011110, 00001111. The embodiment of the present invention does not limit the manner in which the storage address for storing the security information of the target security is determined based on the bit sequence.
An implementation of determining the value of each bit in the [ most significant bit, second bit ] in the memory address is described below.
In one embodiment, the bit sequence may be directly used as the value of each bit in [ the highest bit, the second bit ]. If the number of bits of the [ highest bit, second bit ] is higher than the bit sequence, 0 can be supplemented at the forefront of the bit sequence, so that the number of bits of the bit sequence is the same as the number of bits in the [ highest bit, second bit ].
In another embodiment of the present invention, the process of determining the storage address in step S203 may also be implemented by:
the conversion circuit may be designed as a circuit capable of implementing a CAM-like "Key-Value" (Key Value pair) lookup manner, that is, in the case where the security code in the second register is determined, and the target security can be matched with the security code in the second register, the Value of a bit corresponding to a unique security code matched with the target security stored in the third register may be determined according to the comparison result obtained by the comparison by the comparator, so as to obtain a unique corresponding storage address. The conversion circuit is simple to realize, and correspondingly, the adopted circuit is more simplified, the speed is higher, and the occupied chip area is smaller.
In addition, the circuits in the circuit system only need to complete the data transmission and reception in the process, and binary data comparison is realized, so that the circuit is simple, and the circuit can be suitable for application-specific integrated circuits such as various hardware, such as ASICs, FPGAs and the like.
As can be seen from the above, since the serial numbers of the bits stored in the third register of the first bits are changed only with the security code matching the target security, the serial numbers of the bits stored in the third register of the first bits are also different in the case of the security code being different, so that the obtained bit sequences are also different based on the above-mentioned serial numbers, so that different storage addresses can be determined based on different bit sequences for different security codes.
The overall flow of the memory address determination method is described below in conjunction with the schematic structure of the further circuitry provided in fig. 4.
As shown in fig. 4, the first registers obtain target security codes, for example, the first registers 1, 2, 3, 4 obtain target security codes, respectively. In fig. 4, if the total number of security codes in the security code sequence is 4, the security codes in the security code sequence are security codes 1, 2, 3, and 4 shown in the figure respectively. Then, the security codes 1 to 4 may be stored in the second registers 1 to 4, respectively. In this case, the first register obtains the target security code and sends the target security code to each comparator. The comparator may output as follows: if the compared security codes are different, 0 is input to the pin of the third register connected to the comparator, and if the compared security codes are the same, 1 is input to the pin of the third register connected to the comparator. If the target security code matches the security code 2, the comparator 2 inputs 1 to the pin connected to the comparator 2 in the third register, and the comparison results of the comparator 1, the comparator 3 and the comparator 4 are all 0. If the third register is a 4-bit register, including parallel input pins PL1-PL3, and pin PL1 of the third register is connected to comparator 2, then the stored bits in the third register are in turn: 0100.
Taking the bit width of 8 as an example, by the conversion circuit, it can be determined that the sequence number of the bit stored in the third register is 2 for the first bit of 0100 in the third register, and then the binary representation value 10 can be taken as the high order bit in the memory address. In the case where the second bit is the 4 th bit, the upper bit in the memory address may be determined to be 0010, and the lower bit in the memory address may be determined to be 0000, then. The storage address of the target security code is 00100000.
Corresponding to the above memory address determining method, the embodiment of the application also provides a circuit system.
In one embodiment of the present application, referring to fig. 1, fig. 1 provides a schematic structural diagram of a circuit system, the circuit system includes: the device comprises a first register, comparators, second registers, third registers and a conversion circuit, wherein the first register is connected with the comparators, the second registers are equal to the comparators in number, each second register is connected with one comparator, each second register is used for storing one security code in a preset security code sequence, and each comparator is respectively connected with one pin of the third register;
the first register is used for obtaining the target security code of the target security and sending the target security code to the comparator corresponding to the first register;
The comparator is used for comparing the received target security code with the security code stored in the second register connected with the comparator to obtain a comparison result, and storing the comparison result into the bit corresponding to the target sequence number in the third register, wherein the target sequence number is as follows: a serial number of a pin connected with the comparator in the third register;
and a conversion circuit for determining a storage address for storing security information of the target security based on the bit stored in the third register, and outputting the storage address.
In the scheme provided by the embodiment of the invention, the security codes in the second register are compared with the target security codes to obtain the comparison results of the target security codes and the security codes in each second register, and as each bit in the third register respectively stores the comparison results output by each comparator, each bit in the third register reflects the matching condition of the target security codes and the security codes in the security code sequence, and the bit stored in the third register changes along with the change of the matching condition of the target security codes and the security codes in the security code sequence, different storage addresses can be determined based on the bit stored in the third register for different target security codes, namely, different storage addresses can be obtained for different target security codes under the condition that the target security codes are matched with the security codes in different second registers, namely, different storage addresses are allocated for different security codes. In this way, the security information of different security codes can be stored in different storage addresses, and the problem of hash collision can not occur in the process of determining the storage addresses, so that the delay and jitter generated in the process of determining the storage addresses for the security codes due to the problem of hash collision are avoided. The time required for determining the memory address is reduced, and the efficiency of determining the memory address is improved.
In one embodiment of the application, in the case that the number of first registers is equal to the number of comparators, each first register is connected to one comparator, the first register is specifically configured to send the target security code to the comparator connected thereto. Thus, each comparator is provided with the independent first register which is connected, and when the comparators are compared, the parallelism of the comparators can be improved, the comparison speed is improved, and the efficiency of determining the storage address is improved.
In one embodiment of the application, the second register, which does not store security codes, is also used to store new security codes in case a new security code is added to the security code sequence, in case the number of comparators is greater than the number of security codes in the security code sequence.
Therefore, when the securities with the storage addresses to be determined are expanded, the circuit system can be directly input the securities codes needing to be expanded into the second register which does not store the securities codes, and the expansion can be realized, so that the operation of personnel is facilitated.
In one embodiment of the present application, the conversion circuit is specifically configured to determine a first bit having a value of 1 among bits stored in the third register, obtain a bit sequence based on a sequence number of the bit stored in the third register by the first bit, and determine a storage address for storing security information of the target security based on the bit sequence. As can be seen from the above, since the serial numbers of the bits stored in the third register of the first bits are changed only with the security code matching the target security, the serial numbers of the bits stored in the third register of the first bits are also different in the case of the security code being different, so that the obtained bit sequences are also different based on the above-mentioned serial numbers, so that different storage addresses can be determined based on different bit sequences for different security codes.
In one embodiment of the present application, the conversion circuit is specifically configured to determine, based on a bit sequence, a value of each bit in [ the highest bit, the second bit ] in the storage address, and set the value of each bit in [ the second bit-1, the lowest bit ] in the storage address to 0, where the sequence number of the second bit in the storage address is preset.
In this way, the high-order address and the low-order address in the storage address for storing the information of the target securities can be adjusted through the second bit, namely, the high-order address with preset digits is reserved for each securities code, so that the allocated storage address can store the securities information of each securities, and the low-order address with preset digits is reserved, so that enough offset can be provided for storing the detailed content in the securities information of each securities, and the error rate for determining the Chuncheng address is reduced.
In one embodiment of the present application, the conversion circuit is specifically configured to obtain, as the bit sequence, a binary representation value of the sequence number of the bit of the first bit stored in the third register.
Therefore, different bit sequences can be determined according to different sequence numbers, the bit sequences are not repeated, the numerical value represented by the bit sequences is continuous, the storage addresses determined based on the continuous bit sequences can be continuous, the waste of the storage space can be reduced by the continuous storage addresses, and the utilization rate of the storage space is improved.
In yet another embodiment of the present application, there is also provided a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the storage address determination methods of the above embodiments.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (6)
1. A memory address determination method, applied to circuitry, the circuitry comprising: the method comprises the steps of connecting a first register with comparators, wherein the number of the second registers is equal to that of the comparators, each second register is connected with one comparator, each second register is used for storing one security code in a preset security code sequence, and each comparator is respectively connected with one pin of the third register, and the method comprises the following steps:
the first register obtains a target security code of a target security and sends the target security code to the comparator;
the comparator compares the received target security code with the security code stored in the second register connected with the comparator to obtain a comparison result, and stores the comparison result into a bit corresponding to the target sequence number in the third register, wherein the target sequence number is: a serial number of a pin connected with the comparator in the third register;
The conversion circuit determines a storage address for storing security information of the target security based on the bit stored in the third register, and outputs the storage address;
wherein the conversion circuit determines a storage address for storing security information of the target security based on the bit stored in the third register, comprising:
the conversion circuit determines a first bit of the bits stored in the third register, wherein the value of the first bit represents that the target securities are matched with the securities codes in the securities code sequence, obtains a bit sequence based on the serial number of the bit stored in the third register by the first bit, and determines a storage address for storing securities information of the target securities based on the bit sequence;
the conversion circuit determining a storage address for storing security information of the target security based on the bit sequence, comprising:
the conversion circuit determines the value of each bit in [ the highest bit and the second bit ] in the storage address based on the bit sequence, and sets the value of each bit in [ the second bit-1 and the lowest bit ] in the storage address to 0, wherein the sequence number of the second bit in the storage address is preset.
2. The method of claim 1, wherein the first registers are equal in number to the comparators, each first register being coupled to a comparator, the first register sending the target security code to the comparator, comprising:
the first register sends the target security code to a comparator connected thereto.
3. The method of claim 1, wherein the converting circuit obtains a bit sequence based on a sequence number of bits of the first bit stored in the third register, comprising:
the conversion circuit obtains a binary representation value of the sequence number of the bit stored in the third register as the bit sequence.
4. A circuit system, the circuit system comprising: the device comprises a first register, comparators, second registers, third registers and a conversion circuit, wherein the first registers are connected with the comparators, the second registers are equal to the comparators in number, each second register is connected with one comparator, each second register is used for storing one security code in a preset security code sequence, and each comparator is respectively connected with one pin of the third register;
The first register is used for obtaining a target security code of a target security and sending the target security code to a comparator corresponding to the first register;
the comparator is configured to compare the received target security code with security codes in a second register connected to the comparator, obtain a comparison result, and store the comparison result into a bit corresponding to a target sequence number in the third register, where the target sequence number is: a serial number of a pin connected with the comparator in the third register;
the conversion circuit is used for determining a storage address for storing security information of the target security based on the bit stored in the third register and outputting the storage address;
the conversion circuit is specifically configured to determine a first bit with a value of 1 in bits stored in the third register, obtain a bit sequence based on a sequence number of the bit stored in the third register by the first bit, and determine a storage address for storing security information of the target security based on the bit sequence;
the conversion circuit is specifically configured to determine, based on the bit sequence, a value of each bit in [ the highest bit, the second bit ] in the storage address, and set the value of each bit in [ the second bit-1, the lowest bit ] in the storage address to 0, where a sequence number of the second bit in the storage address is preset.
5. The circuit system of claim 4, wherein the circuit system further comprises a logic circuit,
in case the number of first registers is equal to the number of comparators, each first register is connected to one comparator, the first register is specifically configured to send the target security code to the comparator connected thereto.
6. The circuit system of claim 4, wherein the circuit system further comprises a logic circuit,
the conversion circuit is specifically configured to obtain, as the bit sequence, a binary representation value of a sequence number of the bit stored in the third register by the first bit.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665953A (en) * | 1996-02-14 | 1997-09-09 | Lobar Code Inc. | Self-contained personal data collector for redeeming coupons |
| CN1333891A (en) * | 1998-11-16 | 2002-01-30 | 因芬尼昂技术股份公司 | Using page tag registers to track state of physical pages in memory device |
| CN103440881A (en) * | 2013-08-12 | 2013-12-11 | 平湖凌云信息科技有限公司 | Content addressable memory system, addressing method and addressing device |
| CN113254389A (en) * | 2021-06-07 | 2021-08-13 | 深圳华云信息系统有限公司 | Data processing method and device based on FPGA, electronic equipment and storage medium |
| CN113903392A (en) * | 2020-06-22 | 2022-01-07 | 爱思开海力士有限公司 | Memory, memory system and operation method of memory system |
-
2023
- 2023-05-09 CN CN202310511226.7A patent/CN116225977B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665953A (en) * | 1996-02-14 | 1997-09-09 | Lobar Code Inc. | Self-contained personal data collector for redeeming coupons |
| CN1333891A (en) * | 1998-11-16 | 2002-01-30 | 因芬尼昂技术股份公司 | Using page tag registers to track state of physical pages in memory device |
| CN103440881A (en) * | 2013-08-12 | 2013-12-11 | 平湖凌云信息科技有限公司 | Content addressable memory system, addressing method and addressing device |
| CN113903392A (en) * | 2020-06-22 | 2022-01-07 | 爱思开海力士有限公司 | Memory, memory system and operation method of memory system |
| CN113254389A (en) * | 2021-06-07 | 2021-08-13 | 深圳华云信息系统有限公司 | Data processing method and device based on FPGA, electronic equipment and storage medium |
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