CN116225370A - Method, system, storage medium and electronic equipment for realizing division operation on MCU - Google Patents
Method, system, storage medium and electronic equipment for realizing division operation on MCU Download PDFInfo
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Abstract
The invention discloses a method, a system, a storage medium and an electronic device for realizing division operation on an MCU, wherein a dividend A and a divisor B are integers, binary division operation is required to be carried out, and the method comprises the following steps: judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, assigning the divisor B to B1, comparing B1 with the dividend A, and determining the optimal shift number i of the divisor B1 through continuous left shift and repeated comparison of B1; the divisor A is subtracted from the divisor B1 after being compared, the divisor A is assigned, meanwhile, 1 is added with a quotient C after being shifted leftwards by a step length by a bit number i and assigned to the quotient C, and then B1 is shifted rightwards and the bit number i is subtracted by 1, and the operation is repeatedly carried out until the divisor A is equal to 0 or the divisor A is smaller than the divisor B, so that a final quotient C is obtained. The invention saves the cost of devices, is beneficial to improving the competitiveness of products, greatly improves the operation efficiency of division, limits the error to be small and can be practically applied.
Description
Technical Field
The present invention relates to the field of embedded systems, and in particular, to a method, a system, a storage medium, and an electronic device for implementing division operation on an MCU.
Background
In embedded systems, due to the high sensitivity of the product to cost, a MCU with limited resources is usually selected to save cost. These MCUs can meet most application needs, but some applications require division, for example, dividing the actual measured value by the theoretical value to correct certain parameters or curves. Unfortunately, the inexpensive MCU does not have a built-in floating point operator, or the compiler does not support division operations, or is defective, such as supporting too small a range and too poor accuracy. If the MCU supporting division is replaced, the cost is increased, the development workload is increased due to the change of the MCU architecture, the time of product release in the market is delayed, and the business opportunity is missed.
Even if the MCU or the compiler does not directly support division operation, the division effect can be achieved. Assuming a is the dividend a, B is the divisor B, the actual division is the solution of the quotient C of a divided by B. Clearly, division has a precision factor, since for the inexhaustible operation, how many bits after the decimal point are reserved has a direct impact on the precision of quotient C. The division is realized on the computer, so that the operation cost is reduced as much as possible on the premise of meeting the precision requirement. These overheads include workload and time and memory space, which are several metrics of mutual constraints. When in use, the best scheme which can be accepted by all indexes is selected.
The basic principle of the technology is that the division between integers is realized on a computer, the subtraction count, and the quotient C is actually the integer division result of the integer division A by the integer division B, and the integer division result is not provided with decimal numbers. The algorithm is described as (assuming B is not 0, a, B are both positive integers):
a. firstly, assigning C=0;
b. comparing A and B, returning to C if A < B;
c. if A is greater than or equal to B, A is assigned with A-B, and C is added with 1; otherwise, returning to the step C;
d. jump to b execution
Thus quotient C is a count of A decreasing B until A is reduced to less than B.
The above is referred to as the "basic algorithm". It is straightforward but inefficient because the quotient C is a count value, and a larger value indicates a greater number of count cycles, with the computation time increasing linearly with the value of C. When the A, B value range is large, the calculation of the calculation formula consumes much time, is possibly too long, and makes division infeasible, so that the calculation formula is only suitable for division of small-range data types.
Another problem with the "basic algorithm" is that the accuracy of the operation is too poor, and since the decimal fraction cannot be calculated, it can only be rounded, and when the B value is large, the error of quotient C will be very large, since the remainder can be maximally as large as B-1. Resulting in an operation result of this kind that is of no practical value.
Disclosure of Invention
The technical problem to be solved by the present invention is to address at least one of the drawbacks of the related art mentioned in the background art above: the low-cost MCU is not internally provided with a floating point arithmetic unit, or the compiler does not support division operation, or has defects, if the MCU supporting division is replaced for the purpose, the cost is increased, the development workload is increased due to the change of the MCU architecture, the time of putting the product into the market is delayed, and the business opportunity is missed; the basic division algorithm is low in efficiency, and a method, a system, a storage medium and electronic equipment for realizing division operation on the MCU are provided.
The technical scheme adopted for solving the technical problems is as follows: a method for realizing division operation on MCU is constructed, the divisor A and the divisor B are integers, binary division operation is to be carried out, and the method comprises the following steps:
s0: judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, executing S1;
s1: assigning the divisor B to B1, comparing the B1 with the divisor A, and determining the optimal number i of the B1 through repeated comparison after the continuous left shift of the B1 and the number i of the shifts are correspondingly added with 1;
s2: and (3) subtracting the divisor A from the divisor B1, assigning the divisor A, adding the divisor I with the quotient C after shifting 1 left by the shifting number i according to the step length, assigning the divisor C to the quotient C, and repeating the steps until the divisor A is equal to 0 or the divisor A is smaller than the divisor B after shifting the B1 right and subtracting the shifting number i by 1, thereby obtaining the final quotient C.
Preferably, in the method for implementing division operation on MCU according to the present invention, step S1 includes:
s11: assigning the divisor B to B1, and setting the initial value of the quotient C and the number of shifting bits i to 0;
s12: judging whether the dividend A is greater than or equal to the B1 and whether the dividend A is less than 2 times the B1, if not, executing S13; if yes, executing S15;
s13: the B1 is shifted left by 1 bit, and the shifting number i is added with 1;
s14: judging whether the shift does not reach the highest bit of the B1, if so, returning to the step S12; if not, executing S15;
s15: judging whether the shifting number i is 0, if so, returning to the quotient C to be 1; if not, determining the number i of shifts of the B1 and the B1 after left shift.
Preferably, in the method for implementing division operation on MCU according to the present invention, step S2 includes:
s21: judging whether the dividend A is greater than or equal to the B1, if so, executing S22; if not, executing S23;
s22: assigning the divisor A minus the B1 to the divisor A, and adding 1 to the quotient C after shifting the shifting number i left and assigning the quotient C;
s23: right shifting the B1 by 1 bit, and subtracting the shift number i by 1;
s24: judging whether the dividend A is equal to 0 or whether the dividend A is smaller than the divisor B, if so, obtaining the final quotient C; if not, the process returns to S21.
Preferably, in the method for implementing division operation on MCU according to the present invention, the method further includes:
when a correction coefficient is required, shifting the divisor A left by N bits, and then carrying out division operation on the divisor A and the divisor B to obtain a quotient k;
and multiplying the value to be corrected by the quotient k, and then shifting the value to the right by N bits to obtain the correction value.
The invention also constructs a system for realizing division operation on MCU, the divisor A and the divisor B are integers, the binary division operation is to be carried out, the system comprises:
the judging module is used for judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, jumping to a determining module;
the determining module is used for assigning the divisor B to B1, comparing the B1 with the dividend A, and repeatedly comparing the continuous left shift of the B1 and the corresponding addition of 1 to the number of shift bits i to determine the optimal number of shift bits i of the B1;
the first operation module is configured to subtract the divisor a from the divisor B1 and assign the divisor a, add the divisor i to the quotient C and assign the divisor C to the quotient C after shifting the divisor a by 1 to the left by the shifting number i according to the step length, and then shift the divisor a by 0 or the divisor a is smaller than the divisor B after shifting the divisor B to the right by the B1 and subtracting the shifting number i, so as to obtain the final quotient C.
Preferably, in the system for implementing division operation on MCU according to the present invention, the determining module includes:
an initialization unit, configured to assign the divisor B to B1, and set the number of shifts i and the initial value of the quotient C to 0;
a first judging unit, configured to judge whether the dividend a is greater than or equal to the B1 and whether the dividend a is less than 2 times the B1, and if not, jump to a first computing unit and a second judging unit; if yes, jumping to a third judging unit;
the first operation unit is used for shifting the B1 left by 1 bit, and the shifting number i is added with 1;
the second judging unit is used for judging whether the shifting number i is smaller than the bit number of the dividend A or the divisor B, if yes, the first judging unit is jumped to; if not, jumping to a third judging unit;
the third judging unit is used for judging whether the shifting number i is 0, if so, returning to the quotient C to be 1; if not, determining the number i of shifts of the B1 and the B1 after left shift.
Preferably, in the system for implementing division operation on MCU according to the present invention, the first operation module includes:
a fourth judging unit, configured to judge whether the dividend a is greater than or equal to the B1, and if yes, execute a jump to a second operation unit; if not, executing a third operation unit and a fifth judgment unit;
the second operation unit is used for subtracting the B1 from the dividend A and assigning the dividend A, and adding the 1 left shift number i to the quotient C and assigning the quotient C;
a third operation unit for shifting the B1 to the right by 1 bit, and subtracting 1 from the number of shifting bits i;
a fifth judging unit, configured to judge whether the dividend a is equal to 0 or whether the dividend a is smaller than the divisor B, and if yes, obtain the final quotient C; if not, the method jumps to a fourth judging unit.
Preferably, in the system for implementing division operation on MCU according to the present invention, the system further includes:
the second operation module is used for shifting the divisor A left by N bits when the correction coefficient is required, and then carrying out division operation on the divisor A and the divisor B to obtain a quotient k;
and the third operation module is used for multiplying the value to be corrected by the quotient k and then shifting the value to the right by N bits to obtain the correction value.
The present invention also constructs a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a method of implementing a division operation on an MCU as described in any of the above.
The present invention also constructs an electronic device including:
one or more processors;
storage means for storing one or more programs that, when executed by the one or more processors, cause the one or more processors to implement a method of performing a division operation on an MCU as claimed in any preceding claim.
By implementing the invention, the following beneficial effects are achieved:
the division is realized on the MCU with limited resources by subtraction and shift operation, so that the problem that the division operation cannot be directly used because the cheap MCU is not internally provided with a floating point operator or a compiler cannot support the division well is solved, the cost of devices is saved, the MCU is not required to be replaced, the development requirement is met, and the product competitiveness is improved. Meanwhile, the operation efficiency of division is greatly improved, the error is limited to be small, and the practical application can be obtained.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a flow chart of a method of implementing division operations on an MCU in accordance with the present invention;
FIG. 2 is a detailed flowchart of steps S1 and S2 in the method of implementing a division operation on an MCU of the present invention;
FIG. 3 is a flow chart of a method for implementing division on an MCU and solving for correction coefficients in accordance with other embodiments of the present invention;
FIG. 4 is a block diagram of a system for implementing division operations on an MCU in accordance with the present invention;
FIG. 5 is a block diagram of a system for performing division on an MCU and calculating correction coefficients in accordance with other embodiments of the present invention.
Detailed Description
For a clearer understanding of technical features, objects and effects of the present invention, a detailed description of embodiments of the present invention will be made with reference to the accompanying drawings.
It should be noted that the flow diagrams depicted in the figures are merely exemplary and do not necessarily include all of the elements and operations/steps, nor are they necessarily performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
As shown in fig. 1, one embodiment of the present invention discloses a method for implementing division operation on an MCU, where a dividend a and a divisor B are integers, and binary division operation is performed, and the method includes the following steps:
s0: judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, executing S1;
s1: assigning the divisor B to B1, comparing B1 with the divisor A, and repeatedly comparing the continuous left shift of B1 and the corresponding addition of 1 to the number i of shift bits to determine the optimal number i of shift of B1, so as to find the optimal shift position of B1 before formally starting operation, thereby avoiding operation waste;
s2: the divisor A is subtracted from the divisor B1 after being compared, the divisor A is assigned, meanwhile, 1 is added with a quotient C after being shifted leftwards by a step length by a bit number i and assigned to the quotient C, and then B1 is shifted rightwards and the bit number i is subtracted by 1, and the operation is repeatedly carried out until the divisor A is equal to 0 or the divisor A is smaller than the divisor B, so that a final quotient C is obtained.
Specifically, in this embodiment, as shown in fig. 2, step S1 includes:
s11: assigning a divisor B to B1, and setting the initial values of the number of shifts i and the quotient C to 0 (i.e., b1=b, i=0, c=0);
s12: judging whether the dividend A is greater than or equal to B1 and whether the dividend A is less than 2 times B1 (namely, A is greater than or equal to B1 and A is less than 2B 1; if yes, executing S15;
s13: b1 shifts left by 1 bit and the number of shifts i is increased by 1 (i.e., B1 shifts left by 1 bit, i++);
s14: determining whether the shift has not reached the highest bit of B1, i.e., whether the shift number i is less than the bit number of the dividend a or the divisor B (e.g., i < 16 if the dividend a and the divisor B are 16-bit unsigned integers; if not, executing S15;
s15: determining whether the shift number i is 0 (i.e., i=0; if not, the number of shifts i of B1 and the left-shifted B1 are determined, and S21 described below is executed.
Completely, step S11 is preceded by S10: judging whether the dividend A is greater than or equal to the divisor B (i.e., A is greater than or equal to B; if yes, S11 is executed.
In this embodiment, as shown in fig. 2, step S2 includes:
s21: judging whether the dividend A is greater than or equal to B1 (namely, A is greater than or equal to B1; if not, executing S23;
s22: assign divisor a minus B1 to divisor a, and add 1 left shift number i to quotient C and assign quotient C (i.e., a=a-B1, c+=1 < < i); wherein, due to the nature of binary operation, the divisor a minus B1 must be a < B1 or a=0;
s23: shift B1 to the right by 1 bit and the shift number i minus 1 (i.e., b1=b1 > >1, i- -); wherein, in the binary operation, B1 is shifted by 1 bit to the right to be equivalent to B1/2, so that the divisor A is possibly larger than B1;
s24: determining whether the dividend a is equal to 0 or whether the dividend a is less than the divisor B (i.e., a=0 or a < B; if not, the process returns to S21.
In other embodiments, to solve the limitation that the calculation accuracy is too poor to take the decimal fraction, only the rounding is performed, as shown in fig. 3, the method further includes:
s3: when a correction coefficient or the like is required to be used as a numerical value of the multiplication coefficient, shifting the divisor A left by N bits, and then carrying out division operation with the divisor B to obtain a quotient k;
s4: and multiplying the value to be corrected by a quotient k, and then shifting the value to the right by N bits to obtain the correction value.
Specifically, for some division operations that solve correction coefficients (for example, values that are needed to be used as multiplication coefficients), it is quite difficult to solve a decimal number with several digits after a decimal point as in the decimal operation in ordinary times, as the correction coefficients in an embedded system. Even if this is possible, the difficulty of using this correction factor for the subsequent multiplication is great, since the multiplication with the decimal is not easy to do in embedded systems that do not support floating point operations.
For this case, the following procedure can be skillfully adopted:
when solving the correction coefficient, the divisor A is intentionally shifted left by N bits (in binary operation, this is equivalent to multiplying A by N times 2. When N is larger, A is amplified by a plurality of times than the original value), and then division operation is performed with the divisor B, thereby obtaining a quotient k as the correction coefficient, and the quotient k is still an integer but is N times the 2 of the quotient k obtained by the original value A/B. By this magnification, the phase change preserves the details of several bits after the decimal point.
When using the correction factor, the value to be corrected X is multiplied by the quotient k (correction factor) obtained in the above step, resulting in a result Y that is obviously also a power N times 2 of the result to be obtained. Therefore, by shifting Y by N right, a desired correction value can be obtained. This approach preserves the precision of several bits after the coefficient decimal point, so that the resulting error is within an acceptable range, with an effect sufficient to compete with computer systems with floating point computing capabilities.
For example, assume that the dividend a=43, the divisor b=11, the correction coefficient k=a/b=3, and the remainder 10 is the error. To-be-corrected value x=25, the ideal value of the correction value y=kx is 3.909×25= 97.737, but the actual value of the correction value Y is 3×25=75.
If a is amplified 10000 times, divided by B, the correction factor k=10000 x a/b=39090, the remainder being 10. The correction value y=kx= 977250, and then Y is reduced to 1/10000 of the original value, to obtain 97.
The reason for this is that division does not satisfy the exchange rate in the computer because the remainder is discarded. The alternative method is to enlarge the divisor, and then reduce the quotient in equal proportion after division operation, thereby reducing the influence of the discarded remainder.
As shown in fig. 4, an embodiment of the present invention discloses a system for implementing division operation on an MCU, where a dividend a and a divisor B are integers, and binary division operation is to be performed, including:
the judging module is used for judging whether the divisor A is larger than or equal to the divisor B, and if not, the quotient C is 0; if yes, jumping to a determining module;
the determining module is used for assigning the divisor B to B1, comparing the B1 with the divisor A, and repeatedly comparing the B1 after the continuous left shift of the B1 and the corresponding 1 added to the shift number i to determine the optimal shift number i of the B1, so as to find the optimal shift position of the B1 before the formal start of operation and avoid the operation waste;
the first operation module is used for subtracting and assigning the divisor A to the divisor A after comparing the divisor A with the divisor B1, adding the divisor A with the quotient C after shifting the divisor I to the left by the step length and assigning the divisor C to the quotient C, and repeating the steps until the divisor A is equal to 0 or the divisor A is smaller than the divisor B after shifting the divisor B to the right by the B1 and subtracting the divisor I from the divisor C to obtain the final quotient C.
Specifically, in this embodiment, the determining module includes:
an initialization unit for assigning a divisor B to B1 and setting the initial values of the number of shifts i and the quotient C to 0;
the first judging unit is used for judging whether the dividend A is larger than or equal to B1 and whether the dividend A is smaller than 2 times B1, if not, the first judging unit is jumped to the first operation unit and the second judging unit; if yes, jumping to a third judging unit;
a first operation unit for shifting B1 left by 1 bit, and adding 1 to the shift number i;
the second judging unit is used for judging whether the shift is less than the highest bit of B1, namely whether the shift number i is smaller than the bit number of the dividend A or the divisor B, if yes, the first judging unit is jumped to; if not, jumping to a third judging unit;
the third judging unit is used for judging whether the shifting number i is 0, if so, the return quotient C is 1; if not, the number of shifts i of B1 and the left-shifted B1 are determined, and adjusted to a fourth determination unit described below.
The determining module is further provided with a sixth judging unit, which is used for judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, jumping to the initialization unit.
In this embodiment, the first operation module includes:
a fourth judging unit, configured to judge whether the dividend a is greater than or equal to B1, if yes, execute a jump to the second operation unit; if not, executing a third operation unit and a fifth judgment unit;
the second operation unit is used for subtracting B1 from the dividend A and assigning the dividend A, and adding 1 left shift bit number i to the quotient C and assigning the quotient C; wherein, due to the nature of binary operation, the divisor a minus B1 must be a < B1 or a=0;
a third operation unit for shifting B1 by 1 bit to the right and subtracting 1 from the shift number i; wherein, in the binary operation, B1 is shifted by 1 bit to the right to be equivalent to B1/2, so that the divisor A is possibly larger than B1;
a fifth judging unit, configured to judge whether the dividend a is equal to 0 or whether the dividend a is smaller than the divisor B, if yes, obtain a final quotient C; if not, the method jumps to a fourth judging unit.
In other embodiments, to solve the limitation that the calculation accuracy is too poor to take the decimal fraction, only the rounding is performed, as shown in fig. 5, the system further includes:
the second operation module is used for shifting the divisor A left by N bits when the correction coefficient and the like are required to be used as the numerical value of the multiplication coefficient, and then carrying out division operation on the divisor A and the divisor B to obtain a quotient k;
and the third operation module is used for multiplying the value to be corrected by the quotient k and then shifting the value to the right by N bits to obtain the correction value.
Specifically, for some division operations that solve correction coefficients (for example, values that are needed to be used as multiplication coefficients), it is quite difficult to solve a decimal number with several digits after a decimal point as in the decimal operation in ordinary times, as the correction coefficients in an embedded system. Even if this is possible, the difficulty of using this correction factor for the subsequent multiplication is great, since the multiplication with the decimal is not easy to do in embedded systems that do not support floating point operations.
For this case, the following procedure can be skillfully adopted:
when solving the correction coefficient, the divisor A is intentionally shifted left by N bits (in binary operation, this is equivalent to multiplying A by N times 2. When N is larger, A is amplified by a plurality of times than the original value), and then division operation is performed with the divisor B, thereby obtaining a quotient k as the correction coefficient, and the quotient k is still an integer but is N times the 2 of the quotient k obtained by the original value A/B. By this magnification, the phase change preserves the details of several bits after the decimal point.
When using the correction factor, the value to be corrected X is multiplied by the quotient k (correction factor) obtained in the above step, resulting in a result Y that is obviously also a power N times 2 of the result to be obtained. Therefore, by shifting Y by N right, a desired correction value can be obtained. This approach preserves the precision of several bits after the coefficient decimal point, so that the resulting error is within an acceptable range, with an effect sufficient to compete with computer systems with floating point computing capabilities.
For example, assume that the dividend a=43, the divisor b=11, the correction coefficient k=a/b=3, and the remainder 10 is the error. To-be-corrected value x=25, the ideal value of the correction value y=kx is 3.909×25= 97.737, but the actual value of the correction value Y is 3×25=75.
If a is amplified 10000 times, divided by B, the correction factor k=10000 x a/b=39090, the remainder being 10. The correction value y=kx= 977250, and then Y is reduced to 1/10000 of the original value, to obtain 97.
The reason for this is that division does not satisfy the exchange rate in the computer because the remainder is discarded. The alternative method is to enlarge the divisor, and then reduce the quotient in equal proportion after division operation, thereby reducing the influence of the discarded remainder.
An embodiment of the invention discloses a computer readable storage medium having stored thereon a computer program which when executed by a processor implements a method of performing a division operation on an MCU as described in the above embodiments.
One embodiment of the invention discloses an electronic device comprising:
one or more processors;
and a storage device for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement a method for performing a division operation on an MCU as described in the above embodiments.
It should be noted that, no matter what MCU is, 8-bit, 16-bit, 32-bit or even 64-bit MCU, no matter whether the MCU is a self-contained floating point operator or not, no matter whether the compiler perfectly supports multiplication and division or not, all are protected. The data types participating in the operation are not limited to the 16-bit unsigned integer types in the description of the algorithm, and include custom data types, such as signed integers, etc., which are all protected. In addition, for the operation of the coefficient, the N times is intentionally amplified, and the operation is reduced to 1/N of the result after the actual operation, so that the correct operation result is obtained, and no matter how large the N is selected, the amplification/reduction is carried out by adopting shift or multiplication division, and the protection is provided.
By implementing the invention, the following beneficial effects are achieved:
the division is realized on the MCU with limited resources by subtraction and shift operation, so that the problem that the division operation cannot be directly used because the cheap MCU is not internally provided with a floating point operator or a compiler cannot support the division well is solved, the cost of devices is saved, the MCU is not required to be replaced, the development requirement is met, and the product competitiveness is improved. Meanwhile, the operation efficiency of division is greatly improved, the error is limited to be small, and the practical application can be obtained.
It is to be understood that the above examples represent only some embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention; it should be noted that, for a person skilled in the art, the above embodiments or technical features may be freely combined, and several variations and modifications may be made, without departing from the spirit of the invention, which fall within the scope of the invention, i.e. the embodiments described in "some embodiments" may be freely combined with any of the above and below embodiments; therefore, all changes and modifications that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims (10)
1. A method for implementing division operation on an MCU, wherein a dividend a and a divisor B are integers, and binary division operation is performed, comprising the steps of:
s0: judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, executing S1;
s1: assigning the divisor B to B1, comparing the B1 with the divisor A, and determining the optimal number i of the B1 through repeated comparison after the continuous left shift of the B1 and the number i of the shifts are correspondingly added with 1;
s2: and (3) subtracting the divisor A from the divisor B1, assigning the divisor A, adding the divisor I with the quotient C after shifting 1 left by the shifting number i according to the step length, assigning the divisor C to the quotient C, and repeating the steps until the divisor A is equal to 0 or the divisor A is smaller than the divisor B after shifting the B1 right and subtracting the shifting number i by 1, thereby obtaining the final quotient C.
2. The method for implementing division operation on MCU according to claim 1, wherein step S1 comprises:
s11: assigning the divisor B to B1, and setting the initial value of the quotient C and the number of shifting bits i to 0;
s12: judging whether the dividend A is greater than or equal to the B1 and whether the dividend A is less than 2 times the B1, if not, executing S13; if yes, executing S15;
s13: the B1 is shifted left by 1 bit, and the shifting number i is added with 1;
s14: judging whether the shift does not reach the highest bit of the B1, if so, returning to the step S12; if not, executing S15;
s15: judging whether the shifting number i is 0, if so, returning to the quotient C to be 1; if not, determining the number i of shifts of the B1 and the B1 after left shift.
3. The method for implementing division operation on MCU according to claim 1, wherein step S2 comprises:
s21: judging whether the dividend A is greater than or equal to the B1, if so, executing S22; if not, executing S23;
s22: assigning the divisor A minus the B1 to the divisor A, and adding 1 to the quotient C after shifting the shifting number i left and assigning the quotient C;
s23: right shifting the B1 by 1 bit, and subtracting the shift number i by 1;
s24: judging whether the dividend A is equal to 0 or whether the dividend A is smaller than the divisor B, if so, obtaining the final quotient C; if not, the process returns to S21.
4. The method of implementing a division operation on an MCU of claim 1, further comprising:
when a correction coefficient is required, shifting the divisor A left by N bits, and then carrying out division operation on the divisor A and the divisor B to obtain a quotient k;
and multiplying the value to be corrected by the quotient k, and then shifting the value to the right by N bits to obtain the correction value.
5. A system for implementing division operations on an MCU, wherein a dividend a and a divisor B are integers, and wherein binary division operations are to be performed, comprising:
the judging module is used for judging whether the dividend A is larger than or equal to the divisor B, if not, the quotient C is 0; if yes, jumping to a determining module;
the determining module is used for assigning the divisor B to B1, comparing the B1 with the dividend A, and repeatedly comparing the continuous left shift of the B1 and the corresponding addition of 1 to the number of shift bits i to determine the optimal number of shift bits i of the B1;
the first operation module is configured to subtract the divisor a from the divisor B1 and assign the divisor a, add the divisor i to the quotient C and assign the divisor C to the quotient C after shifting the divisor a by 1 to the left by the shifting number i according to the step length, and then shift the divisor a by 0 or the divisor a is smaller than the divisor B after shifting the divisor B to the right by the B1 and subtracting the shifting number i, so as to obtain the final quotient C.
6. The system for performing division operations on an MCU of claim 5, wherein the determination module comprises:
an initialization unit, configured to assign the divisor B to B1, and set the number of shifts i and the initial value of the quotient C to 0;
a first judging unit, configured to judge whether the dividend a is greater than or equal to the B1 and whether the dividend a is less than 2 times the B1, and if not, jump to a first computing unit and a second judging unit; if yes, jumping to a third judging unit;
the first operation unit is used for shifting the B1 left by 1 bit, and the shifting number i is added with 1;
the second judging unit is used for judging whether the shift does not reach the highest bit of the B1, if so, the first judging unit is jumped to; if not, jumping to a third judging unit;
the third judging unit is used for judging whether the shifting number i is 0, if so, returning to the quotient C to be 1; if not, determining the number i of shifts of the B1 and the B1 after left shift.
7. The system for performing a division operation on an MCU of claim 5, wherein the first operation module comprises:
a fourth judging unit, configured to judge whether the dividend a is greater than or equal to the B1, and if yes, execute a jump to a second operation unit; if not, executing a third operation unit and a fifth judgment unit;
the second operation unit is used for subtracting the B1 from the dividend A and assigning the dividend A, and adding the 1 left shift number i to the quotient C and assigning the quotient C;
a third operation unit for shifting the B1 to the right by 1 bit, and subtracting 1 from the number of shifting bits i;
a fifth judging unit, configured to judge whether the dividend a is equal to 0 or whether the dividend a is smaller than the divisor B, and if yes, obtain the final quotient C; if not, the method jumps to a fourth judging unit.
8. The system for performing division operations on an MCU of claim 5, further comprising:
the second operation module is used for shifting the divisor A left by N bits when the correction coefficient is required, and then carrying out division operation on the divisor A and the divisor B to obtain a quotient k;
and the third operation module is used for multiplying the value to be corrected by the quotient k and then shifting the value to the right by N bits to obtain the correction value.
9. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements a method of implementing a division operation on an MCU according to any of claims 1-4.
10. An electronic device, comprising:
one or more processors;
storage means for storing one or more programs which when executed by the one or more processors cause the one or more processors to implement the method of performing a division operation on an MCU as claimed in any of claims 1 to 4.
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| CN117908833A (en) * | 2024-03-19 | 2024-04-19 | 广州三晶电气股份有限公司 | Acceleration method and device of MCU high-order integer divider |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117908833A (en) * | 2024-03-19 | 2024-04-19 | 广州三晶电气股份有限公司 | Acceleration method and device of MCU high-order integer divider |
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