CN116224028A - Integrated circuit package test system and method - Google Patents
Integrated circuit package test system and method Download PDFInfo
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- CN116224028A CN116224028A CN202310200022.1A CN202310200022A CN116224028A CN 116224028 A CN116224028 A CN 116224028A CN 202310200022 A CN202310200022 A CN 202310200022A CN 116224028 A CN116224028 A CN 116224028A
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- Prior art keywords
- test
- signal
- tester
- testing
- motherboard
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a system and a method for testing integrated circuit package, comprising a motherboard, a power supply device, a testing device and a management and control device, wherein the motherboard is internally provided with the testing device; providing operation power through the power supply device to make the motherboard present operation state; establishing a communication pipeline between the motherboard and the management and control device; transmitting a test signal to the motherboard by using a control device, and testing the chip by using a test device; and according to the test result of the chip, checking whether the chip operates normally. The invention can test without assembling the motherboard in the electronic equipment, saves the cost of a hardware testing instrument in the production process of the product, saves manual operation, can effectively intercept the outflow of defective products, improves the quality of the product, realizes the instant control of the production, effectively shortens the total testing time of all tested devices, improves the production efficiency and improves the testing efficiency.
Description
Technical Field
The present invention relates to the field of integrated circuit package testing technology, and in particular, to a system and a method for testing an integrated circuit package.
Background
Since the quality and condition of the chip used in the chip package (Multi-ChipPackage, MCP) are different, a complete test method is required to determine whether the active circuit (IC) is good or bad. It is known that the manufacturer of a typical active circuit (IC) must use special ball grid array (BallGridArray, BGA) tools and applications to determine whether the test is good or bad when testing the active circuit (IC). Therefore, even if the active circuit (IC) is judged to be good before the attachment, it is still difficult to judge whether the active circuit (IC) is operable after the attachment to the Motherboard (MB), and at this time, it is necessary to complete the assembly of the Motherboard (MB) and the machine, and then to perform a functional test to judge whether the active circuit (IC) attached to the Motherboard (MB) is usable.
When the Motherboard (MB) and the machine are assembled into a complete machine, if the active circuit (IC) on the Motherboard (MB) is found to be inoperable (or defective), a great maintenance cost is required for maintenance, so that even if the chip is known to be faulty, the defective chip must be disassembled and reassembled with the Motherboard (MB) because the defective chip is already packaged into the complete machine, thereby causing adverse effects such as production efficiency loss, increased inventory defective products, increased repair cost, and damaged performance. Therefore, we propose a system and method for testing an integrated circuit package.
Disclosure of Invention
The invention mainly aims to provide an integrated circuit package testing system and method, which can effectively solve the problems in the background technology.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
an integrated circuit package testing system, comprising: motherboard, power supply device, testing device and control device,
the motherboard is used for being provided with a chip, and the chip comprises a plurality of tested devices;
the power supply device is used for providing operation power to enable the mainboard to be in an operation state;
the control device establishes a communication pipeline with the mainboard through the communication unit to send a test signal to the mainboard for testing the chip and checking whether the chip operates normally according to the test result of the chip;
wherein, the motherboard is built-in with testing arrangement, testing arrangement is equipped with communication port.
As a further improvement of the above scheme, a plurality of the main boards are connected into a yoke plate, so that the yoke plate is put into a tool for testing the chip.
As a further improvement of the above solution, the test device includes a test module, a first tester and a second tester, a signal transmission controller, and a test controller;
the test module is used for electrically coupling at least two devices under test in the devices under test, and is used for controlling the at least two devices under test to transmit and receive signals;
a first tester for performing a first signal test including a first signal transmission test and a first signal reception test;
the second tester is used for carrying out a second signal test, and the second signal test comprises a second signal sending test and a second signal receiving test;
the signal transmission controller is used for controlling the test module, and the signal transmission controller is respectively connected with the signal transmission paths between the first tester and the second tester;
the test controller is used for controlling the test module, the first tester and the second tester to perform the first signal test and the second signal test on the at least two different tested devices in parallel, and recording the test result of any tested device in the configuration data contained in the loading module when the first signal test and the second signal test are completed by any tested device of the tested devices.
As a further improvement of the above solution, the first tester is a wireless fidelity tester, and the second tester is a bluetooth tester.
As a further improvement of the above, the first signal test includes a first signal transmission test and a first signal reception test, the second signal test includes a second signal transmission test and a second signal reception test, and the first tester sequentially executes the first signal transmission test and the first signal reception test, and the second tester sequentially executes the second signal transmission test and the second signal reception test.
As a further improvement of the above-described aspect, the first signal reception test and the second signal reception test are executed in parallel, and the first signal transmission test and the second signal transmission test are executed in parallel.
As a further improvement of the above scheme, the connection mode of the communication port and the communication unit is bluetooth connection.
An integrated circuit package testing method for an integrated circuit package testing system, comprising the steps of:
s1: mounting the chip on the motherboard;
s2: providing operation power through the power supply device to make the motherboard present operation state;
s3: establishing a communication pipeline between the motherboard and the management and control device;
s4: transmitting a test signal to the motherboard by using a control device, and testing the chip by using a test device;
s5: and according to the test result of the chip, checking whether the chip operates normally.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention can test without assembling the motherboard in the electronic equipment, thereby saving the cost of a hardware testing instrument in the production process of the product, saving manual operation, effectively intercepting the outflow of defective products, improving the quality of the product, realizing the immediate control of the production, saving the testing time of the product leaving the factory and improving the production efficiency.
2. According to the invention, more than two tested devices are tested in parallel in the same time, so that the total test time of all tested devices can be effectively shortened, and the test efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an integrated circuit package testing method according to the present invention.
Detailed Description
The invention is further described in connection with the following detailed description, in order to make the technical means, the creation characteristics, the achievement of the purpose and the effect of the invention easy to understand.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", "front", "rear", "both ends", "one end", "the other end", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "provided," "connected," and the like are to be construed broadly, and may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The technical scheme of the invention is further described below with reference to the accompanying drawings.
Examples
An integrated circuit package testing system, comprising: motherboard, power supply device, testing device and control device,
the motherboard is used for installing a chip, and the chip comprises a plurality of tested devices;
the power supply device is used for providing operation power to enable the motherboard to be in an operation state;
the control device establishes a communication pipeline with the mainboard through the communication unit to send a test signal to the mainboard for testing the chip and checking whether the chip operates normally according to the test result of the chip;
wherein, the motherboard is internally provided with a testing device which is provided with a communication port.
Preferably, a plurality of main boards are connected into a yoke plate, so that the yoke plate is put into a tool for testing the chip.
Preferably, the testing device comprises a testing module, a first tester, a second tester, a signal transmission controller and a testing controller;
the test module is used for electrically coupling at least two tested devices in the tested devices, and the test module is used for controlling the at least two tested devices to transmit and receive signals;
the first tester is used for performing a first signal test, wherein the first signal test comprises a first signal transmission test and a first signal reception test;
the second tester is used for carrying out a second signal test, and the second signal test comprises a second signal transmission test and a second signal reception test;
the signal transmission controller is used for controlling the test module, and the signal transmission controller is respectively connected with the signal transmission paths between the first tester and the second tester;
and the test controller is used for controlling the test module, the first tester and the second tester to perform the first signal test and the second signal test on the at least two different tested devices in parallel, and recording the test result of any tested device in the configuration data contained in the loading module when any tested device of the tested devices completes the first signal test and the second signal test.
Preferably, the first tester is a wireless fidelity tester, and the second tester is a bluetooth tester.
Preferably, the first signal test includes a first signal transmission test and a first signal reception test, the second signal test includes a second signal transmission test and a second signal reception test, the first tester sequentially executes the first signal transmission test and the first signal reception test, and the second tester sequentially executes the second signal transmission test and the second signal reception test.
Preferably, the first signal reception test and the second signal reception test are performed in parallel, and the first signal transmission test and the second signal transmission test are performed in parallel.
Preferably, the connection mode of the communication port and the communication unit is Bluetooth connection.
As shown in fig. 1, an integrated circuit package testing method is used for an integrated circuit package testing system, and includes the following steps:
s1: mounting the chip on the motherboard;
s2: providing operation power through the power supply device to make the motherboard present operation state;
s3: establishing a communication pipeline between the motherboard and the management and control device;
s4: transmitting a test signal to the motherboard by using a control device, and testing the chip by using a test device;
s5: and according to the test result of the chip, checking whether the chip operates normally.
In the specific use process, the embodiment can test without assembling the motherboard in the electronic equipment, so that the cost of a hardware testing instrument in the production process of the product is saved, meanwhile, the manual operation is also saved, the outflow of defective products can be effectively intercepted, the product quality is improved, the immediate management and control of the production are realized, the testing time of the product delivery is saved, and the production efficiency is improved; in the same time, more than two tested devices are tested in parallel, so that the total test time of all tested devices can be effectively shortened, and the test efficiency is improved.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. An integrated circuit package testing system, characterized by: comprising the following steps: motherboard, power supply device, testing device and control device,
the motherboard is used for being provided with a chip, and the chip comprises a plurality of tested devices;
the power supply device is used for providing operation power to enable the mainboard to be in an operation state;
the control device establishes a communication pipeline with the mainboard through the communication unit to send a test signal to the mainboard for testing the chip and checking whether the chip operates normally according to the test result of the chip;
wherein, the motherboard is built-in with testing arrangement, testing arrangement is equipped with communication port.
2. An integrated circuit package testing system according to claim 1, wherein: the plurality of main boards are connected into a connecting board, so that the connecting board is put into a tool for testing the chip.
3. An integrated circuit package testing system according to claim 1, wherein: the testing device comprises a testing module, a first tester, a second tester, a signal transmission controller and a testing controller;
the test module is used for electrically coupling at least two devices under test in the devices under test, and is used for controlling the at least two devices under test to transmit and receive signals;
a first tester for performing a first signal test including a first signal transmission test and a first signal reception test;
the second tester is used for carrying out a second signal test, and the second signal test comprises a second signal sending test and a second signal receiving test;
the signal transmission controller is used for controlling the test module, and the signal transmission controller is respectively connected with the signal transmission paths between the first tester and the second tester;
the test controller is used for controlling the test module, the first tester and the second tester to perform the first signal test and the second signal test on the at least two different tested devices in parallel, and recording the test result of any tested device in the configuration data contained in the loading module when the first signal test and the second signal test are completed by any tested device of the tested devices.
4. An integrated circuit package testing system according to claim 3, wherein: the first tester is a wireless fidelity tester, and the second tester is a Bluetooth tester.
5. An integrated circuit package testing system according to claim 3, wherein: the first signal test comprises a first signal transmission test and a first signal reception test, the second signal test comprises a second signal transmission test and a second signal reception test, the first tester sequentially executes the first signal transmission test and the first signal reception test, and the second tester sequentially executes the second signal transmission test and the second signal reception test.
6. An integrated circuit package testing system according to claim 3, wherein: the first signal reception test and the second signal reception test are performed in parallel, and the first signal transmission test and the second signal transmission test are performed in parallel.
7. An integrated circuit package testing system according to claim 1, wherein: the communication port is connected with the communication unit in a Bluetooth mode.
8. An integrated circuit package testing method for an integrated circuit package testing system as recited in any of claims 1-7, wherein: the method comprises the following steps:
s1: mounting the chip on the motherboard;
s2: providing operation power through the power supply device to make the motherboard present operation state;
s3: establishing a communication pipeline between the motherboard and the management and control device;
s4: transmitting a test signal to the motherboard by using a control device, and testing the chip by using a test device;
s5: and according to the test result of the chip, checking whether the chip operates normally.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310200022.1A CN116224028A (en) | 2023-03-03 | 2023-03-03 | Integrated circuit package test system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310200022.1A CN116224028A (en) | 2023-03-03 | 2023-03-03 | Integrated circuit package test system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116224028A true CN116224028A (en) | 2023-06-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310200022.1A Pending CN116224028A (en) | 2023-03-03 | 2023-03-03 | Integrated circuit package test system and method |
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| Country | Link |
|---|---|
| CN (1) | CN116224028A (en) |
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- 2023-03-03 CN CN202310200022.1A patent/CN116224028A/en active Pending
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