CN116223515B - Conductive pattern defect detection method for circuit board test process - Google Patents
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- 230000007547 defect Effects 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000012360 testing method Methods 0.000 title claims abstract description 25
- 238000001514 detection method Methods 0.000 title claims abstract description 13
- 238000010586 diagram Methods 0.000 claims abstract description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 28
- 238000012937 correction Methods 0.000 claims abstract description 23
- 230000000903 blocking effect Effects 0.000 claims abstract description 10
- 230000002159 abnormal effect Effects 0.000 claims description 49
- 238000009826 distribution Methods 0.000 claims description 29
- 230000008021 deposition Effects 0.000 claims description 22
- 238000009713 electroplating Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 238000003466 welding Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 abstract description 7
- 238000007747 plating Methods 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
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- G01N21/892—Investigating the presence of flaws or contamination in moving material, e.g. running paper or textiles characterised by the flaw, defect or object feature examined
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Abstract
The invention provides a conductive pattern defect detection method for a circuit board test process, which relates to the technical field of circuit board test, wherein a circuit board comprises two parts: the invention utilizes a standard circuit board gray level diagram to carry out gray level correction on a circuit board diagram to be tested, improves detection precision, finds a copper plating area to be tested in the corrected gray level diagram to be tested, carries out blocking treatment on the copper plating area to be tested, finds the range of a defect, carries out blocking, and determines the position of the defect, thereby realizing a full-automatic conductive pattern defect identification method based on image processing.
Description
Technical Field
The invention relates to the technical field of circuit board testing, in particular to a conductive pattern defect detection method for a circuit board testing process.
Background
After the production of the circuit board is finished, a test experiment is required to be carried out, whether the circuit board meets the national standard is evaluated, and the unqualified circuit board is screened out. In the test, the defect of the conductive pattern needs to be detected, and the defect of the conductive pattern comprises: rough edges, gaps, pinholes and scratches of exposed substrates. The signal wires in the circuit board are very small and fine, so that it is very difficult to find all conductive pattern defects by means of human eyes.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a conductive pattern defect detection method for a circuit board test process, which solves the problem of the lack of the conventional conductive pattern defect detection method.
In order to achieve the aim of the invention, the invention adopts the following technical scheme: a conductive pattern defect detection method for a circuit board test process includes the following steps:
s1, collecting a circuit board diagram to be tested in a circuit board testing process;
s2, carrying out gray level correction on the circuit board diagram to be tested according to the standard circuit board gray level diagram to obtain a corrected gray level diagram to be tested;
s3, removing a solder mask coverage area in the correction gray scale image to be detected to obtain a copper deposition electroplating area to be detected;
s4, performing block treatment on the copper deposition electroplating area to be tested to obtain a plurality of blocks to be tested;
s5, finding out abnormal blocks to be detected according to gray features on the blocks to be detected;
s6, the abnormal blocks to be detected are segmented again, and the defect positions of the conductive patterns are found.
Further, the step S2 includes the following sub-steps:
s21, carrying out gray scale treatment on the standard circuit board graph to obtain a standard circuit board gray scale graph;
s22, respectively taking pixel points of a solder mask coverage area and a copper deposition electroplating area in a standard circuit board gray scale map;
s23, calculating an average gray value of pixel points of a solder mask coverage area in a gray map of a standard circuit board to obtain a first standard gray value;
s24, calculating an average gray value of pixel points of a copper deposition electroplating area in the gray map of the standard circuit board to obtain a second standard gray value;
s25, carrying out graying treatment on the circuit board diagram to be tested to obtain a gray diagram to be tested;
s26, finding a plurality of pixel points of which the gray value of the gray value in the gray image to be detected and the gray value of the first standard gray value are smaller than a gray threshold value, and obtaining a first reference pixel point;
s27, finding a plurality of pixel points of which the gray value of the gray value in the gray image to be detected and the gray value of the second standard gray value are smaller than the gray threshold value, and obtaining a second reference pixel point;
s28, respectively calculating the gray average value of a plurality of first reference pixel points and the gray average value of a plurality of second reference pixel points to obtain a first reference gray value and a second reference gray value;
and S29, correcting the gray value in the gray image to be detected according to the first standard gray value, the second standard gray value, the first reference gray value and the second reference gray value to obtain a corrected gray image to be detected.
Further, the calculation formula of the gray distance value in S26 is as follows:
wherein,,
for the gray level diagram to be measured +.>
Gray value of individual pixel dot +.>
And the first standard gray value->
Is a gray scale distance value of (a).
Further, the calculation formula of the gray distance value in S27 is as follows:
wherein,,
for the gray level diagram to be measured +.>
Gray value of individual pixel dot +.>
And a second standard gray value->
Is a gray scale distance value of (a).
Further, the correction formula in S29 is:
wherein,,
to be measured correct gray level map +.>
Gray value of each pixel point，/>
For the first standard gray value +.>
For the second standard gray value +.>
For the first reference gray value +.>
For the second reference gray value +.>
For the gray level diagram to be measured +.>
Gray values of individual pixels.
The beneficial effects of the above further scheme are: and calculating the gray scale correction coefficient according to the gray scale value conditions of the solder resist coverage area and the copper deposition electroplating area in the gray scale image of the standard circuit board, so as to correct the gray scale image to be detected.
Further, the step S3 includes the following sub-steps:
s31, taking any pixel point in the correction gray scale image to be detected as a contrast pixel point;
s32, calculating a gray scale distance value of the pixel points of the welding resistance coverage area in the gray scale graph of the contrast pixel points and the standard circuit board;
s33, when the gray distance value corresponding to the contrast pixel point is smaller than the gray threshold value, the contrast pixel point is the pixel point of the welding resistance coverage area in the gray map to be corrected;
s34, finding out pixel points of the solder mask coverage areas in all the correction gray maps to be detected through the steps S31-S33, and removing the pixel points of the solder mask coverage areas in the correction gray maps to be detected to obtain the copper deposition electroplating areas to be detected.
Further, the step S5 includes the following sub-steps:
s51, calculating gray value distribution characteristics of each pixel point of the to-be-detected block to obtain the to-be-detected distribution characteristics;
s52, calculating the similarity between the distribution characteristics to be measured and the standard characteristics;
s53, judging whether the similarity is lower than a similarity threshold, if so, judging that the block to be detected is an abnormal block to be detected, and if not, judging that the block to be detected has no conductive pattern defect.
Further, the formula for obtaining the distribution feature to be measured in S51 is:
wherein,,
for the distribution feature to be measured->
For the block to be measured->
Gray value of each pixel, +.>
For the number of pixels on the block to be measured, < >>
For the maximum gray value of the pixel point on the block to be measured, < >>
The minimum gray value of the pixel points on the block to be detected is obtained.
The beneficial effects of the above further scheme are: according to the invention, the distribution characteristics of the to-be-detected blocks are obtained through the distribution condition of the gray values on the to-be-detected blocks and the sizes of the gray values, so that the characteristics of the to-be-detected blocks are expressed, and the similarity between two images is obtained through the similarity between the characteristics.
Further, the formula for calculating the similarity in S52 is:
wherein,,
for the similarity of the distribution feature to be measured and the standard feature, < + >>
For the distribution feature to be measured->
As a standard feature of the device,
is a similarity coefficient.
Further, the step S6 includes the following sub-steps:
s61, performing blocking again on the abnormal to-be-detected sub-blocks to obtain a plurality of abnormal to-be-detected sub-blocks;
s62, calculating an abnormal value of each abnormal sub-block to be detected:
wherein,,
for the abnormal value of the abnormal sub-block to be measured, < ->
For the number of pixels on the abnormal sub-block to be measured, < +.>
For the number of pixels on the standard sub-block, < +.>
For the abnormal test sub-block +.>
The distance between each pixel point and the central pixel point on the abnormal sub-block to be detected is +.>
For standard sub-block +.>
The distance between each pixel point and the central pixel point on the standard sub-block is the absolute value;
and S63, finding out abnormal sub-blocks to be detected, the abnormal value of which is greater than the abnormal threshold value, and obtaining the defect positions of the conductive patterns.
The beneficial effects of the above further scheme are: the number of the pixel points represents the size of a copper deposition electroplating area on the abnormal sub-block to be detected, the distance from the center pixel point represents the position distribution condition of the pixel points, the position distribution of the pixel points is similar, and the two images are similar and the abnormal value is smaller.
The technical scheme of the embodiment of the invention has at least the following advantages and beneficial effects: the circuit board comprises two parts: the invention utilizes a standard circuit board gray level diagram to carry out gray level correction on a circuit board diagram to be tested, improves detection precision, finds a copper plating area to be tested in the corrected gray level diagram to be tested, carries out blocking treatment on the copper plating area to be tested, finds the range of a defect, carries out blocking, and determines the position of the defect, thereby realizing a full-automatic conductive pattern defect identification method based on image processing.
Drawings
Fig. 1 is a flowchart of a conductive pattern defect detection method for a circuit board test process.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
As shown in fig. 1, a conductive pattern defect detection method for a circuit board test process includes the steps of:
s1, collecting a circuit board diagram to be tested in a circuit board testing process;
s2, carrying out gray level correction on the circuit board diagram to be tested according to the standard circuit board gray level diagram to obtain a corrected gray level diagram to be tested;
and S2, shooting a good circuit board image without conductive pattern defects in advance, and obtaining a standard circuit board gray level chart after performing gray level processing on the image.
The step S2 comprises the following sub-steps:
s21, carrying out gray scale treatment on the standard circuit board graph to obtain a standard circuit board gray scale graph;
s22, respectively taking pixel points of a solder mask coverage area and a copper deposition electroplating area in a standard circuit board gray scale map;
s23, calculating an average gray value of pixel points of a solder mask coverage area in a gray map of a standard circuit board to obtain a first standard gray value;
s24, calculating an average gray value of pixel points of a copper deposition electroplating area in the gray map of the standard circuit board to obtain a second standard gray value;
s25, carrying out graying treatment on the circuit board diagram to be tested to obtain a gray diagram to be tested;
s26, finding a plurality of pixel points of which the gray value of the gray value in the gray image to be detected and the gray value of the first standard gray value are smaller than a gray threshold value, and obtaining a first reference pixel point;
the calculation formula of the gray distance value in S26 is as follows:
wherein,,
for the gray level diagram to be measured +.>
Gray value of individual pixel dot +.>
And the first standard gray value->
Is a gray scale distance value of (a).
S27, finding a plurality of pixel points of which the gray value of the gray value in the gray image to be detected and the gray value of the second standard gray value are smaller than the gray threshold value, and obtaining a second reference pixel point;
in this embodiment, the gradation threshold value may be empirically set.
The calculation formula of the gray distance value in S27 is as follows:
wherein,,
for the gray level diagram to be measured +.>
Gray value of individual pixel dot +.>
And a second standard gray value->
Is a gray scale distance value of (a).
S28, respectively calculating the gray average value of a plurality of first reference pixel points and the gray average value of a plurality of second reference pixel points to obtain a first reference gray value and a second reference gray value;
and S29, correcting the gray value in the gray image to be detected according to the first standard gray value, the second standard gray value, the first reference gray value and the second reference gray value to obtain a corrected gray image to be detected.
The correction formula in S29 is:
wherein,,
to be measured correct gray level map +.>
Gray value of each pixel, +.>
For the first standard gray value +.>
For the second standard gray value +.>
For the first reference gray value +.>
For the second reference gray value +.>
For the gray level diagram to be measured +.>
Gray values of individual pixels.
And calculating the gray scale correction coefficient according to the gray scale value conditions of the solder resist coverage area and the copper deposition electroplating area in the gray scale image of the standard circuit board, so as to correct the gray scale image to be detected.
S3, removing a solder mask coverage area in the correction gray scale image to be detected to obtain a copper deposition electroplating area to be detected;
the step S3 comprises the following substeps:
s31, taking any pixel point in the correction gray scale image to be detected as a contrast pixel point;
s32, calculating a gray scale distance value of the pixel points of the welding resistance coverage area in the gray scale graph of the contrast pixel points and the standard circuit board;
s33, when the gray distance value corresponding to the contrast pixel point is smaller than the gray threshold value, the contrast pixel point is the pixel point of the welding resistance coverage area in the gray map to be corrected;
s34, finding out pixel points of the solder mask coverage areas in all the correction gray maps to be detected through the steps S31-S33, and removing the pixel points of the solder mask coverage areas in the correction gray maps to be detected to obtain the copper deposition electroplating areas to be detected.
S4, performing block treatment on the copper deposition electroplating area to be tested to obtain a plurality of blocks to be tested;
s5, finding out abnormal blocks to be detected according to gray features on the blocks to be detected;
the step S5 comprises the following substeps:
s51, calculating gray value distribution characteristics of each pixel point of the to-be-detected block to obtain the to-be-detected distribution characteristics;
s52, calculating the similarity between the distribution characteristics to be measured and the standard characteristics;
in this embodiment, the standard circuit board gray scale map is processed according to the processing modes of S3 and S4 to obtain a standard copper deposition electroplating area, and the standard circuit board gray scale map is segmented, and then standard features are obtained according to the processing mode of S51.
S53, judging whether the similarity is lower than a similarity threshold, if so, judging that the block to be detected is an abnormal block to be detected, and if not, judging that the block to be detected has no conductive pattern defect.
The formula for obtaining the distribution characteristics to be measured in the step S51 is as follows:
wherein,,
for the distribution feature to be measured->
For the block to be measured->
Gray value of each pixel, +.>
For the number of pixels on the block to be measured, < >>
For the maximum gray value of the pixel point on the block to be measured, < >>
The minimum gray value of the pixel points on the block to be detected is obtained.
According to the invention, the distribution characteristics of the to-be-detected blocks are obtained through the distribution condition of the gray values on the to-be-detected blocks and the sizes of the gray values, so that the characteristics of the to-be-detected blocks are expressed, and the similarity between two images is obtained through the similarity between the characteristics.
The formula for calculating the similarity in S52 is:
wherein,,
for the similarity of the distribution feature to be measured and the standard feature, < + >>
For the distribution feature to be measured->
As a standard feature of the device,
is a similarity coefficient.
S6, the abnormal blocks to be detected are segmented again, and the defect positions of the conductive patterns are found.
The step S6 comprises the following substeps:
s61, performing blocking again on the abnormal to-be-detected sub-blocks to obtain a plurality of abnormal to-be-detected sub-blocks;
s62, calculating an abnormal value of each abnormal sub-block to be detected:
wherein,,
for the abnormal value of the abnormal sub-block to be measured, < ->
For the number of pixels on the abnormal sub-block to be measured, < +.>
For the number of pixels on the standard sub-block, < +.>
For the abnormal test sub-block +.>
The distance between each pixel point and the central pixel point on the abnormal sub-block to be detected is +.>
For standard sub-block +.>
The distance between each pixel point and the central pixel point on the standard sub-block is the absolute value;
in this embodiment, the standard circuit board gray scale map is processed according to the processing modes of S3 and S4 to obtain a standard copper deposition electroplating area, and the standard copper deposition electroplating area is segmented, and then segmented again according to S61 to obtain a standard sub-segmented.
And S63, finding out abnormal sub-blocks to be detected, the abnormal value of which is greater than the abnormal threshold value, and obtaining the defect positions of the conductive patterns.
The number of the pixel points represents the size of a copper deposition electroplating area on the abnormal sub-block to be detected, the distance from the center pixel point represents the position distribution condition of the pixel points, the position distribution of the pixel points is similar, and the two images are similar and the abnormal value is smaller.
The technical scheme of the embodiment of the invention has at least the following advantages and beneficial effects: the circuit board comprises two parts: the invention utilizes a standard circuit board gray level diagram to carry out gray level correction on a circuit board diagram to be tested, improves detection precision, finds a copper plating area to be tested in the corrected gray level diagram to be tested, carries out blocking treatment on the copper plating area to be tested, finds the range of a defect, carries out blocking, and determines the position of the defect, thereby realizing a full-automatic conductive pattern defect identification method based on image processing.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A conductive pattern defect detection method for a circuit board test process, comprising the steps of:
s1, collecting a circuit board diagram to be tested in a circuit board testing process;
s2, carrying out gray level correction on the circuit board diagram to be tested according to the standard circuit board gray level diagram to obtain a corrected gray level diagram to be tested;
s3, removing a solder mask coverage area in the correction gray scale image to be detected to obtain a copper deposition electroplating area to be detected;
s4, performing block treatment on the copper deposition electroplating area to be tested to obtain a plurality of blocks to be tested;
s5, finding out abnormal blocks to be detected according to gray features on the blocks to be detected;
s6, performing secondary blocking on the abnormal to-be-detected blocks to find the defect positions of the conductive patterns;
the step S2 comprises the following sub-steps:
s21, carrying out gray scale treatment on the standard circuit board graph to obtain a standard circuit board gray scale graph;
s22, respectively taking pixel points of a solder mask coverage area and a copper deposition electroplating area in a standard circuit board gray scale map;
s23, calculating an average gray value of pixel points of a solder mask coverage area in a gray map of a standard circuit board to obtain a first standard gray value;
s24, calculating an average gray value of pixel points of a copper deposition electroplating area in the gray map of the standard circuit board to obtain a second standard gray value;
s25, carrying out graying treatment on the circuit board diagram to be tested to obtain a gray diagram to be tested;
s26, finding a plurality of pixel points of which the gray value of the gray value in the gray image to be detected and the gray value of the first standard gray value are smaller than a gray threshold value, and obtaining a first reference pixel point;
s27, finding a plurality of pixel points of which the gray value of the gray value in the gray image to be detected and the gray value of the second standard gray value are smaller than the gray threshold value, and obtaining a second reference pixel point;
s28, respectively calculating the gray average value of a plurality of first reference pixel points and the gray average value of a plurality of second reference pixel points to obtain a first reference gray value and a second reference gray value;
s29, correcting the gray value in the gray image to be detected according to the first standard gray value, the second standard gray value, the first reference gray value and the second reference gray value to obtain a corrected gray image to be detected;
the step S3 comprises the following substeps:
s31, taking any pixel point in the correction gray scale image to be detected as a contrast pixel point;
s32, calculating a gray scale distance value of the pixel points of the welding resistance coverage area in the gray scale graph of the contrast pixel points and the standard circuit board;
s33, when the gray distance value corresponding to the contrast pixel point is smaller than the gray threshold value, the contrast pixel point is the pixel point of the welding resistance coverage area in the gray map to be corrected;
s34, finding out pixel points of the solder mask coverage areas in all the correction gray maps to be detected through the steps S31-S33, and removing the pixel points of the solder mask coverage areas in the correction gray maps to be detected to obtain copper deposition electroplating areas to be detected;
s6, the following substeps are included:
s61, performing blocking again on the abnormal to-be-detected sub-blocks to obtain a plurality of abnormal to-be-detected sub-blocks;
s62, calculating an abnormal value of each abnormal sub-block to be detected:
wherein,,
for the abnormal value of the abnormal sub-block to be measured, < ->
For the number of pixels on the abnormal sub-block to be measured, < +.>
For the number of pixels on the standard sub-block, < +.>
For the abnormal test sub-block +.>
The distance between each pixel point and the central pixel point on the abnormal sub-block to be detected is +.>
For standard sub-block +.>
The distance between each pixel point and the central pixel point on the standard sub-block is the absolute value;
and S63, finding out abnormal sub-blocks to be detected, the abnormal value of which is greater than the abnormal threshold value, and obtaining the defect positions of the conductive patterns.
2. The method for detecting defects of conductive patterns used in a circuit board testing process according to claim 1, wherein the calculation formula of the gray scale distance value in S26 is:
wherein,,
for the gray level diagram to be measured +.>
Gray value of individual pixel dot +.>
And the first standard gray value->
Is a gray scale distance value of (a).
3. The method for detecting defects of conductive patterns used in a circuit board testing process according to claim 1, wherein the calculation formula of the gray scale distance value in S27 is:
wherein,,
for the gray level diagram to be measured +.>
Gray value of individual pixel dot +.>
And a second standard gray value->
Is a gray scale distance value of (a).
4. The method for detecting defects of a conductive pattern for a circuit board testing process according to claim 1, wherein the correction formula in S29 is:
wherein,,
to be measured correct gray level map +.>
Gray value of each pixel, +.>
For the first standard gray value +.>
For the second standard gray value +.>
For the first reference gray value +.>
For the second reference gray value +.>
For the gray level diagram to be measured +.>
Gray values of individual pixels.
5. The method for detecting defects of a conductive pattern for a circuit board testing process according to claim 1, wherein said S5 comprises the sub-steps of:
s51, calculating gray value distribution characteristics of each pixel point of the to-be-detected block to obtain the to-be-detected distribution characteristics;
s52, calculating the similarity between the distribution characteristics to be measured and the standard characteristics;
s53, judging whether the similarity is lower than a similarity threshold, if so, judging that the block to be detected is an abnormal block to be detected, and if not, judging that the block to be detected has no conductive pattern defect.
6. The method for detecting defects of a conductive pattern for a circuit board testing process according to claim 5, wherein the formula for obtaining the distribution characteristics to be tested in S51 is:
wherein,,
for the distribution feature to be measured->
For the block to be measured->
Gray value of each pixel, +.>
For the number of pixels on the block to be measured, < >>
For the maximum gray value of the pixel point on the block to be measured, < >>
The minimum gray value of the pixel points on the block to be detected is obtained.
7. The method for detecting defects in a conductive pattern for a circuit board testing process according to claim 5, wherein the formula for calculating the similarity in S52 is:
wherein,,
for the similarity of the distribution feature to be measured and the standard feature, < + >>
For the distribution feature to be measured->
For standard feature->
Is a similarity coefficient.
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| US6208412B1 (en) * | 1999-06-14 | 2001-03-27 | Visteon Global Technologies, Inc. | Method and apparatus for determining optical quality |
| JP4004998B2 (en) * | 2003-06-23 | 2007-11-07 | 三井金属鉱業株式会社 | Manufacturing method of flexible printed wiring board |
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Denomination of invention: A conductive pattern defect detection method for circuit board testing process Granted publication date: 20230711 Pledgee: Chengdu financial holding Financing Guarantee Co.,Ltd. Pledgor: CHENGDU CAVT TECHNOLOGY CO.,LTD. Registration number: Y2024510000072 |