CN1162192A

CN1162192A - Isolation method for use in semiconductor device

Info

Publication number: CN1162192A
Application number: CN97101876A
Authority: CN
Inventors: 权五成
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1996-01-11
Filing date: 1997-01-11
Publication date: 1997-10-15
Anticipated expiration: 2017-01-11
Also published as: CN1064779C; KR19980030859U

Abstract

The present invention discloses an isolation method in a semiconductor device. The method includes the steps of: forming a pad oxide film, a buffer polysilicon layer, and a nitride layer; etching the nitride layer and the buffer polysilicon layer; forming a field oxide layer on the device isolation regions of the cell region and the peripheral region; etching the exposed substrate in the device isolation regions of the cell region and the peripheral region; forming a first insulating layer; etching to form a spacer in the side wall of the field oxide layer on the exposed substrate; etching the exposed substrate to form a trench; forming a second insulating layer to fill the trench with the second insulating layer; planarizing the surface of the substrate; and removing the nitride layer and the buffer polysilicon layer.

Description

Partition method in the semiconductor device

The present invention relates to a kind of method that forms semiconductor device, particularly a kind of method of utilizing grooving technology and LOCOS (silicon selective oxidation) technology to form the isolated area in the semiconductor device.

As everyone knows, the LOCOS technology is generally as the isolation technology in the semiconductor device.Utilize the isolation technology of LOCOS method to have such problem, promptly the area of the shared Semiconductor substrate of field oxide region is relatively large, so that active area reduces, and the topological structure in the semiconductor device is owing to the step between substrate and field oxide region becomes higher.As the method that addresses these problems, a kind of size of field oxide region and method of height of reducing proposed once.

Yet this method can cause being difficult to obtain the problem of the electrical insulation characteristics in the semiconductor device.

In order to solve this problem in the isolation technology that utilizes conventional LOCOS method, SALOT (autoregistration LOCOS groove) technology that a kind of LOCOS method combines with the grooving method has been proposed (referring to InternationalElectron Device Meeting, 28.2.1,675-678pp, 1994).

Figure 1A-1E is the profile that the processing step of the isolation technology that utilizes conventional SALOT technology is described.

Referring to Figure 1A, on Semiconductor substrate 1, form the thick liner oxide film (padoxide film) 2 of about 100-120 dust.Then, the thick buffering polysilicon layer 3 of the about 600-800 dust of deposit on liner oxide film 2, the stress that the oxidation mask that will form with buffering produces.The nitration case 4 that the about 1500-2500 dust of deposit is thick on polysilicon layer 3 then, is used conventional photoetching process as oxidation mask, forms the photoresist (not shown) on buffering polysilicon layer 3.Subsequently, utilize photoresist to make mask, corrode nitration case 4, buffering polysilicon layer 3 and liner oxide film 2 successively, the device isolation region of exposure unit district 1A and external zones 1B.By carrying out an oxidation technology, on the device isolation region of the exposure of cellular zone 1A and external zones 1B, form the field oxide 5A and the 5B of thick 1000-1100 dust.

Referring to Figure 1A, to compare with field oxide 5A among the cellular zone 1A, the field oxide 5B area among the external zones 1B is bigger.

Referring to Figure 1B, by low-pressure chemical vapor phase deposition (LPCVD) technology, the polysilicon film of the thick about 900-1000 dust of deposit on the whole surface of established substrate.Then, carry out anisotropic etch, on the two side of the nitration case on field oxide 5A and the 5B 4, form polycrystalline isolating pad 6A and 6B.Subsequently, form photoresist 7, field oxide 5A among the exposure unit district 1A and polycrystalline isolating pad 6A.

Referring now to Fig. 1 C,, make mask with photoresist 7, field oxide 5A among the anisotropic etch cellular zone 1A and substrate 1 form the groove 8 of thick about 2500-3500 dust.At this moment, utilize this anisotropy rot etching technique to remove polycrystalline isolating pad 6A simultaneously.Thereby the purpose that forms groove 8 in the substrate 1 of cellular zone 1A is by making device isolation region extend to the substrate 1 inner electrical insulation characteristics that obtains.Owing to form the crystal defect that the etching process of groove 8 causes, carry out thermal oxidation technology in order to prevent, so in groove 8, form oxide film 9.

Referring to Fig. 1 D, then, form the CVD oxide layer 10 of thick about 2300-2700 dust, to fill up groove 8.Then, with chemico-mechanical polishing (CMP) corrosion oxidation layer 10, till exposing nitration case 4 fully.

Referring now to Fig. 1 E,, remove remaining nitration case 4 and polysilicon layer 3, form device isolation region 5A ' and 5B.

Thereby, at cellular zone 1A, provide by being filled in the SALOT structure that field oxide 5A that CVD oxide layer 10 in the groove 8 and LOCOS technology forms constitutes, at external zones 1B, the device isolation region that provides field oxide 5B to constitute.

Yet there is following problem in these conventional isolation technologies:

At first, when photoresist is exposed,, therefore need remove the additional process of polycrystalline isolating pad because misalignment causes meeting residual fraction polycrystalline isolating pad after forming groove.

The second, need carry out LOCOS technology and twice mask process that forms groove.

The 3rd, necessary additional heat oxidation technology forms dislocation to prevent owing to form groove in substrate, so the process time prolongs, yield poorly.

The 4th, because the substrate surface out-of-flatness, topological structure is poor, thereby is difficult to carry out subsequent technique.

General purpose of the present invention provides a kind of method of isolation of semiconductor devices, by form the isolated area of identical figure at identical shaped cellular zone and external zones, can only carry out one time mask process.

The present invention's purpose more specifically provides a kind of method of isolation of semiconductor devices, by eliminating the difference of surface topology, can improve process margin and integration density.

Another object of the present invention provides a kind of method of isolation of semiconductor devices, by reducing the thickness of field oxide, reduces the beak phenomenon, can increase active area.

In order to realize these purposes, have in qualification on the Semiconductor substrate of the cellular zone of corresponding device isolated area and external zones, form liner oxide film, buffering polysilicon layer and nitration case successively.After this, nitration case on the device isolation region of erosion unit district and external zones and buffering polysilicon layer.Then, on the device isolation region of cellular zone and external zones, form field oxide.The field oxide of corrosion except that the edge part is in order to the substrate at the device isolation region place of exposure unit district and external zones.Afterwards, formerly form first insulating barrier on the substrate of corrosion step gained.Corrode first insulating barrier again, on the field oxide sidewall on the substrate that exposes, form isolating pad.Next step, the substrate that corrosion exposes forms groove.Then, on the substrate that has formed groove, form second insulating barrier, so that fill this groove with second insulating barrier.Then, corrode second insulating barrier, make the surface planarization of substrate.At last, remove nitration case and buffering polysilicon layer.

By with reference to the following explanation of clearly having showed each accompanying drawing of preferred embodiment, understand clearer other purpose of the present invention and advantage.In each accompanying drawing:

Figure 1A-1E is the profile of the semiconductor device of conventional each manufacturing step of partition method in the explanation semiconductor device;

Fig. 2 A-2G is the profile of explanation by the semiconductor device of each manufacturing step of partition method in the semiconductor device of the present invention.

Referring to Fig. 2 A, on the Semiconductor substrate 21 that limits cellular zone 21A and external zones 21B, form the buffering polysilicon layer 23 of the liner oxide film 22 of thick about 150 dusts, thick about 500 dusts and the nitration case 24 of thick about 2000 dusts successively.Utilize conventional photoetching process, on nitration case 24, form photoresist figure (not shown), then, make mask, corrosion nitration case 24 and polysilicon layer 23 with this photoresist figure.At this moment, corrosion polysilicon layer 23 is so dark to the thick about 200-250 dust of the buffering polysilicon that makes the reservation in cellular zone 21A and the external zones, is preferably formed as the photoresist figure of the about 0.4-0.6 μ of minimum feature m, to adapt to the existing trend of high integration.

Referring to Fig. 2 B, remove the photoresist figure, then, form field oxide 25 in the isolated area between cellular zone 21A and external zones 21B.In the present embodiment, form the field oxide 25 of thick about 2000-3000 dust, it is thinner than the field oxide thickness that a conventional oxidation technology forms.

In the present embodiment, the formation of thin field oxide film can reduce the generation of beak phenomenon.

Referring to Fig. 2 C, utilize again as salt down the nitration case 24 of mould of oxidation, the field oxide 25 among erosion unit district 21A and the external zones 21B is to suppress the oxidation of bottom liner oxide film.Herein, the field oxide except that the marginal zone that comprises the beak district all is corroded.Then, utilize low-pressure chemical vapor phase deposition technology, the TEOS oxide layer 26 that the about 1800-2200 dust of deposit is thick.

Referring now to Fig. 2 D,, anisotropy mask etch TEOS oxide layer 26, the corrosion of field oxide 25 partly form sidewall spacer 26 '.At this moment, be preferably formed as the isolating pad of wide about 0.1-0.2 μ m.Form sidewall spacer 26 ' after, utilize nitration case 24 and TEOS isolating pad 26 ' make mask, corrosion substrate 21 forms groove 27 in cellular zone 21A and external zones 21B.At this moment, groove 27 dark about 0.1-0.3 μ m.

In the present embodiment, since as the nitration case 24 of the oxidation mask of LOCOS technology again as the etching mask that forms groove, so do not need the mask process of other formation groove.At this moment, the width W of coming the groove 27 among the determining unit district 21A according to the spacing W1 between nitration case and the adjacent nitration case and the wide W2 of isolating pad.Be W=W1-2W2.For example, if spacing W1 is 0.5 μ m, the wide W2 of isolating pad is 0.15 μ m, and then groove width W is 0.2 μ m (=0.5-2 * 0.15 μ m).

Referring to Fig. 2 E, under 760-800 ℃ temperature, at SiH ₄And N ₂In the O gas atmosphere, low pressure chemical vapor deposition is enough to fill up high-temperature oxydation (HTO) layer 28 of groove 27 as thick about 6000-7000 dust on the whole surface of substrate.In the step that is formed HTO layer 28 by low pressure chemical vapor deposition technology, the crystal defect in the part that is corroded of damaged substrate is capped, and has formed the thick oxide film 29 of tens dusts in groove 27.

Referring now to Fig. 2 F,, utilize nitration case 24 as the etch stop layer in the CMP technology, corrosion HTO layer 28 is so form the substrate surface of complanation.

Then, referring to Fig. 2 G, remove remaining nitration case 24 and buffering polysilicon layer 23, corrosion liner oxide film 22 is up to staying the thick liner oxide film of 50-150 dust with till protecting substrate.Thereby, shown in Fig. 2 G, in cellular zone 21A and external zones 21B, form the identical device isolation region of shape.

As mentioned above, by the present invention, can obtain following advantage and performance.

At first, owing to formed the identical isolated area of shape at cellular zone and external zones respectively, only need once form the mask process of isolated area.Thereby, simplified technology, improved output.

The second, no matter be LOCOS technology or form isolated area with grooving technology, the difference of surface topology all takes place hardly.Therefore, process margin and integration density improve.

The 3rd, owing in LOCOS technology, form thin field oxide, so reduced the generation of beak phenomenon.Thereby, increased active area, might make highly integrated circuit.

After having read above-mentioned explanation, those of ordinary skill in the art can be readily understood that further feature disclosed in this invention, advantage and embodiment.Therefore, owing to very described specific embodiments of the invention in detail, so under situation about not breaking away from, can make various variations and remodeling to these embodiment as spirit of the present invention as described in specification and claims and essence and scope.

Claims

1, the partition method in the semiconductor device may further comprise the steps:

Have in qualification on the Semiconductor substrate of the cellular zone of corresponding device isolated area and external zones, form liner oxide film, buffering polysilicon layer and nitration case successively;

Nitration case on the device isolation region of erosion unit district and external zones and buffering polysilicon layer;

On the device isolation region of cellular zone and external zones, form field oxide;

The field oxide of corrosion except that the edge part, the substrate in the device isolation region of exposure unit district and external zones;

Formerly form first insulating barrier on the substrate of corrosion step gained;

Corrode first insulating barrier, on the field oxide sidewall on the substrate that exposes, form isolating pad;

The substrate that corrosion exposes forms groove;

On the substrate that has formed groove, form second insulating barrier, so that fill this groove with second insulating barrier;

Corrode second insulating barrier, make the surface planarization of substrate; And

Remove nitration case and buffering polysilicon layer.

2, partition method according to claim 1 wherein, in the step of carrying out described corrosion nitration case and buffering polysilicon layer, keeps the thick buffering polysilicon layer of 200-300 dust.

3, partition method according to claim 1 wherein, forms described field oxide by the thickness of 2000-3000 dust.

4, partition method according to claim 1 wherein, is pressed the thickness of 1800-2000 dust, utilizes low-pressure chemical vapor deposition method, described first insulating barrier of deposit.

5, partition method according to claim 4, wherein, described first insulating barrier is TEOS.

6, partition method according to claim 1, wherein, the wide 0.1-0.2 μ of described isolating pad m.

7, partition method according to claim 1, wherein, the corrosion described substrate with the step that forms described groove in, make mask with described nitration case and described isolating pad.

8, partition method according to claim 7 wherein, is corroded described substrate by the degree of depth of 0.1-0.3 μ m.

9, partition method according to claim 1 wherein, is pressed the thickness of 6000-7000 dust, described second insulating barrier of low pressure chemical vapor deposition.

10, partition method according to claim 9, wherein said second insulating barrier is the HTO layer.

11, partition method according to claim 1 wherein, is corroded in the described second insulating barrier step and is corroded described second insulating barrier with the CMP method, wherein makes mask with described nitration case.