CN116207182A - Chip preparation method and electronic device - Google Patents
Chip preparation method and electronic device Download PDFInfo
- Publication number
- CN116207182A CN116207182A CN202310114341.0A CN202310114341A CN116207182A CN 116207182 A CN116207182 A CN 116207182A CN 202310114341 A CN202310114341 A CN 202310114341A CN 116207182 A CN116207182 A CN 116207182A
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- chip
- raw material
- epitaxial layer
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- scribing
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000002994 raw material Substances 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 5
- 238000003486 chemical etching Methods 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000000992 sputter etching Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 47
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005057 refrigeration Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001931 thermography Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1876—Particular processes or apparatus for batch treatment of the devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Dicing (AREA)
Abstract
The invention provides a chip preparation method and an electronic device, wherein the preparation method comprises the following steps: determining a scribing area on the surface of a raw material sheet, and coating photoresist on other areas of the surface of the raw material sheet except the scribing area; etching the epitaxial layer on the outermost layer of the surface of the raw material sheet, which corresponds to the part in the scribing area, and exposing a substrate layer below the epitaxial layer; the substrate layer in the scribe area is cut to separate chip modules from the raw sheet. According to the technical scheme, the epitaxial layer in the scribing area is firstly etched, scribing is carried out, so that the rest epitaxial layer can form a smooth edge end face, a cutter for scribing cannot touch the rest epitaxial layer, and further damage such as cracks and broken edges cannot be generated at the edge of the epitaxial layer.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a chip preparation method and an electronic device.
Background
In various electronic devices, a chip is one of essential core components, and in the process of preparing the chip, a dicing process for the chip is a necessary process. In the current dicing mode, the edges of the chips are grinded and cut by a dicing blade in the dicing process, so that the periphery of the chips can be damaged to different degrees, and micro cracks, broken edges and other damages are generated. These damage can lead to subsequent device failure in certain types of electronic devices.
For example, when the chip is applied to an infrared detector, the main development direction in the infrared detector field is a refrigeration type infrared detector, and the refrigeration type infrared detector has wide application in the aspects of infrared thermal imaging, infrared remote sensing and the like. When the detector works, the temperature of the detector can be reduced to 80k from room temperature, and severe temperature change can cause thermal mismatch in the detector chip, especially the damage is aggravated at the position of the edge during scribing, and cracks are formed under the influence of the thermal mismatch. When serious, cracks can extend into the detector to influence the performance of the detector, and continuous blind pixels are generated to cause the detector to fail or fail.
If damage to the edge of the chip is avoided in the preparation process of the chip of the detector, the preparation yield of the chip of the detector can be remarkably improved. Therefore, how to avoid the damage to the chip edge is a problem to be solved in the present art.
Disclosure of Invention
The invention provides a chip preparation method and an electronic device, and aims to solve the problem of device qualification caused by damages such as cracks, broken edges and the like generated by chip edges in the prior art.
In a first aspect, the present invention provides a chip preparation method, including:
determining a scribing area on the surface of a raw material sheet, and coating photoresist on other areas of the surface of the raw material sheet except the scribing area;
etching the epitaxial layer on the outermost layer of the surface of the raw material sheet, which corresponds to the part in the scribing area, and exposing a substrate layer below the epitaxial layer;
the substrate layer in the dicing area is cut to separate chip units from the raw material sheet.
In one embodiment, before cutting the substrate layer in the scribe area, the method further comprises:
and removing the photoresist coated on the other areas of the surface of the raw material sheet, and coating the photoresist on the whole surface of the raw material sheet again.
In one embodiment, the epitaxial layer on the outermost layer of the surface of the raw material wafer is etched to form a scribing groove corresponding to the part in the scribing region, the width of the scribing groove is larger than the thickness of the scribing cutter, and the depth of the scribing groove is larger than the thickness of the epitaxial layer.
In one embodiment, chemical etching, ion etching or laser ablation is used to remove the portion of the epitaxial layer of the outermost layer of the surface of the raw material sheet that corresponds to the scribe area.
In one embodiment, the method further comprises:
connecting the chip unit with a circuit module, wherein the epitaxial layer of the chip unit is connected with the surface of the circuit module through a plurality of welding balls;
and removing the substrate layer of the chip unit.
In one embodiment, before the chip unit is connected to the circuit module, the method further comprises:
and removing the photoresist coated on the chip unit, and cleaning the chip unit.
In one embodiment, the solder balls are indium balls.
In a second aspect, the electronic device provided by the invention comprises the chip prepared by the preparation method, and further has all technical effects.
The above-described features may be combined in various suitable ways or replaced by equivalent features as long as the object of the present invention can be achieved.
Compared with the prior art, the chip preparation method and the electronic device provided by the invention have the following beneficial effects:
according to the chip preparation method and the electronic device, the epitaxial layer in the scribing area is firstly etched, scribing is carried out, so that the rest of the epitaxial layer can form a smooth edge end face, a scribing cutter cannot touch the rest of the epitaxial layer, and further damage such as cracks and broken edges can not be generated at the edge of the epitaxial layer.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
FIG. 1 shows a schematic diagram of the main flow of the preparation method of the present invention;
FIG. 2 shows a schematic diagram of the structure of a raw material sheet corresponding to the preparation method of the present invention;
FIG. 3 is a schematic view showing the structure of the scribe line formed on the structure shown in FIG. 2;
FIG. 4 is a schematic diagram showing the structure of FIG. 3 after removal of the original photoresist;
FIG. 5 is a schematic diagram showing the structure of FIG. 4 after the photoresist has been applied again in its entirety;
FIG. 6 is a schematic view showing the structure of FIG. 5 after dicing to separate out the chip units;
FIG. 7 is a schematic diagram showing the structure of the separated chip unit of FIG. 6 after being connected to a circuit module;
fig. 8 shows a schematic view of the structure of fig. 7 with the substrate layer removed.
In the drawings, like parts are designated with like reference numerals. The figures are not to scale.
Reference numerals:
1-scribing area, 2-photoresist, 3-epitaxial layer, 4-substrate layer, 5-scribing groove, 6-circuit module and 7-welding ball.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Referring to fig. 1 to 8 of the drawings, an embodiment of the present invention provides a chip manufacturing method, including:
step S100: a dicing area 1 is defined on the surface of the raw material sheet, and a photoresist 2 is coated on other areas of the surface of the raw material sheet except for the dicing area 1.
Specifically, as shown in fig. 2 of the accompanying drawings, the first step in chip preparation is to separate the base of the prepared chip from the raw material sheet. The raw material wafer originally comprises a two-layer structure, namely an epitaxial layer 3 serving as a surface layer and a substrate layer serving as a base, wherein the epitaxial layer 3 is just the basis of a chip, and a dicing process is required to separate a chip unit with part of the epitaxial layer 3 from the raw material wafer. Firstly, a scribing area 1 is determined on the surface of a raw material sheet according to the sizes of the raw material sheet and a chip, the area outside the scribing area 1 is used as a chip unit capable of preparing a chip finished product after scribing in principle, and the surface of the area outside the scribing area 1 is coated with photoresist 2 for protection.
Step S200: the outermost epitaxial layer 3 on the surface of the raw material sheet is etched away to expose the substrate layer located below the epitaxial layer 3 in the portion corresponding to the scribe area 1.
Specifically, chemical etching, ion etching or laser ablation is used to remove the portion of the epitaxial layer 3 of the outermost layer on the surface of the raw material sheet corresponding to the scribe area 1. As shown in fig. 3 of the accompanying drawings, due to the protection of the photoresist 2, only the portion of the epitaxial layer 3 on the raw material wafer corresponding to the scribing region 1 is etched away, compared with mechanical scribing, chemical etching, ion etching or laser ablation is adopted, the edge of the epitaxial layer 3 which is protected by the photoresist 2 and is reserved is not damaged, such as cracks, broken edges and the like, and the end face of the edge is smooth and free from damage.
Simultaneously, the epitaxial layer 3 on the outermost layer of the surface of the raw material wafer is etched to form a scribing groove 5 at a part corresponding to the inside of the scribing region 1, the width of the scribing groove 5 is larger than the thickness of the scribing cutter, and the depth of the scribing groove 5 is larger than the thickness of the epitaxial layer 3. I.e. the size of the scribe line 5 needs to be controlled, mainly by having a width wide enough for the scribe tool to enter; the depth is required to be larger than the thickness of the epitaxial layer 3, so that the epitaxial layer 3 at the scribing area 1 is completely etched, and the bottom surface of the scribing groove 5 (the scribing reference surface) is staggered with the interface between the epitaxial layer 3 and the substrate layer, so that the possible damage to the edge of the epitaxial layer 3 caused by the fact that the force acting on the bottom surface of the scribing groove 5 during scribing is directly transmitted to the interface between the epitaxial layer 3 and the substrate layer is avoided.
Step S210: the photoresist 2 coated on other areas of the surface of the raw material sheet is removed, and the photoresist 2 is entirely coated on the surface of the raw material sheet again.
Specifically, as shown in fig. 4 and 5 of the accompanying drawings, after forming the dicing grooves 5 and before dicing, the photoresist 2 originally partially coated on the raw material piece is taken out, the photoresist 2 is integrally coated again, the photoresist 2 is coated again, the area corresponding to the chip unit is covered by the photoresist 2, and meanwhile, the dicing grooves 5 formed in the dicing area 1 are also covered, so that the purpose of completely wrapping the top surface and the peripheral surface of the chip unit by the photoresist 2 is to avoid damage to the material surface by chips generated in the dicing process.
Step S300: the substrate layer in the scribe area 1 is cut to separate the chip units from the raw material sheet.
Step S310: the photoresist 2 coated on the chip unit is removed and the chip unit is cleaned.
In particular, as shown in fig. 6 of the drawings, for the substrate material, since it is removed in the subsequent process, the edge state of the substrate has less influence on the detector chip and can be scribed by a conventional scribe-lane manner. After dicing the substrate layer of the scribe area 1, the chip units for further chip preparation are separated.
Step S400: connecting the chip unit with the circuit module 6, wherein the epitaxial layer 3 of the chip unit is connected with the surface of the circuit module 6 through a plurality of welding balls 7, and the welding balls 7 are indium balls;
step S500: the substrate layer of the chip unit is removed.
Specifically, as shown in fig. 7 and 8 of the drawings, the chip unit is flip-chip mounted on the circuit module 6, the epitaxial layer 3 of the chip unit and the circuit module 6 are soldered by using solder balls 7, and the solder balls 7 may be indium balls or other materials. The preparation process in this application is completed, and the following step of further packaging the structure shown in fig. 8 is of course also involved, but the present disclosure is not limited thereto, and thus will not be further described.
The embodiment of the invention also provides an electronic device, which comprises the chip prepared by adopting the preparation method, and further has all the technical effects.
In the description of the present invention, it should be understood that the terms "upper," "lower," "bottom," "top," "front," "rear," "inner," "outer," "left," "right," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features described herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other described embodiments.
Claims (8)
1. A method of manufacturing a chip, comprising:
determining a scribing area on the surface of a raw material sheet, and coating photoresist on other areas of the surface of the raw material sheet except the scribing area;
etching the epitaxial layer on the outermost layer of the surface of the raw material sheet, which corresponds to the part in the scribing area, and exposing a substrate layer below the epitaxial layer;
the substrate layer in the dicing area is cut to separate chip units from the raw material sheet.
2. The chip manufacturing method according to claim 1, further comprising, before dicing the substrate layer in the dicing area:
and removing the photoresist coated on the other areas of the surface of the raw material sheet, and coating the photoresist on the whole surface of the raw material sheet again.
3. The method of manufacturing a chip according to claim 1, wherein a dicing groove is formed in a portion of the epitaxial layer of the outermost layer of the surface of the raw material wafer corresponding to the dicing area, the dicing groove having a width larger than a thickness of the dicing blade, and the dicing groove having a depth larger than the thickness of the epitaxial layer.
4. The method of claim 1, wherein the portion of the epitaxial layer on the outermost surface of the raw material wafer corresponding to the scribe area is removed by chemical etching, ion etching or laser ablation.
5. The chip preparation method according to claim 1, further comprising:
connecting the chip unit with a circuit module, wherein the epitaxial layer of the chip unit is connected with the surface of the circuit module through a plurality of welding balls;
and removing the substrate layer of the chip unit.
6. The chip manufacturing method according to claim 5, further comprising, before connecting the chip unit with the circuit module:
and removing the photoresist coated on the chip unit, and cleaning the chip unit.
7. The method of manufacturing a chip as claimed in claim 5, wherein the solder balls are indium balls.
8. An electronic device comprising a chip manufactured by the manufacturing method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310114341.0A CN116207182B (en) | 2023-01-29 | 2023-01-29 | Chip preparation method and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310114341.0A CN116207182B (en) | 2023-01-29 | 2023-01-29 | Chip preparation method and electronic device |
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| Publication Number | Publication Date |
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| CN116207182A true CN116207182A (en) | 2023-06-02 |
| CN116207182B CN116207182B (en) | 2024-03-12 |
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| CN202310114341.0A Active CN116207182B (en) | 2023-01-29 | 2023-01-29 | Chip preparation method and electronic device |
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|---|---|
| CN116207182B (en) | 2024-03-12 |
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