CN116207170A - Laminated solid-state doping source structure and preparation method of p-type TOPCON solar cell - Google Patents
Laminated solid-state doping source structure and preparation method of p-type TOPCON solar cell Download PDFInfo
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
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- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
- H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
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Abstract
The invention provides a laminated solid-state doping source structure and a preparation method of a p-type TOPCON solar cell. The invention uses the laminated structure of the medium layer and the phosphorus doping source amorphous silicon layer as the phosphorus diffusion source, has good electricity and passivation performance, and can regulate and control the diffusion temperature to be matched with the annealing temperature of the back p-TOPCon structure, thereby realizing the preparation process of one-step annealing.
Description
Technical Field
The invention relates to the technical field of photovoltaic cells, in particular to a laminated solid-state doping source structure and a p-type TOPCON solar cell preparation method.
Background
Tunneling silicon oxide passivation contact (TOPCon) crystalline silicon solar cells are widely recognized as a next generation high efficiency cell technology. The current industry focuses on developing an n-type TOPCon battery with high efficiency, however, the n-type TOPCon battery adopts an n-type silicon wafer and double-sided silver paste, and the cost is high. If a p-type TOPCon cell based on a p-type silicon wafer can be developed, the efficiency of the p-type cell can be improved, and the low cost advantages of the p-type silicon wafer and the industry ecology can be maintained, which has become a hot spot of current industry attention.
The phosphorus emitter is one of the key components of the p-type TOPCON solar cell, but the preparation process of the phosphorus emitter in the prior art has the following defects: 1) Phosphorus diffusion techniques typically use phosphorus oxychloride (POCl) 3 ) As a diffusion source, toxic byproducts and a large amount of metaphosphoric acid are easy to generate in the diffusion process, and the quartz piece is corroded, so that the maintenance cost is increased; 2) The surface concentration of the phosphorus emitter prepared by the traditional method is too high (generally 2-5 multiplied by 10 20 cm -3 ) Resulting in higher surface recombination>25fA/cm 2 ) The open-circuit voltage of the p-type battery is severely limited; 3) In terms of process steps, POCl 3 The temperature of the phosphorus expansion of (a) is typically around 860 ℃, whereas the preparation temperature of the back p-TOPCon structure is typically 900-950 ℃, and the preparation temperatures are not matched, resulting in process incompatibility. 4) Finally, the preparation of the front-side phosphorus-expanding emitter and the preparation of the p-TOPCon structure of the back-side of the existing battery require two high-temperature annealing processes, so that the process steps are increased.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to solve the technical problems of developing a novel phosphorus doping source to regulate and control the annealing temperature during the preparation of a phosphorus emitter, simplify the preparation process of a p-type TOPCO solar cell and reduce the production cost.
In order to solve the above problems, the present invention provides a double-sided source structure based on a stacked solid-state doping source and a manufacturing technology thereof, wherein the stacked solid-state doping source structure comprises a phosphorus doping source amorphous silicon layer, a front dielectric layer, a crystalline silicon substrate, a back dielectric layer and a boron doping source amorphous silicon layer which are stacked.
The invention takes an innovative material system as a front phosphorus source, namely takes a laminated structure of a dielectric layer and a phosphorus doping source amorphous silicon layer as a phosphorus diffusion source, has good electricity and passivation performance, and can regulate and control diffusion temperature to be matched with annealing temperature of a back p-TOPCON structure, thereby realizing a preparation process of one-step annealing; the dielectric layer can avoid the occurrence of stacking fault defects and remarkably improve the passivation effect of the emitter. It is noted that the phosphorus doped source structure can also be used as a phosphorus doped source layer required for laser selective emitter (laser SE) technology, and the laser treated region can form a high concentration phosphorus doped region.
Further, the doping atoms of the boron doping source amorphous silicon layer comprise one or more of carbon (C), nitrogen (N) and oxygen (O) besides boron, and the doping concentration is 1E17-1E22 cm -3 。
Further, the doping atoms of the phosphorus doping source amorphous silicon layer comprise one or more of carbon, nitrogen and oxygen besides phosphorus, and the doping concentration is 1E17-1E22 cm -3 。
The front surface and the boron doping source amorphous silicon layer can be respectively doped with carbon (C), nitrogen (N) and oxygen (O) to adjust the annealing temperature, so that the front surface and the back surface are matched with each other in high-temperature treatment temperature, and the passivation and electrical properties are good.
Further, the phosphorus doping concentration of the phosphorus doping source amorphous silicon layer is 1E19-1E21cm -3 Preferably 1E19-5E19cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The boron doping concentration of the boron doping source amorphous silicon layer is 1E17-5E20cm -3 Preferably 1E19-5E19cm -3 . The phosphorus/boron doping concentration in the doping source amorphous silicon layer is limited, so that the annealing temperature required by diffusion is reduced.
Further, the front dielectric layer is selected from any one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film, and the back dielectric layer is selected from any one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film. The front dielectric layer can avoid the contact between amorphous silicon and polycrystalline silicon and the substrate, thereby avoiding the crystal defects such as the stacking fault and the like caused by the epitaxial growth of the amorphous silicon during high-temperature annealing and obviously improving the passivation effect of the emitter; in addition, the existence of the front dielectric layer has little influence on the emitter sheet resistance and junction depth.
Further, the thickness of the phosphorus doped source amorphous silicon layer is 1-200nm, preferably 3-30nm; the thickness of the front dielectric layer is 1-5nm, preferably 1-3nm; the thickness of the back dielectric layer is 1-5nm, preferably 1-3nm; the thickness of the boron doped source amorphous silicon layer is 20-200nm, preferably 25-60nm. The thickness of the key material is limited, the subsequent wet etching is convenient, and the phosphorus expansion and passivation effects can be ensured.
The invention also provides a preparation method of the p-type TOPCON solar cell, which comprises the following steps:
s1, preparing a front dielectric layer on the front side of a crystalline silicon substrate;
s2, depositing a phosphorus doping source amorphous silicon layer serving as a phosphorus source on the front dielectric layer;
s3, preparing a back medium layer on the back of the crystalline silicon substrate;
s4, depositing a boron doping source amorphous silicon layer on the back dielectric layer to serve as a boron source;
s5, performing one-step high-temperature annealing treatment to enable phosphorus on the front surface of the crystalline silicon substrate to diffuse to form an emitter and amorphous silicon on the back surface to crystallize;
s6, etching the phosphorus doping source amorphous silicon layer and the front dielectric layer on the front side of the crystalline silicon substrate;
s7, depositing a passivation layer and an anti-reflection layer on the front surface and/or the back surface;
and S8, carrying out front and back metallization treatment to obtain the solar cell.
The invention firstly forms the front and back source layer structures by continuous deposition, simultaneously prepares the front phosphorus emitter and the back p-TOPCON structure by one-step high-temperature annealing, combines two high-temperature treatment processes which are originally needed to be carried out twice, finally realizes double-sided film coating, and can reduce the production steps of the p-type TOPCON solar cell by one-step high-temperature annealing preparation process.
Further, in the step S2 and the step S4, the phosphorus doped source amorphous silicon layer and the boron doped source amorphous silicon layer may be PECVD, APCVD, LPCVD or the like deposited by CVD or PVD. Preferably PECVD, the phosphorus doped source amorphous silicon layer and the boron doped source amorphous silicon layer are deposited by a PECVD method, and the activation concentration of phosphorus/boron is high, so that the annealing temperature can be reduced; and the deposition reaction gas is gas, so that the deposition uniformity is high.
Further, in the step S4, the high temperature annealing treatment temperature is 750 to 1000 ℃, preferably 850 to 950 ℃. The front surface of the crystalline silicon substrate is a diffusion structure of a dielectric layer/phosphorus-doped amorphous silicon film, the back surface of the crystalline silicon substrate adopts the dielectric layer/boron-doped amorphous silicon film as a p-TOPCon structure, so that the annealing temperature is matched with the front surface diffusion temperature, the originally inconsistent high-temperature treatment processes on the two sides are unified, the diffusion and crystallization are realized in one high-temperature step, and the process steps are reduced.
Further, in the step S1 and the step S3, the preparation method of the front dielectric layer and the back dielectric layer is selected from one of the following: PECVD, LPCVD, wet chemical, high temperature oxidation, plasma assisted oxidation, and plasma assisted atomic layer deposition.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention uses CVD or PVD method to deposit amorphous silicon layer of phosphor doping source as solid phosphor source layer, and the deposition reaction gas is gas, the uniformity of deposition is high; no by-products having corrosive action on the quartz tube are produced.
(2) A dielectric layer is introduced between the phosphorus doped source amorphous silicon layer and the crystalline silicon substrate, so that contact between amorphous silicon and the substrate can be avoided, crystal defects such as stacking faults caused by epitaxial growth of amorphous silicon during high-temperature annealing are avoided, and the passivation effect of an emitter is remarkably improved; the existence of the dielectric layer has little influence on the emitter sheet resistance and junction depth; the presence of the dielectric layer also allows for adjustment of the surface concentration and diffusion depth of phosphorus, which provides room for improved emitter passivation performance and doping profile.
(3) The phosphorus doped source amorphous silicon layer and the boron doped source amorphous silicon layer can adopt medium layers with different thicknesses or adjust annealing temperature by doping carbon, nitrogen, oxygen and the like, so that the front and back surface high temperature treatment temperatures are matched, and simultaneously, the passivation and electrical properties are good.
(4) Due to SiO in alkaline solution x High selectivity etch ratio between the dielectric layer and polysilicon, the SiO can be completely removed by alkaline etching in mass production x Polysilicon on the layer.
(5) According to the invention, the front diffusion and the back p-TOPCO structure preparation of the solar cell and the subsequent high-temperature treatment are combined together by combining the CVD or PVD pre-deposition with the primary annealing treatment technology, so that the original inconsistent high-temperature treatment processes at two sides are unified, the double-sided film coating is finally realized, the primary high-temperature annealing is realized, the process steps for preparing the p-type TOPCO solar cell are reduced, and the production efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of a stacked solid-state dopant source structure according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another stacked solid-state dopant source structure according to an embodiment of the present invention.
Fig. 3 is a block diagram of a p-type TOPCon solar cell in accordance with an embodiment of the present invention.
Fig. 4 is a schematic flow chart of a method for manufacturing a p-type TOPCon solar cell according to an embodiment of the present invention.
Reference numerals illustrate:
the semiconductor device comprises a 1-crystalline silicon substrate, a 2-front dielectric layer, a 3-phosphorus doped source amorphous silicon layer, a 4-back dielectric layer, a 5-boron doped source amorphous silicon layer, a 6-emitter, a 7-back heavily doped polycrystalline silicon layer, an 8-passivation layer, a 9-antireflection layer, a 10-front metal electrode and an 11-back metal electrode.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It should be noted that the following examples are only for illustrating the implementation method and typical parameters of the present invention, and are not intended to limit the scope of the parameters described in the present invention, so that reasonable variations are introduced and still fall within the scope of the claims of the present invention.
It should be noted that endpoints and any values of the ranges disclosed herein are not limited to the precise range or value, and that such range or value should be understood to include values approaching such range or value. For numerical ranges, one or more new numerical ranges may be found between the endpoints of each range, between the endpoint of each range and the individual point value, and between the individual point value, in combination with each other, and are to be considered as specifically disclosed herein.
The embodiment of the invention provides a laminated solid-state doping source structure, which is shown in fig. 1, and comprises a phosphorus doping source amorphous silicon layer 3, a front dielectric layer 2, a crystalline silicon substrate 1, a back dielectric layer 4 and a boron doping source amorphous silicon layer 5 which are sequentially laminated from front to back, wherein the crystalline silicon substrate 1 is of p type. The structure uses the laminated structure of the front dielectric layer and the doping source amorphous silicon layer as a phosphorus diffusion source, has good electrical and passivation properties, and can regulate and control the diffusion temperature to be matched with the annealing temperature of the back p-TOPCon structure, thereby realizing the preparation process of one-step annealing.
The above-mentioned double-sided source structure based on the laminated solid-state doping source is suitable for silicon wafers with different surface morphologies, including a suede, an alkali polished surface, an acid polished surface, etc., and the double-sided suede structure is shown in fig. 2, and comprises a phosphorus doping source amorphous silicon layer 3, a front dielectric layer 2, a crystalline silicon substrate 1, a back dielectric layer 4 and a boron doping source amorphous silicon layer 5 which are laminated in sequence from front to back.
In a specific embodiment, the phosphorus doping concentration of the phosphorus doping source amorphous silicon layer 3 is 1E19-1E21cm -3 Preferably 1E19-5E19cm -3 A thickness of 1-200nm, preferably 3-30nm; the boron doping concentration of the boron doping source amorphous silicon layer 5 is 1E17-5E20cm -3 Preferably 1E19-5E19cm -3 The thickness is 20-200nm, preferably 25-60nm.
Preferably, the doping atoms of the phosphorus doping source amorphous silicon layer 3 comprise one or more of carbon, nitrogen and oxygen besides phosphorus, and the doping concentration is 1E17-1E22 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping atoms of the boron doping source amorphous silicon layer 5 comprise one or more of carbon, nitrogen and oxygen besides boron, and the doping concentration is 1E17-1E22 cm -3 . C. N or O dopingThe annealing temperature can be adjusted to match the high temperature treatment temperature of the front and back surfaces, and the front and back structures have good passivation and electrical properties.
In a specific embodiment, the front dielectric layer 2 is selected from any one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film, preferably a silicon oxide film, and has a thickness of 1-5nm, preferably 1-3nm. The front dielectric layer 2 can avoid the contact between amorphous silicon and polycrystalline silicon and the substrate, thereby avoiding the crystal defects such as the stacking fault and the like caused by the epitaxial growth of the amorphous silicon during high-temperature annealing and obviously improving the passivation effect of the emitter; the presence of the front side dielectric layer 2 also enables adjustment of the surface concentration and diffusion depth of phosphorus, which provides room for improved emitter passivation and doping profile; in addition, the presence of the front side dielectric layer 2 has little effect on the emitter sheet resistance and junction depth.
In a specific embodiment, the back dielectric layer 4 is selected from any one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film, preferably a silicon oxide film, and has a thickness of 1-5nm, preferably 1-3nm. The backside dielectric layer 4 can improve the thermal stability of the p-TOPCon structure, so that it can be annealed at a higher temperature without causing structural damage, thereby enabling diffusion and crystallization in one high temperature step, and reducing the process steps.
The specific embodiment of the invention also provides a preparation method of the p-type TOPCon solar cell, the structure of the p-type TOPCon solar cell is shown in figure 3, the p-type TOPCon solar cell comprises a crystalline silicon substrate 1, a diffusion layer is arranged on the front surface of the crystalline silicon substrate 1 and used as an emitter 6, a passivation layer 8 and an anti-reflection layer 9 are sequentially arranged on the emitter 6, and a front metal electrode 10 is arranged on the anti-reflection layer 9; the front side of the crystalline silicon substrate 1 is sequentially provided with a back dielectric layer 4 and a back heavily doped polysilicon layer 7, and a back metal electrode 11 is arranged on the back heavily doped polysilicon layer 7.
Referring to fig. 4, the preparation method of the p-type TOPCon solar cell includes the following steps:
s1, preparing a front dielectric layer 2 on the front surface of a crystalline silicon substrate 1, wherein the front dielectric layer 2 is a silicon oxide film, a silicon nitride film, a silicon oxynitride film and the like, and the preparation method is selected from any one of PECVD, LPCVD, a wet chemical method, a high-temperature oxidation method, a plasma assisted atomic layer deposition method and the like.
S2, a layer of phosphorus doped source amorphous silicon layer 3 is deposited on the front medium layer 2 to serve as a phosphorus source, a CVD or PVD method, preferably PECVD, is adopted in the preparation method of the phosphorus doped source amorphous silicon layer 3, the phosphorus activation concentration is high, the deposition reaction gas is gas, and the deposition uniformity is high. The phosphorus doping source amorphous silicon layer 3 is doped with C, N or O, and the annealing temperature can be adjusted.
S3, preparing a back dielectric layer 4 on the back of the crystalline silicon substrate 1, wherein the back dielectric layer 4 is a silicon oxide film, a silicon nitride film, a silicon oxynitride film and the like, and the preparation method is selected from one of PECVD, LPCVD, a wet chemical method, a high-temperature oxidation method, a plasma assisted atomic layer deposition method and the like.
S4, depositing a boron doped source amorphous silicon layer 5 on the back dielectric layer 4, wherein the preparation method of the boron doped source amorphous silicon layer 5 adopts a CVD or PVD method, preferably PECVD, the boron doped source amorphous silicon layer 5 is doped with C, N or O, and the annealing temperature can be adjusted.
S5, performing one-step high-temperature annealing treatment to enable phosphorus on the front surface of the crystalline silicon substrate 1 to diffuse to form an emitter 6 and amorphous silicon on the back surface to crystallize, wherein the high-temperature annealing treatment temperature is 750-950 ℃, preferably 800-900 ℃ and the time is 10-200min. The front-side phosphorus emitter and the back-side p-TOPCon structure are prepared simultaneously by one-step high-temperature annealing, so that the process steps are reduced.
S6, etching the doping source amorphous silicon layer 3 and the front dielectric layer 2 on the front surface of the crystalline silicon substrate 1, wherein etching solution is selected from HF and HNO 3 、NH 4 F. One of KOH and NaOH.
S7, depositing a passivation layer 8 and an anti-reflection layer 9 on the emitter electrode 6, wherein the passivation layer 8 is preferably a silicon oxide film, the preparation method is preferably a thermal oxidation method, the anti-reflection layer 9 is preferably a silicon nitride film, and the preparation method is preferably PECVD.
And S8, carrying out front and back metallization treatment to form a front metal electrode 10 and a back metal electrode 11, wherein the electrode preparation method is selected from thermal evaporation deposition, electron beam deposition, screen printing and the like.
According to the preparation method, the front surface source layer structure and the back surface source layer structure are formed through continuous deposition, the phosphorus emitter and the p-TOPCON structure are prepared simultaneously through one-step high-temperature annealing, two originally inconsistent high-temperature treatment processes are combined, double-sided film coating is finally realized, the preparation process of one-step high-temperature annealing is realized, the process steps for preparing the p-type TOPCON solar cell are reduced, and the production efficiency is improved.
The present invention will be described in detail by way of specific examples.
Example 1
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, double-sided texturing and RCA cleaning.
The wafer was then subjected to nitric acid treatment at 110 ℃ for 10min to grow silicon oxide films of about 1.5nm on the front and back sides of the wafer.
And depositing a 5nm phosphorus-doped amorphous silicon layer on the silicon oxide films on the two sides of the silicon wafer by utilizing tubular PECVD.
And (5) carrying out high-temperature annealing treatment at 900 ℃ for 30min to form a pn junction.
And selectively etching the phosphorus source layer by adopting an HF system solution.
And after the etching is finished, passivating the surface by adopting silicon oxide and silicon nitride to obtain the double-sided emitter passivation sheet.
Example 2
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, double-sided texturing and RCA cleaning.
The wafer was then subjected to nitric acid treatment at 110 ℃ for 10min to grow silicon oxide films of about 1.5nm on the front and back sides of the wafer.
And depositing a 5nm phosphorus-doped amorphous silicon layer on the silicon oxide films on the two sides of the silicon wafer by utilizing tubular PECVD.
And carrying out high-temperature annealing treatment at 920 ℃ for 120min to form a pn junction.
And selectively etching the phosphorus source layer by adopting an HF system solution.
And after the etching is finished, passivating the surface by adopting silicon oxide and silicon nitride to obtain the double-sided emitter passivation sheet.
Example 3
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, double-sided texturing and RCA cleaning.
The wafer was then subjected to nitric acid treatment at 110 ℃ for 10min to grow silicon oxide films of about 1.5nm on the front and back sides of the wafer.
And depositing a 5nm phosphorus-doped amorphous silicon layer on the silicon oxide films on the two sides of the silicon wafer by utilizing tubular PECVD.
And (5) performing high-temperature annealing treatment at 840 ℃ for 30min to form a pn junction.
And selectively etching the phosphorus source layer by adopting an HF system solution.
And after the etching is finished, passivating the surface by adopting silicon oxide and silicon nitride to obtain the double-sided emitter passivation sheet.
Comparative example 1
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, double-sided texturing and RCA cleaning.
And (5) depositing a 5nm phosphorus-doped amorphous silicon layer on two sides of the silicon wafer by utilizing tubular PECVD.
And (5) carrying out high-temperature annealing treatment at 900 ℃ for 30min to form a pn junction.
And selectively etching the phosphorus source layer by adopting an HF system solution.
And after the etching is finished, passivating the surface by adopting silicon oxide and silicon nitride to obtain the double-sided emitter passivation sheet.
Test examples 1-3 and comparative example 1 passivation sheets were tested for emitter sheet resistance, junction depth, current density (J 0,s ) And minority carrier lifetime, and the results are shown in table 1 below. The result shows that the silicon oxide film is arranged between the phosphorus-doped amorphous silicon layer and the crystalline silicon substrate, so that the passivation effect can be remarkably improved, and the battery efficiency can be improved.
TABLE 1 key parameters of emitter passivation sheet
| Parameters (parameters) | Sheet resistance | Junction depth | J 0,s | Minority carrier lifetime |
| Example 1 | 130Ohm/Sq | 0.37μm | 18fA/cm 2 | 743μs |
| Example 2 | 52Ohm/Sq | 0.72μm | 26fA/cm 2 | 480μs |
| Example 3 | 262Ohm/Sq | 0.26μm | 12fA/cm 2 | 996μs |
| Comparative example 1 | 125Ohm/Sq | 0.38μm | 30fA/cm 2 | 398μs |
Example 4
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, front-side texturing, back-side alkali polishing and RCA cleaning.
The silicon wafer is placed in 110 ℃ nitric acid for 10min, and a silicon oxide film with the thickness of about 1.5nm is grown on the front surface of the silicon wafer.
And depositing a 5nm phosphorus-doped amorphous silicon layer serving as a phosphorus source layer on the silicon oxide film on the front side of the silicon wafer by utilizing tubular PECVD.
And depositing a 1.5nm laughing gas silicon oxide layer and a 30nm nitrogen doped boron doped amorphous silicon layer on the back surface of the silicon wafer by utilizing tubular PECVD.
And performing high-temperature annealing treatment at 820-920 ℃ for 30min, and simultaneously forming a p-TOPCon structure of the phosphorus emitter and the back surface.
Using HF/HNO 3 And selectively etching the front phosphorus source layer.
And after etching is finished, passivating the front surface by adopting silicon oxide and silicon nitride to obtain the quasi-p-TOPCO solar cell.
Testing passivation effect of the p-TOPCON solar cell iV ℃ The minority carrier lifetime is between 715 and 720mV, and between 2000 and 2700 mu s.
Example 5
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, front-side texturing, back-side alkali polishing and RCA cleaning.
The silicon wafer is placed in 110 ℃ nitric acid for 10min, and a silicon oxide film with the thickness of about 1.5nm is grown on the front surface of the silicon wafer.
And depositing a 5nm phosphorus-doped amorphous silicon layer on the silicon oxide film on the front side of the silicon wafer by utilizing tubular PECVD.
And depositing a 1.5nm laughing gas silicon oxide layer and a 30nm nitrogen doped boron doped amorphous silicon layer on the back surface of the silicon wafer by utilizing tubular PECVD.
And (3) carrying out high-temperature annealing treatment at 900 ℃ for 30min, and simultaneously forming a p-TOPCon structure of the phosphorus emitter and the back surface.
Using HF/HNO 3 And selectively etching the front phosphorus source layer.
And after etching is finished, passivating the front surface by adopting silicon oxide and silicon nitride.
And preparing a front fine grid by utilizing electron beam deposition, thermally evaporating and depositing a front wide grid, and thermally evaporating a silver electrode on the back to prepare the p-type TOPCO solar cell.
Example 6
Taking a p-type silicon wafer as a crystal silicon substrate, cleaning, front-side texturing, back-side alkali polishing and RCA cleaning.
The silicon wafer is placed in 110 ℃ nitric acid for 10min, and a silicon oxide film with the thickness of about 1.5nm is grown on the front surface of the silicon wafer.
And depositing a 5nm phosphorus-doped amorphous silicon layer on the silicon oxide film on the front side of the silicon wafer by utilizing tubular PECVD.
And depositing a 1.5nm laughing gas silicon oxide layer and a 30nm nitrogen doped boron doped amorphous silicon layer on the back surface of the silicon wafer by utilizing tubular PECVD.
And (3) carrying out high-temperature annealing treatment at 860 ℃ for 30min, and simultaneously forming a p-TOPCon structure of the phosphorus emitter and the back surface.
Using HF/HNO 3 And selectively etching the front phosphorus source layer.
And after etching is finished, passivating the front surface by adopting silicon oxide and silicon nitride.
And preparing a front fine grid by utilizing electron beam deposition, thermally evaporating and depositing a front wide grid, and thermally evaporating a silver electrode on the back to prepare the p-type TOPCO solar cell.
The p-type TOPCON solar cells of examples 5-6 were tested for open circuit voltage (V ℃ ) Short-circuit current (J) sc ) The Fill Factor (FF) and the conversion efficiency (PCE), the results are shown in table 2 below. The result shows that the TOPCon solar cell prepared by the method has good performance, and the conversion efficiency reaches more than 24%.
Table 2 key parameters of TOPCon solar cells
| Test parameters | V ℃ | J sc | FF | PCE |
| Example 5 | 698mV | 41.5mA/cm 2 | 83.2％ | 24.1％ |
| Example 6 | 705mV | 41.6mA/cm 2 | 83.8％ | 24.6％ |
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. The laminated solid-state doping source structure is characterized by comprising a phosphorus doping source amorphous silicon layer, a front dielectric layer, a crystalline silicon substrate, a back dielectric layer and a boron doping source amorphous silicon layer which are laminated.
2. The stacked solid state dopant source structure of claim 1, wherein the dopant atoms of the phosphorus dopant source amorphous silicon layer comprise one or more of carbon, nitrogen, and oxygen in addition to phosphorus, the dopant concentration being 1E17-1E22 cm -3 。
3. The stacked solid state dopant source structure of claim 1, wherein the dopant atoms of the boron dopant source amorphous silicon layer comprise one or more of carbon, nitrogen, and oxygen in addition to boron, the dopant concentration being 1E17-1E22 cm -3 。
4. The stacked solid state dopant source structure of claim 1, wherein the phosphorus dopant source amorphous silicon layer has a phosphorus dopant concentration of 1E19-1E21cm -3 The boron doping concentration of the boron doping source amorphous silicon layer is 1E17-5E20cm -3 。
5. The stacked solid state dopant source structure of claim 1, wherein the front side dielectric layer is selected from any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the back side dielectric layer is selected from any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film.
6. The stacked solid state dopant source structure of any one of claims 1-5, wherein the thickness of the phosphorus dopant source amorphous silicon layer is between 2-200nm, the thickness of the front side dielectric layer is between 1-5nm, the thickness of the back side dielectric layer is between 1-5nm, and the thickness of the boron dopant source amorphous silicon layer is between 20-200nm.
7. The preparation method of the p-type TOPCON solar cell is characterized by comprising the following steps of:
s1, preparing a front dielectric layer on the front side of a crystalline silicon substrate;
s2, depositing a phosphorus doping source amorphous silicon layer serving as a phosphorus source on the front dielectric layer;
s3, preparing a back medium layer on the back of the crystalline silicon substrate;
s4, depositing a boron doping source amorphous silicon layer on the back dielectric layer to serve as a boron source;
s5, performing one-step high-temperature annealing treatment to enable phosphorus on the front surface of the crystalline silicon substrate to diffuse to form an emitter and amorphous silicon on the back surface to crystallize;
s6, etching the phosphorus doping source amorphous silicon layer and the front dielectric layer on the front side of the crystalline silicon substrate;
s7, depositing a passivation layer and an anti-reflection layer on the front surface and/or the back surface;
and S8, carrying out front-side and back-side metallization treatment to obtain the p-type TOPCO solar cell.
8. The method for fabricating the p-type TOPCon solar cell according to claim 7, wherein the step S2 and the step S4 are performed by depositing the phosphorus doped source amorphous silicon layer and the boron doped source amorphous silicon layer by CVD or PVD.
9. The method for manufacturing a p-type TOPCon solar cell according to claim 7, wherein the high temperature annealing treatment temperature in step S4 is 750-1000 ℃.
10. The method for preparing the p-type TOPCon solar cell according to claim 7, wherein in the step S1 and the step S3, the preparation method of the front-side dielectric layer and the back-side dielectric layer is selected from any one of the following: PECVD, LPCVD, wet chemical, high temperature oxidation, plasma assisted oxidation, and plasma assisted atomic layer deposition.
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