CN116207106A

CN116207106A - Display panel and display device

Info

Publication number: CN116207106A
Application number: CN202310100334.5A
Authority: CN
Inventors: 杨魏强
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2023-02-06
Filing date: 2023-02-06
Publication date: 2023-06-02

Abstract

The invention discloses a display panel and a display device. The display panel includes: the display area and the non-display area, a plurality of data wires, a plurality of connecting wires and a plurality of signal wires, wherein the connecting wires are respectively and electrically connected with the data wires and the signal wires; the data wire and the connecting wiring are positioned in the display area, and the signal wiring is positioned in the non-display area; the display area comprises a display area comprising a first display area, wherein the first display area comprises a first light emitting element setting area, a first pixel circuit setting area and a first pixel driving circuit setting area; the first light emitting element setting region overlaps the first pixel circuit setting region and overlaps the first pixel driving circuit setting region in a thickness direction of the display panel; part of the first pixel circuits are electrically connected with the first light-emitting element through signal transmission wires, and at least part of the signal transmission wires and the connection wires are arranged on the same layer. The narrow frame effect of the display panel is improved, meanwhile, the layout difficulty of the signal transmission wiring can be reduced, and the preparation process of the signal transmission wiring is simplified.

Description

Display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.

Background

In electronic devices including display panels, the pursuit of a high screen ratio with a better visual experience has become one of the current trends in display technology development. In the prior art, a pixel driving control circuit for providing driving control signals for sub-pixels in a display area is generally arranged in a frame area of a display panel, and in such a setting mode, the pixel driving control circuit occupies a larger frame area, which is not beneficial to realizing a narrow frame of the display panel.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device, which reduce the size of the frame area of the display panel, and realize the narrow frame of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel, including a display area and a non-display area;

the display panel further comprises a plurality of data lines, a plurality of connecting wires and a plurality of signal wires, wherein the connecting wires are respectively and electrically connected with the data lines and the signal wires; the data line and the connecting wiring are positioned in the display area, and the signal wiring is positioned in the non-display area;

the display area comprises a first display area, the first display area comprises a first light emitting element setting area, a first pixel circuit setting area and a first pixel driving circuit setting area, the first light emitting element setting area is provided with a plurality of first light emitting elements, the first pixel circuit setting area is provided with a plurality of first pixel circuits, the first pixel driving circuit setting area is provided with a first pixel driving circuit, and the first pixel circuits are respectively electrically connected with the first pixel driving circuit and the first light emitting elements; the first light emitting element setting region overlaps the first pixel circuit setting region and overlaps the first pixel driving circuit setting region in a thickness direction of the display panel;

Part of the first pixel circuits are electrically connected with the first light-emitting element through signal transmission wires, and at least part of the signal transmission wires and the connection wires are arranged on the same layer.

In a second aspect, an embodiment of the present invention provides a display device, including the display panel according to the first aspect of the present invention.

Through the technical scheme that this application embodiment provided, through setting up the connection wiring in the display area for signal wiring occupies the area in non-display area less, can reduce display panel's lower frame size. Meanwhile, the first pixel driving circuit setting areas of the first light emitting element setting areas are overlapped, namely, the first pixel driving circuits are arranged in the display areas, so that the number of the pixel driving circuits arranged in the left and right non-display areas of the display panel can be reduced, the size of the left and right frames of the display panel is further reduced, and the narrow frame effect of the display panel is improved. In addition, through setting up partial first pixel circuit and being connected with first light emitting component electricity through signal transmission wiring, at least partial signal transmission wiring and connection wiring are same layer, can guarantee that first light emitting component normally receives the drive signal of first pixel circuit transmission, can also reduce the laying degree of difficulty of signal transmission wiring, simplify the preparation technology of signal transmission wiring.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is an enlarged schematic view of FIG. 1 at A;

FIG. 3 is an enlarged schematic view of FIG. 2 at B;

FIG. 4 is a schematic cross-sectional view of FIG. 1 along the direction C-C';

FIG. 5 is an enlarged schematic view of FIG. 1 at D;

FIG. 6 is a schematic cross-sectional view of FIG. 5 along E-E';

fig. 7 is a schematic diagram of a partial enlarged structure of a display panel according to an embodiment of the invention;

FIG. 8 is a schematic diagram of a partial enlarged structure of another display panel according to an embodiment of the present invention;

FIG. 9 is a schematic view of a partially enlarged structure of a display panel according to another embodiment of the present invention;

fig. 10 is a schematic view of a partial enlarged structure of a display panel according to still another embodiment of the present invention;

FIG. 11 is a schematic view of a partially enlarged structure of a display panel according to another embodiment of the present invention;

fig. 12 is a schematic view of a partial cross-sectional structure of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural view of a display panel according to an embodiment of the present invention, fig. 2 is an enlarged structural view at a of fig. 1, fig. 3 is an enlarged structural view at B of fig. 2, fig. 4 is a schematic structural view of a cross section of fig. 1 along a direction C-C', and referring to fig. 1 to fig. 4, in an embodiment of the present invention, the display panel includes: a display area AA and a non-display area NA; the display panel also comprises a plurality of data lines 1, a plurality of connecting wires 2 and a plurality of signal wires 3, wherein the connecting wires 2 are respectively and electrically connected with the data lines 1 and the signal wires 3; the data line 1 and the connecting wiring 2 are positioned in the display area AA, and the signal wiring 3 is positioned in the non-display area NA; the display area AA includes a first display area AA1, the first display area AA1 includes a first light emitting element setting area 4, a first pixel circuit setting area 5, and a first pixel driving circuit setting area 6, the first light emitting element setting area 4 is provided with a plurality of first light emitting elements 7, the first pixel circuit setting area 5 is provided with a plurality of first pixel circuits 8, the first pixel driving circuit setting area 6 is provided with a first pixel driving circuit 9, and the first pixel circuits 8 are electrically connected with the first pixel driving circuit 9 and the first light emitting elements 7, respectively; the first light emitting element setting region 4 overlaps the first pixel circuit setting region 5 and overlaps the first pixel driving circuit setting region 6 in the thickness direction Z of the display panel; part of the first pixel circuits 8 are electrically connected with the first light emitting elements 7 through signal transmission wires 10, and at least part of the signal transmission wires 10 are arranged on the same layer as the connection wires 2.

Referring to fig. 1 to 4, a plurality of data lines 1 and a plurality of connection wirings 2 are provided in a display area AA of the display panel, and a plurality of signal wirings 3 are provided in a non-display area NA of the display panel. The data lines 1 are used to supply data signals to the light emitting elements of the display area AA, and the data lines 1 are arranged in the first direction X and extend in the second direction Y in the display area AA. The first direction X may be a row direction as shown in the figure and the second direction Y may be a column direction as shown in the figure. The signal wiring 3 is a fan-out wiring for connecting each data line 1 with a driving module (not shown in the figure).

The connection trace 2 is implemented by adopting a FIAA (fanout trace located in the display area) technology. In FIAA technology, a multi-layer connection trace design is introduced to extrude routing space for fan-out traces. As shown in fig. 1, a part of the data lines 1 are connected to the signal wiring 3 through the connection trace 2 in the display area AA by using the FIAA technology, so that the area of the signal wiring 3 occupying the non-display area NA is small. The signal wiring 3 shown in fig. 1 is provided in the non-display area NA below the display panel, and the actual arrangement is not limited thereto, and in this arrangement, the size of the lower frame of the display panel can be reduced. The number of the metal wirings (the data line 1, the connection wiring 2, the signal wiring 3, and the like) shown in the embodiment of the present application is merely an example, and does not represent an actual situation.

Further, the display area AA further includes a first display area AA1, and the first display area AA1 can be further divided into a first light emitting element setting area 4, a first pixel circuit setting area 5, and a first pixel driving circuit setting area 6. The first Light Emitting element arrangement region 4 is used to arrange a plurality of first Light Emitting elements 7, and the first Light Emitting elements 7 may be Organic Light-Emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs (Quantum Dot Light Emitting Diodes, QLEDs), or the like. The first light emitting element 7 may include a red light emitting element R, a green light emitting element G, and a blue light emitting element B, and an arrangement between the red light emitting element R, the green light emitting element G, and the blue light emitting element B is exemplarily shown in fig. 3 as a diamond Pixel (Dimond Pixel) arrangement, and the actual arrangement is not limited thereto. In other not shown embodiments, the red light emitting element R, the green light emitting element G, and the blue light emitting element B may be arranged in a standard RGB arrangement, a Delta Pixel (Delta Pixel) arrangement, a Pearl Pixel (Pearl Pixel) arrangement, a two-in-one Pixel (2 in1 Pixel)) arrangement, or the like, but is not limited thereto. In the embodiments of the present application, the arrangement of diamond pixels is described.

The first pixel circuit setting area 5 is used for setting a plurality of first pixel circuits 8, and the first pixel circuits 8 may be 2T1C circuits, 7T2C circuits, or the like. "2T1C circuit" means a pixel circuit including 2 thin film transistors (T) and 1 capacitor (C), other "7T1C circuits", "7T2C circuits", and the like. The first pixel driving circuit setting area 6 is used for setting the first pixel driving circuit 9, the first pixel driving circuit 9 may also include a thin film transistor and a capacitor, and the number of the thin film transistors and the capacitors in the first pixel driving circuit 9 may be set by those skilled in the art according to actual needs, which is not described in detail and is not limited in the embodiment of the present invention.

The first pixel circuit 8 is electrically connected to the first light emitting element 7, so as to provide a driving signal to the first light emitting element 7, and further drive the first light emitting element 7 to emit light. It will be appreciated that in general, the first pixel circuits 8 and the first light emitting elements 7 are in one-to-one correspondence, and each first light emitting element 7 is driven by a corresponding first pixel circuit 8. The first pixel circuit 8 may be electrically connected to an anode of the first light emitting element 7 to transmit a driving signal to the first light emitting element 7, for example. The circular first light emitting element 7 shown in the figure may represent the anode of the first light emitting element 7.

The first pixel driving circuit 9 is electrically connected to the first pixel circuit 8 to supply a driving control signal to the first pixel circuit 8, and the first pixel circuit 8 generates a driving signal under the control of the driving control signal and transmits the driving signal to the first light emitting element 7. The first pixel driving circuit 9 may be electrically connected to the first pixel circuit 8 through a driving control signal line (not shown), and the driving control signal is transmitted to the first pixel circuit 8 through the driving control signal line.

The pixel driving circuits are disposed in the non-display area NA on the left and right sides of the display panel. In this embodiment, the number of pixel driving circuits disposed in the left and right non-display areas NA of the display panel can be reduced by disposing the first pixel driving circuit 9 in the first display area AA1, so as to reduce the size of the left and right frames of the display panel.

Wherein the first light emitting element setting region 4 and the first pixel circuit setting region 5 overlap in the display panel thickness direction Z, and the first light emitting element setting region 4 and the first pixel driving circuit setting region 6 overlap in the display panel thickness direction Z. It is also understood that at least part of the orthographic projection of the first pixel circuit 8 on the film layer where the first light emitting element 7 is located in the first light emitting element placement area 4; likewise, at least part of the orthographic projection of the first pixel driving circuit 9 on the film layer where the first light emitting element 7 is located in the first light emitting element setting region 4.

In this embodiment, the first pixel circuit 8 and the first pixel driving circuit 9 may be located on the same film layer, so as to reduce the number of film layers of the display panel and reduce the thickness of the display panel. When the first pixel circuit 8 and the first pixel driving circuit 9 are located in the same film layer, the projections of the first pixel circuit arrangement region 5 and the first pixel driving circuit arrangement region 6 in the display panel thickness direction Z do not overlap. In other embodiments, the first pixel circuit 8 and the first pixel driving circuit 9 may be located in different layers.

It can be understood that, in the related art, the display area AA of the display panel is not provided with the pixel driving circuit, and the area of the pixel circuit setting area is larger; at this time, a pixel circuit arrangement region may be arranged to coincide with a projection of the light emitting element arrangement region in the thickness direction Z of the display panel, each light emitting element is driven by a pixel circuit partially overlapping therewith, and both may be electrically connected directly through a via hole between the film layers. In this application, as shown in fig. 1 to 4, since the first pixel driving circuit 9 occupies a part of the position originally belonging to the first pixel circuit 8, the entire size of the first pixel circuit arrangement region 5 is compressed to some extent. The first pixel driving circuit 9 occupies a region below a portion of the first light emitting element 7 (which may define that a direction in which the film layer where the first light emitting element 7 is located points to the film layer where the first pixel circuit 8 is located is a top-down direction), a distance between the portion of the first light emitting element 7 and the first pixel circuit 8 for driving the portion of the first light emitting element 7 increases, and a difficulty in directly and electrically connecting the two through the via hole increases. For the above reasons, the display panel provided in the present application is further provided with a signal transmission trace 10, where the signal transmission trace 10 is used to electrically connect a portion of the first light emitting element 7 and a portion of the first pixel circuit 8. Part of the first pixel circuits 8 transmit driving signals to the corresponding first light emitting elements 7 through the signal transmission wiring 10, so as to ensure that the part of the first light emitting elements 7, which are overlapped with the first pixel driving circuits 9 and are not overlapped with the first pixel circuits 8, normally receives the driving signals. The first pixel driving circuit 9 is not shown in fig. 3 for clarity of illustration of the arrangement of the signal transmission trace 10. In fig. 3, rectangular black dots indicate the holes at different layers when the signal transmission line 10 is electrically connected to the first pixel circuit 8, and circular black dots indicate the holes at different layers when the signal transmission line 10 is electrically connected to the first light emitting element 7.

Note that, in fig. 4, only a portion of the first light emitting element 7 overlapping with the projection of the first pixel drive circuit arrangement region 6 is exemplarily shown, and the first light emitting element 7 overlapping with the projection of the first pixel circuit arrangement region 5 is not shown.

In addition, as shown in fig. 4, at least a part of the signal transmission wires 10 and the connection wires 2 are arranged on the same layer, so that at least a part of the signal transmission wires 10 and the connection wires 2 can be prepared by the same layer of metal through the same etching process, no additional preparation process is added, and the thickness of the display panel is not increased. In addition, the connection trace 2 is generally disposed in a different layer from the electronic components (such as a thin film transistor and/or a capacitor) in the first pixel driving circuit 9 or the first pixel circuit 8, that is, the signal transmission trace 10 disposed in the same layer as the connection trace 2 and the electronic components in the first pixel driving circuit 9 are disposed in different film layers, and the signal transmission trace 10 does not occupy the position of the electronic components or the traces in the original first pixel driving circuit 9, which is beneficial to reducing the difficulty in preparing the signal transmission trace 10. The first pixel driving circuit 9 or the first pixel circuit 8 shown in fig. 4 is a corresponding electronic component structure.

Since the overall size of the first pixel circuit arrangement area 5 is compressed, but the number of the first pixel circuits 8 accommodated therein is not changed, it is necessary to adaptively reduce the projection size of each first pixel circuit 8 in the display panel thickness direction Z, that is, the occupied area of the first pixel circuit 8 in the first display area AA 1. The embodiment of the present invention is not limited to a specific way of reducing the size of the first pixel circuit 8, and those skilled in the art can design the first pixel circuit according to actual requirements. For example, the number of electronic components in the first pixel circuit 8, the size of the electronic components, the distance between the electronic components, or the driving manner of the first light emitting element 7 may be reduced, but is not limited thereto.

Alternatively, the embodiment of the present invention is not limited to the specific form of the signal transmission line 10, and the signal transmission line 10 is exemplarily shown in fig. 3 as a straight line, but is not limited thereto, and may be a curve, a broken line, or the like, which may be set by those skilled in the art according to actual needs.

In this application, the display panel includes: a display area and a non-display area; the display panel also comprises a plurality of data lines, a plurality of connecting wires and a plurality of signal wires, wherein the connecting wires are respectively and electrically connected with the data lines and the signal wires; the data line and the connecting wiring are positioned in the display area, and the signal wiring is positioned in the non-display area. Thus, the signal wiring occupies a smaller area of the non-display area, and the lower frame size of the display panel can be reduced. In addition, the display area comprises a first display area, the first display area comprises a first light emitting element setting area, a first pixel circuit setting area and a first pixel driving circuit setting area, the first light emitting element setting area is provided with a plurality of first light emitting elements, the first pixel circuit setting area is provided with a plurality of first pixel circuits, the first pixel driving circuit setting area is provided with a first pixel driving circuit, and the first pixel circuits are respectively and electrically connected with the first pixel driving circuit and the first light emitting elements; the first light emitting element setting region overlaps the first pixel circuit setting region and overlaps the first pixel driving circuit setting region in a thickness direction of the display panel. The first pixel driving circuits are arranged in the first display area, so that the number of the pixel driving circuits arranged in the left and right non-display areas of the display panel can be reduced, and the size of the left and right frames of the display panel can be further reduced. In addition, the application further provides that a part of the first pixel circuits are electrically connected with the first light emitting element through signal transmission wires, and at least a part of the signal transmission wires and the connection wires are arranged in the same layer. By adopting the scheme, the first light-emitting element can be ensured to normally receive the driving signal transmitted by the first pixel circuit, the layout difficulty of the signal transmission wiring can be reduced, and the preparation process of the signal transmission wiring is simplified.

Alternatively, with continued reference to fig. 1 and 2, in a possible embodiment, the first display area AA1 may include two first pixel circuit arrangement areas 5; the first pixel driving circuit arrangement region 6 is located between two first pixel circuit arrangement regions 5.

Specifically, in the present application, two first pixel circuit arrangement regions 5 may be disposed in the first display region AA1, and the two first pixel circuit arrangement regions 5 are located at both sides of the first pixel driving circuit arrangement region 6 along the first direction X. In this way, the first pixel driving circuit 9 can be electrically connected to the first pixel circuits 8 on both sides thereof at the same time, so as to drive the first pixel circuits 8 on both sides at the same time. When the first pixel driving circuit 9 transmits the driving control signals to the first pixel circuits 8 on both sides at the same time, the voltage drops of the driving control signals transmitted on the driving control signal lines are the same or similar, and are smaller, which is beneficial to improving the overall brightness uniformity of the first light emitting element 7.

Of course, in other embodiments not shown, only one first pixel circuit arrangement area 5 may be disposed in the first display area AA1, and the first pixel driving circuit arrangement area 6 is located at one side of the first pixel circuit arrangement area 5. In this arrangement, the first pixel circuit 8 may be located at one side of the first display area AA1 along the first direction X, and the first pixel driving circuit 9 may be located at the other side of the first display area AA1 along the first direction X, which is beneficial to reducing the difficulty in setting the first pixel circuit 8 and the first pixel driving circuit 9. In the embodiment of the present application, the first display area AA1 includes two first pixel circuit arrangement areas 5 as an example.

Optionally, fig. 5 is an enlarged schematic structural view of fig. 1 at D, fig. 6 is a schematic structural view of fig. 5 in a cross-section along the direction of E-E', and referring to fig. 1, fig. 5 and fig. 6, in a possible embodiment, the display area AA may further include a second display area AA2, where the second display area AA2 includes a second light emitting element setting area 11 and a second pixel circuit setting area 12, the second light emitting element setting area 11 is provided with a plurality of second light emitting elements 13, the second pixel circuit setting area 12 is provided with a plurality of second pixel circuits 14, and the second pixel circuits 14 are electrically connected to the first pixel driving circuit 9 and the second light emitting elements 13, respectively; and the second light emitting element setting region 11 overlaps the second pixel circuit setting region 12 in the thickness direction Z of the display panel; the second display area AA2 is located at a side of the first pixel circuit arrangement area 5 remote from the first pixel driving circuit arrangement area 6.

Specifically, as shown in fig. 1, 2 and 6, a second display area AA2 is further disposed in the display area AA, and the second display area AA2 may be further divided into a second Light Emitting element disposition area 11 and a second pixel circuit disposition area 12, where the second Light Emitting element disposition area 11 is used to dispose a plurality of second Light Emitting elements 13, and the second Light Emitting elements 13 may be Organic Light-Emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot Light Emitting diodes (Quantum Dot Light Emitting Diodes, QLEDs), and the like. The second pixel circuit setting area 12 is used for setting a plurality of second pixel circuits 14, and the second pixel circuits 14 may be 2T1C circuits, 7T2C circuits, or the like. "2T1C circuit" means a pixel circuit including 2 thin film transistors (T) and 1 capacitor (C), other "7T1C circuits", "7T2C circuits", and the like.

The second pixel circuit 14 is electrically connected to the second light emitting element 13, so as to provide a driving signal to the second light emitting element 13, and further drive the second light emitting element 13 to emit light. It will be appreciated that in general, the second pixel circuits 14 are in one-to-one correspondence with the second light emitting elements 13, and each second light emitting element 13 is driven by a corresponding second pixel circuit 14. The second pixel circuit 14 may be electrically connected to an anode of the second light emitting element 13 to transmit a driving signal to the second light emitting element 13, for example.

With continued reference to fig. 1, 5 and 6, unlike the first display area AA1, the pixel driving circuit is not required to be provided in the second display area AA2, and thus the size of the second pixel circuit 14 within the second pixel circuit-providing area 12 is not required to be compressed. The second light emitting element arrangement region 11 and the second pixel circuit arrangement region 12 may overlap in the display panel thickness direction Z, each of the second light emitting elements 13 may be driven by the second pixel circuit 14 partially overlapping therewith, and both may be electrically connected directly through the via hole b between the film layers. Meanwhile, the second pixel circuit 14 is still electrically connected to the first pixel driving circuit 9 (not shown in the figure), and receives the driving control signal output from the first pixel driving circuit 9.

The second pixel circuit arrangement area 12 may be arranged on a side of the first pixel circuit arrangement area 5 facing away from the first pixel driving circuit 9, i.e. the second pixel circuit 14 is closer to the frame area of the display panel than the first pixel circuit 8. For example, when the number of the first pixel circuit arrangement regions 5 is 2, the number of the second pixel circuits 14 may be 2, and at this time, the second pixel circuit arrangement region 12, the first pixel circuit arrangement region 5, the first pixel driving circuit arrangement region 6, the first pixel circuit arrangement region 5, and the second pixel circuit arrangement region 12 are sequentially arranged in the first direction X.

In this embodiment, only the design manner of the first pixel circuit 8 in the first display area AA1 is improved, and the second pixel circuit 14 in the second display area AA2 is still designed by adopting the existing scheme, so that the overall manufacturing process of the display panel is simplified.

Alternatively, referring to fig. 4 and 6 in combination, the first pixel circuit 8 includes at least two first electronic components 15, and the at least two first electronic components 15 include at least one first transistor T1 and at least one first storage capacitor C1; the second pixel circuit 14 comprises at least two second electronic components 16, the at least two second electronic components 16 comprising at least one second transistor T2 and at least one second storage capacitor C2; the channel width-to-length ratio of the at least one first transistor T1 is smaller than the channel width-to-length ratio of the second transistor T2, the area of the at least one first storage capacitor C1 is smaller than the area of the second storage capacitor C2, and/or the distance between two adjacent first electronic components 15 is smaller than the distance between two adjacent second electronic components 16 along the first direction X; the first direction X is the same as the arrangement direction of the plurality of data lines 1.

The first pixel circuit 8 may be formed by at least two first electronic components 15, where the at least two first electronic components 15 are at least one first transistor T1 and at least one first storage capacitor C1, respectively, and the first transistor T1 is the thin film transistor mentioned above. Accordingly, the second pixel circuit 14 may be formed by at least two second electronic components 16, and the at least two second electronic components 16 are respectively formed by at least one second transistor T2 and at least one second storage capacitor C2.

Referring to fig. 1, since the first driving pixel circuit arrangement region is located at a central region in the first direction X in the first display region AA1, the size of the first pixel circuit arrangement region 5 as a whole is compressed in the first direction X. Therefore, in the present embodiment, the compression of the area of the first pixel circuit arrangement region 5 can be achieved by reducing the size of the first electronic component 15 in the first pixel circuit 8 in the first direction X, and/or the distance between two first electronic components 15 adjacent in the first direction X.

Specifically, in general, the channel of the transistor has a dimension along the first direction X that is the width of the channel and a dimension along the second direction Y that is the length of the channel, and therefore, in order to reduce the dimension of the first electronic element 15 along the first direction X, the channel width-to-length ratio of the first transistor T1 can be appropriately reduced; in addition, the product of the dimensions of the storage capacitor along the first direction X and/or the second direction Y is the area of the storage capacitor, so in order to reduce the dimension of the first electronic component 15 along the first direction X, the area of the first storage capacitor C1 may be also reduced appropriately. It will be appreciated that the size of the second pixel circuit arrangement area 12 need not be compressed and the size of the second electronic component 16 need not be reduced. Therefore, the channel width-to-length ratio of the second transistor T2 is slightly larger than that of the first transistor T1, and the area of the second storage capacitor C2 is slightly larger than that of the first storage capacitor C1.

Accordingly, the distance between two adjacent second electronic components 16 along the first direction X does not need to be reduced, and if the distance between two adjacent first electronic components 15 along the first direction X is reduced appropriately, the distance between two adjacent second electronic components 16 along the first direction X will be slightly larger than the distance between two adjacent first electronic components 15 along the first direction X.

With the arrangement in this example, the difference in luminance between the first light emitting element 7 and the second light emitting element 13 is not caused, and the display uniformity is good, with respect to the case where the first pixel circuit arrangement region 5 is compressed by reducing the number of the first electronic elements 15 in the first pixel circuit 8 (for example, changing from a 7T1C circuit to a 2T1C circuit). Compared with the mode of changing the driving mode of the first light emitting elements 7 (for example, driving one first light emitting element 7 from one first pixel circuit 8 to drive at least two first light emitting elements 7), the first pixel circuit setting area 5 is compressed, and the scheme in the example is adopted, so that PPI is not reduced, no driving control line is additionally added in the circuit, and the process difficulty can be reduced.

Alternatively, fig. 7 is a schematic view of a partial enlarged structure of a display panel according to an embodiment of the present invention, and referring to fig. 3 and 7 in combination, in a possible embodiment, the first pixel circuit arrangement area 5 includes a plurality of first sub-pixel circuit arrangement areas 17 and a plurality of second sub-pixel circuit arrangement areas 18, where the first sub-pixel circuit arrangement areas 17 are provided with first sub-pixel circuits 24, and the second sub-pixel circuit arrangement areas 18 are provided with second sub-pixel circuits 19; the first light-emitting element 7 region includes a first sub-light-emitting element arrangement region 20 and a second sub-light-emitting element arrangement region 21, the first sub-light-emitting element arrangement region 20 being provided with a first sub-light-emitting element 22, the second sub-light-emitting element arrangement region 21 being provided with a second sub-light-emitting element 23; the first sub-pixel circuit 24 is directly electrically connected with the first sub-light emitting element 22 or the first sub-pixel circuit 24 is electrically connected with the first sub-light emitting element 22 through the first signal transmission trace 101, the second sub-pixel circuit 19 is electrically connected with the second sub-light emitting element 23 through the second signal transmission trace 102, and the length of the second signal transmission trace 102 is longer than that of the first signal transmission trace 101.

Specifically, as shown in fig. 3 and 7, in the present embodiment, the first pixel circuit arrangement region 5 may be further divided into a plurality of first sub-pixel circuit arrangement regions 17 and a plurality of second sub-pixel circuit arrangement regions 18. The first sub-pixel circuit setting area 17 is used for setting the first sub-pixel circuit 24, and the second sub-pixel circuit setting area 18 is used for setting the second sub-pixel circuit 19. Accordingly, the first light emitting element arrangement region 4 may be divided into a first sub light emitting element arrangement region 20 and a second sub light emitting element arrangement region 21. The first sub-light emitting element setting region 20 is for setting a plurality of first sub-light emitting elements 22, and the second sub-light emitting element setting region 21 is for setting a plurality of second sub-light emitting elements 23. The first sub-pixel circuit 24 drives and controls the first sub-light emitting element 22 to emit light, and the second sub-pixel circuit 19 drives and controls the second sub-light emitting element 23 to emit light.

Wherein, along the thickness direction Z of the display panel, the first sub light emitting element setting region 20 may overlap the first pixel driving circuit setting region 6, and the second sub light emitting element setting region 21 may overlap the first pixel driving circuit setting region 6. Referring to fig. 3 and 7, it can be understood that in this arrangement, the first sub-light emitting element 22 is closer to the first sub-pixel circuit 24 for transmitting the driving signal, and the first sub-light emitting element 22 can be directly electrically connected to the first sub-pixel circuit 24 (as shown in fig. 7) or can be electrically connected to the first sub-pixel circuit 24 through the signal transmission trace 10 (as shown in fig. 3), where the direct electrical connection refers to the electrical connection between the two through the via b between the layers.

In addition, as mentioned in the above embodiment, since the second sub-light emitting element 23 is further away from the second sub-pixel circuit 19 for transmitting the driving signal thereto, the direct electrical connection process of the two is more difficult. Accordingly, the second sub-light emitting element 23 may be provided to be electrically connected to the second sub-pixel circuit 19 through the signal transmission wiring 10.

The signal transmission line 10 for connecting the first sub-pixel circuit 24 and the first sub-light emitting element 22 is defined as a first signal transmission line 101, and the signal transmission line 10 for connecting the second sub-pixel circuit 19 and the second sub-light emitting element 23 is defined as a second signal transmission line 102. In view of the fact that the distance between the first sub-pixel circuit 24 and the first sub-light emitting element 22 along the first direction X is greater than the distance between the second sub-pixel circuit 19 and the second sub-light emitting element 23 along the first direction X, the length of the first signal transmission trace 101 along the first direction X is smaller than the length of the second signal transmission trace 102 along the first direction X.

Alternatively, with continued reference to fig. 3, in a possible embodiment, the first sub-pixel circuit arrangement area 17 is located on a side of any of the second sub-pixel circuit arrangement areas 18 remote from the first pixel driving circuit 9.

Specifically, in the embodiment shown in fig. 3, the first sub-pixel circuit setting area 17 is located on the side of the second sub-pixel circuit setting area 18 away from the first pixel driving circuit setting area 6 as a whole. That is, the first sub-pixel circuit setting area 17 is entirely located in an area outside in the first pixel circuit setting area 5. In this way, the second sub-pixel circuit arrangement region 18 is closer to the second sub-light emitting element arrangement region 21, the length of the second signal transmission trace 102 along the first direction X is shorter, and the voltage drop when transmitting the driving signal is smaller.

In fig. 3, the first sub-pixel circuit 24 and the first sub-light emitting element 22 are exemplarily shown to be electrically connected through the first signal transmission wiring 101, and the actual arrangement manner is not limited thereto, and direct electrical connection between the two may be provided. When the first signal transmission wiring 101 is directly and electrically connected, the first signal transmission wiring 101 is not required.

Alternatively, with continued reference to fig. 7, in another possible embodiment, there are first sub-pixel circuit arrangement areas 17 located between two adjacent second sub-pixel circuit arrangement areas 18, and there are second sub-pixel circuit arrangement areas 18 located between two adjacent first sub-pixel circuit arrangement areas 17.

Specifically, in the embodiment shown in fig. 7, a portion of the first sub-pixel circuit arrangement region 17 and a portion of the second sub-pixel circuit arrangement region 18 may be disposed alternately along the first direction X. Along the first direction X, there are one or more first sub-pixel circuit arrangement regions 17 arranged between two adjacent second sub-pixel circuit arrangement regions 18; accordingly, along the first direction X, there are one or more second sub-pixel circuit arrangement regions 18 arranged between two adjacent first sub-pixel circuit arrangement regions 17. In this arrangement shown in fig. 7, the first sub-pixel circuit 24 and the first sub-light emitting device 22 can be directly electrically connected, and the signal transmission trace 10 includes only the second signal transmission trace 102. In this way, the arrangement density of the second signal transmission traces 102 can be reduced to some extent due to the spacing between the portions of the second sub-pixel circuit arrangement regions 18. And further, the difficulty in laying the second signal transmission wires 102 is reduced, and meanwhile, the interference of driving signals transmitted between adjacent second signal transmission wires 102 is avoided.

For example, with continued reference to fig. 7, the first sub-pixel circuit arrangement areas 17 and the second sub-pixel circuit arrangement areas 18 are alternately arranged in a cyclic manner along the first direction X; the first direction X is the same as the arrangement direction of the plurality of data lines 1.

Specifically, as shown in fig. 7, the first sub-pixel circuit arrangement region 17 and the second sub-pixel circuit arrangement region 18 may be arranged alternately in order in the first direction X. A second sub-pixel circuit arrangement region 18 is arranged between any two adjacent first sub-pixel circuit arrangement regions 17, and a first sub-pixel circuit arrangement region 17 is arranged between any two adjacent second sub-pixel circuit arrangement regions 18. In this arrangement, the overall arrangement of the second signal transmission trace 102 is relatively uniform.

Of course, the arrangement of the first sub-pixel circuit arrangement region 17 and the second sub-pixel circuit arrangement region 18 is not limited thereto, and can be adjusted according to actual requirements by those skilled in the art. When the arrangement of the first sub-pixel circuit arrangement region 17 and the second sub-pixel circuit arrangement region 18 is changed, the arrangement of the first signal transmission trace 101 and the second signal transmission trace 102 may be adjusted accordingly.

In addition, referring to fig. 7, for the diamond pixel arrangement mode, red light emitting elements R, green light emitting elements G, blue light emitting elements B, and green light emitting elements G are alternately and circularly arranged along the first direction X. One red light emitting element R (or blue light emitting element B) and one green light emitting element G constitute a first sub-pixel. In this arrangement, the green light emitting element G is always located at an upper position in the second direction Y for the same row of sub-pixels. Therefore, in this embodiment, for the sub-pixels in the same row direction, the orthographic projection of the second signal transmission trace 102 electrically connected to the green light emitting element G on the plane of the display panel is located at one side of the sub-pixel in the row (or the second sub-pixel circuit 19 in the row) near the sub-pixel in the row (or the second sub-pixel circuit 19 in the row), and the orthographic projection of the second signal transmission trace 102 electrically connected to the red light emitting element R or the blue light emitting element B on the plane of the display panel is located at one side of the sub-pixel in the row (or the second sub-pixel circuit 19 in the row) near the sub-pixel in the next row (or the second sub-pixel circuit 19 in the next row), so as to facilitate the arrangement of the second signal transmission trace 102.

For other arrangements of the light emitting elements, the layout of the second signal transmission trace 102 may be adjusted accordingly, which is not illustrated in the embodiments of the present invention.

As will be appreciated by those skilled in the art, the first pixel driving circuit 9 for supplying the driving control signal to the first pixel circuit 8 includes various types, and may include, for example, a scanning driving circuit transmitting a scanning control signal and/or a light emission control driving circuit transmitting a light emission control signal, etc. The scanning driving circuit is electrically connected with the first pixel circuit 8 through a scanning line, and the light emission control driving circuit is electrically connected with the first pixel circuit 8 through a light emission control signal line, wherein the scanning line and the light emission control signal line are the driving control signal line. The embodiment of the present invention is not limited to a specific type of arrangement of the first pixel driving circuit 9, and one skilled in the art may perform the arrangement according to actual requirements.

Optionally, fig. 8 is a schematic diagram of a partial enlarged structure of another display panel according to an embodiment of the present invention, and referring to fig. 8, a plurality of first pixel circuits 8 may be arranged in an array; the first pixel driving circuit 9 includes a scanning driving circuit 25; the display panel further includes a light emission control driving circuit 26 located in the non-display area NA, the light emission control driving circuit 26 including a light emission control unit 27 arranged in cascade of a plurality of stages; the light emission control unit 27 is electrically connected to the n rows of first pixel circuits 8 disposed adjacently, and the light emission control unit 27 overlaps the n rows of first pixel circuits 8 disposed adjacently in the first direction X; the first direction X is the same as the arrangement direction of the plurality of data lines 1; wherein n is more than or equal to 2 and n is an integer.

As shown in fig. 8, the plurality of first pixel circuits 8 may be arranged in an array along the first direction X and the second direction Y. In this embodiment, the first pixel driving circuit 9 may be a scan driving circuit 25, and the scan driving circuit 25 provides scan control signals to the first pixel circuits 8 arranged in an array. The light emission control driving circuit 26 is disposed in the non-display area NA, and may be disposed in the non-display area NA at the left and/or right of the display area AA.

The scan driving circuit 25 may be constituted by a plurality of scan driving units 28 disposed in cascade, and each scan driving unit 28 may be electrically connected to the 1-line first pixel circuits 8 through a scan line 29 extending in the first direction X, and transmit a scan control signal to the 1-line first pixel circuits 8. That is, the scan driving unit 28 can drive and control the 1-row first pixel circuits 8 in a 1-drive 1 manner to ensure that the first pixel circuits 8 work normally. When the number of the first pixel circuit arrangement regions 5 is 2, the scan driving unit 28 simultaneously transmits the scan control signals to the first pixel circuits 8 on both sides thereof.

The light emission control driving circuit 26 is constituted by a plurality of light emission control units 27 in cascade, and each light emission control unit 27 is electrically connectable to the n-row first pixel circuits 8 through a light emission control signal line 30 extending in the first direction X for driving and controlling the n-row first pixel circuits 8 at the same time. That is, the light emission control units 27 are 1-drive-more, and each light emission control unit 27 is configured to drive at least two rows of the first pixel circuits 8. As will be appreciated by those skilled in the art, in general, the enable period of the light-emitting control signal is longer, and the display effect of the display panel is not substantially affected by the light-emitting control unit 27 adopting the 1-drive driving method. Meanwhile, the light-emitting control unit 27 adopts a 1-drive driving mode, so that the difficulty in arrangement of signal lines between the light-emitting control unit 27 and the first pixel circuit 8 is reduced. Each of the light emission control units 27 is exemplarily shown to be electrically connected to the 2-row first pixel circuits 8, and the actual arrangement is not limited thereto.

With continued reference to fig. 8, in the present embodiment, it may also be provided that projections of the light emission control unit 27 in the first direction X overlap projections of n rows of the first pixel circuits 8 electrically connected thereto in the first direction X. In this arrangement, the length of the light emission control unit 27 along the second direction Y is similar to or the same as the length of the n rows of the first pixel circuits 8 along the second direction Y.

In which fig. 8 exemplarily shows that the non-display area NA on both the left and right sides of the display panel is provided with the light emission control driving circuit 26. In this arrangement, the light-emitting control units 27 at the same stage of the non-display area NA on both sides are electrically connected to the same n rows of the first pixel circuits 8, and the light-emitting control units 27 can drive the n rows of the first pixel circuits 8 in a bilateral driving manner. The adjacent n rows of first pixel circuits 8 simultaneously receive the light emission control signals transmitted from the light emission control units 27 in the non-display area NA on both sides, thereby reducing the load of the light emission control signal lines 30. Of course, in other embodiments not shown, the light emission control driving circuit 26 may be disposed in the non-display area NA on only one side, and the light emission control unit 27 drives the n rows of the first pixel circuits 8 in a single-side driving manner, which will not be described in detail in the embodiments of the present invention.

Optionally, fig. 9 is a schematic diagram of a partial enlarged structure of a display panel according to another embodiment of the present invention, referring to fig. 9, in other possible embodiments, a plurality of first pixel circuits 8 are arranged in an array, and the display panel includes a plurality of first pixel circuit groups 31, the plurality of first pixel circuit groups 31 are arranged along a second direction Y, and each of the first pixel circuit groups 31 includes 2*n first pixel circuit rows adjacently arranged along the second direction Y; the second direction Y is the same as the extending direction of the data line 1, n is more than or equal to 2, and n is an integer; the first pixel driving circuit 9 includes a scanning driving circuit 25; the non-display area NA comprises a first non-display area NA1 and a second non-display area NA2 which are positioned at two sides of the display area AA opposite to each other; the display panel further includes a first light emission control driving circuit 261 located at the first non-display area NA1 and a second light emission control driving circuit 262 located at the second non-display area NA2, the first light emission control driving circuit 261 including a plurality of stages of first light emission control units 271, the second light emission control driving circuit 262 including a plurality of stages of second light emission control units 272; the ith-stage first light emission control unit 271 is electrically connected with the first n rows of first pixel circuit rows in the ith-group first pixel circuit group 31, the ith-stage second light emission control unit 272 is electrically connected with the last n rows of first pixel circuit rows in the ith-group first pixel circuit group 31, and the light emission control signal output terminal 32 of the ith-stage first light emission control unit 271 is electrically connected with the enable signal receiving terminal 33 of the ith-stage second light emission control unit 272; and in the first direction X, the i-th stage first light emission control unit 271 and the i-th stage second light emission control unit 272 each overlap the i-th group first pixel circuit group 31; the first direction X is the same as the arrangement direction of the plurality of data lines 1.

Specifically, as shown in fig. 9, the arrangement of the first pixel circuits 8 is the same as that of the embodiment shown in fig. 8, the first pixel driving circuits 9 may still be the scan driving circuits 25, and the light emission control driving circuits 26 are still disposed in the non-display area NA at both sides of the display area AA. The difference is that in the present embodiment, the light emission control driving circuit 26 can be divided into a first light emission control driving circuit 261 and a second light emission control driving circuit 262. The first light emission control driving circuit 261 is located in a first non-display area NA1 on one side of the display panel, and the second light emission control driving circuit 262 is located in a second non-display area NA2 on the other side of the display panel. The first light emission control driving circuit 261 is constituted by a plurality of stages of first light emission control units 271 arranged in the second direction Y, and the second light emission control driving circuit 262 is constituted by a plurality of stages of second light emission control units 272 arranged in the second direction Y.

In addition, in the present embodiment, the plurality of first pixel circuits 8 are further divided into a plurality of first

pixel circuit groups

31, and 2*n rows of first pixel circuits 8 adjacent to each other in the second direction Y are disposed in each of the first pixel circuit groups 31, and the plurality of first pixel circuit groups 31 are arranged in the second direction Y. Wherein 2*n rows of first pixel circuits 8 in each first pixel circuit group 31 are driven by a first light emission control unit 271 and a second light emission control unit 272, respectively, which are disposed at the same stage.

Specifically, the first n-th row first pixel circuits 8 in the i-th group first pixel circuit group 31 receive the light emission control signal output from the i-th stage first light emission control unit 271, and the second n-th row first pixel circuits 8 receive the light emission control signal output from the i-th stage second light emission control unit 272. i is more than or equal to 1 and i is an integer. Taking n as 2 as an example in the drawing, the first 2 rows of first pixel circuits 8 in the 1 st group of first pixel circuits 31 receive the light emission control signals output by the 1 st stage first light emission control unit 271, and the second 2 rows of first pixel circuits 8 receive the light emission control signals output by the 1 st stage second light emission control unit 272, and the connection manner of the other first pixel circuit groups 31 and the other light emission control driving circuits 26 is similarly deduced.

In addition, as shown in fig. 9, the 1 st to i th stage first light emission control units 271 and the 1 st to i th stage second light emission control units 272 may be provided alternately in turn. In short, the light emission control signal output terminal 32 of the 1 st stage first light emission control unit 271 is electrically connected to the enable signal receiving terminal 33 of the 1 st stage second light emission control unit 272, and the light emission control signal output by the 1 st stage first light emission control unit 271 is used not only to drive the first n rows of first pixel circuits 8 in the 1 st group of first pixel circuit groups 31 but also to serve as the enable signal of the 1 st stage second light emission control unit 272, and the 1 st stage second light emission control unit 272 sends the light emission control signal to the second n rows of first pixel circuits 8 in the 1 st group of first pixel circuit groups 31 after receiving the enable signal. Similarly, the light emission control signal output by the 1 st stage second light emission control unit 272 is used not only to drive the first pixel circuits 8 of the next n rows in the 1 st group of first pixel circuit groups 31, but also to serve as the enable signal of the 2 nd stage first light emission control unit 271, and the 2 nd stage first light emission control unit 271 receives the enable signal and transmits the light emission control signal to the first pixel circuits 8 of the first n rows in the 2 nd group of first pixel circuit groups 31, and so on.

In this arrangement, each stage of the light-emitting control unit 27 can drive the corresponding n rows of the first pixel circuits 8 in a single-side driving manner. In contrast to the embodiment shown in fig. 8, each stage of the light emission control unit 27 overlaps with n rows of the first pixel circuits 8 in the first direction X. In this embodiment, in the single-side driving manner, the second light-emitting control units 272 of each stage of the first light-emitting control units 271 and the same stage of the first light-emitting control units 271 and the second light-emitting control units 272 can overlap the first pixel circuits 8 of 2*n rows along the first direction X, so that the lengths of the first light-emitting control units 271 and the second light-emitting control units 272 along the second direction Y can be further increased, the lengths of the first light-emitting control units 271 and the second light-emitting control units 272 along the first direction X can be shortened, and the narrow-frame effect can be further improved.

Optionally, fig. 10 is a schematic view of a partial enlarged structure of a display panel according to another embodiment of the present invention, and referring to fig. 10, in other possible embodiments, a plurality of first pixel circuits 8 are still arranged in an array; the first pixel driving circuit 9 includes a light emission control driving circuit 26, and the light emission control driving circuit 26 includes a light emission control unit 27 provided in cascade of a plurality of stages; the light emission control unit 27 is electrically connected to the n rows of first pixel circuits 8 disposed adjacently, and the light emission control unit 27 overlaps the n rows of first pixel circuits 8 disposed adjacently in the first direction X; the first direction X is the same as the arrangement direction of the plurality of data lines 1; wherein n is more than or equal to 2 and n is an integer.

Specifically, as shown in fig. 10, the first pixel circuits 8 are still arranged in an array, and unlike the above embodiment, in this embodiment, the first pixel driving circuit 9 may be provided as the light emission control driving circuit 26. The scan driving circuit 25 may be disposed in a frame region of the display panel.

The light-emitting control driving circuit 26 may still include a plurality of light-emitting control units 27 arranged in cascade, and the light-emitting control units 27 may still be driven in a 1-wheel drive manner. N rows of first pixel circuits 8 to which each stage of the light emission control unit 27 is electrically connected may be provided to overlap in the first direction X, and each stage of the light emission control unit 27 is electrically connected to n rows of first pixel circuits 8 provided adjacently in the second direction Y. When the number of the first pixel circuit arrangement regions 5 is 2, the light emission control unit 27 simultaneously transmits light emission control signals to the n rows of the first pixel circuits 8 on both sides thereof.

In the embodiment shown in fig. 9 and 10, either one of the scan driving circuit 25 and the light emission control driving circuit 26 is disposed in the display area AA, and the other is disposed in the non-display area NA, so that the frame size can be effectively reduced. The problem that the first pixel driving circuit 9 is arranged too much in the display area AA and the first pixel circuit 8 drives the first light emitting element 7 normally is not caused. In other embodiments, not shown, both the scan driving circuit 25 and the light emission control driving circuit 26 may be disposed in the display area AA, thereby further reducing the size of the frame area.

Alternatively, with continued reference to fig. 8, in a possible embodiment, a plurality of first pixel circuits 8 are arranged in an array; the display panel may further include a plurality of initialization signal lines 34, the initialization signal lines 34 being connected to the first pixel circuits 8 columns in the same column; the initialization signal lines 34 extend in the second direction Y, and the plurality of initialization signal lines 34 are arranged in the first direction X; the first direction X is the same as the arrangement direction of the plurality of data lines 1, and the second direction Y is the same as the extending direction of the data lines 1.

Specifically, as shown in fig. 8, the first pixel circuits 8 are still arranged in an array, and a plurality of initialization signal lines 34 are further disposed in the display panel, and the initialization signal lines 34 are arranged in the same manner as the data lines 1, and also extend along the second direction Y and are arranged along the first direction X. Each of the initialization signal lines 34 is electrically connected to the same column of first pixel circuits 8 to transmit an initialization signal to the same column of first pixel circuits 8. Only the arrangement of the initializing signal lines 34 is shown in fig. 8, which is not shown in electrical connection with the first pixel circuits 8, and it will be understood by those skilled in the art that each initializing signal line 34 should be actually electrically connected to the first pixel circuits 8 of the same column, respectively.

The advantage of this arrangement is that the initialization signal line 34 is mainly disposed in the display area AA and does not occupy the positions of the left and right non-display areas NA of the display panel, so that the size of the left and right frames of the display panel is further reduced.

Optionally, with continued reference to fig. 8, the display panel may further include an initialization signal bus 35 located in the non-display area NA, the initialization signal bus 35 extending along the first direction X; the plurality of initialization signal lines 34 are electrically connected to the initialization signal bus 35.

As shown in fig. 8, an initialization signal bus 35 extending in the first direction X is further provided in the non-display area NA, and the initialization signal bus 35 is electrically connected to the plurality of initialization signal lines 34, respectively. The initialization signal bus 35 is used to connect a driving module (not shown) with the plurality of initialization signal lines 34. The initialization signal bus 35 extends along the first direction X, and may be disposed on the display panel and/or in the lower non-display area NA, so as not to occupy the area of the left and right non-display areas NA of the display panel.

Alternatively, referring to fig. 1 and 8 in combination, in a possible embodiment, the initialization signal line 34 is arranged in the same layer as the data line 1; alternatively, the connection trace 2 includes a first connection portion 201 and a second connection portion 202, the first connection portion 201 and the second connection portion 202 are connected, the first connection portion 201 extends along a first direction X, and the second connection portion 202 extends along a second direction Y; the initialization signal line 34 is arranged in the same layer as the second connection section 202.

As shown in fig. 8, the initialization signal line 34 and the same wiring layer as the extending direction thereof may be disposed, so as to reduce the difficulty of layout of the initialization signal line 34. As mentioned in the above embodiment, the initialization signal line 34 is the same as the extending direction of the data line 1. Thus, in one possible embodiment, the initialization signal line 34 may be located in the same layer as the data line 1 and prepared in the same process.

As shown in fig. 1, the connection trace 2 may be formed by a first connection portion 201 and a second connection portion 202 that are electrically connected, wherein the first connection portion 201 extends along a first direction X (i.e., a row direction), and the second connection portion 202 extends along a second direction Y (i.e., a column direction). In a possible embodiment, the initialization signal line 34 and the second connection portion 202 are also located in the same layer and manufactured in the same process.

In addition, referring to fig. 4, in the embodiment of the present application, the display panel may include a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 that are sequentially stacked along the light emitting direction of the display panel, where the metal layers are mutually insulated. The first transistor T1 in the first pixel circuit 8 includes a gate, a source, and a drain. Wherein, the gate electrode can be prepared by using the first metal layer M1, and the source electrode and the drain electrode can be prepared by using the second metal layer M2. A data line (not shown in fig. 4) for outputting a data signal to the source electrode (or drain electrode) may also be prepared using the second metal layer M2. The third metal layer M3 may be used to prepare a light shielding metal layer, a connection trace 2, a power transmission line, a connection jumper between the anode of the first light emitting element 7 and the source (or drain) of the first transistor T1, and the like. The fourth metal layer M4 may be used to prepare the connection trace 2. Accordingly, in the embodiment of the present application, the initialization signal line (not shown in fig. 4) may be prepared using the second metal layer M2, the third metal layer M3, or the third metal layer M4.

Of course, in other embodiments not shown, the initialization signal line 34 may be prepared by using other metal layers, which will not be described in detail herein, and those skilled in the art may set the initialization signal line according to actual requirements.

Optionally, fig. 11 is a schematic view of a partial enlarged structure of a display panel according to another embodiment of the present invention, referring to fig. 1 and 11, in a possible embodiment, the display panel may further include a virtual connection trace 36 located in the second display area AA2, where the virtual connection trace 36 and the connection trace 2 are in the same layer and are insulated from each other; the dummy connection trace 36 is electrically connected to the fixed potential signal structure.

Specifically, the display panel may further include a virtual connection trace 36, where the virtual connection trace 36 is disposed in the second display area AA2 and is disposed in the same layer as the connection trace 2. Since the signal transmission line 10 is not disposed in the second display area AA2, by disposing the virtual connection line 36 in the second display area AA2, the resistance difference existing in the transmission process of the balanced signal transmission line 10 can be improved, and the stability of signal transmission on the display surface can be ensured. In addition, the virtual connection trace 36 and the signal transmission trace 10 may be disposed on the same film layer, for example, may be disposed on the fourth metal layer M4, so as to improve uniformity of the trace layout in the fourth metal layer M4, further avoid different light reflectivities in different areas of the display panel due to imbalance of the signal transmission trace 10, and improve display uniformity.

The dummy connection trace 36 is insulated from the connection trace 2, i.e. the dummy connection trace 36 is prevented from interfering with the signal transmitted in the connection trace 2. Further, in order to avoid that other signals are induced to influence normal transmission of the display signals when the virtual connection wiring 36 is arranged in a floating mode, potential adjustment can be performed on the virtual connection wiring 36, for example, the virtual connection wiring 36 is electrically connected with a fixed potential signal structure, so that on one hand, fixed potential signals are transmitted on the virtual connection wiring 36, the potential is not influenced by other signals, and interference is not caused to other signals; on the other hand, when the virtual connection trace 36 is electrically connected with the fixed potential signal structure, the resistance loss of the signal in the metal trace for providing the fixed potential signal in the transmission process can be reduced, and the signal transmission effect in the display panel can be improved.

It should be noted that, the setting position of the fixed potential signal structure is not specifically limited in the embodiment of the present invention, and the fixed potential signal structure includes at least one of a positive power signal line (not shown in the figure), a negative power signal line (not shown in the figure), and an initialization signal line 34 by way of example.

Wherein the dummy connection trace 36 may be electrically connected with at least one of the positive power signal line, the negative power signal line, and the initialization signal line 34.

In an alternative embodiment, a dummy connection trace 36 may be provided in electrical connection with the negative power signal line. The negative power signal line is generally connected from the non-display area NA of the display panel frame, resulting in a larger impedance and a larger loading of the negative power signal. After the virtual connection wiring 36 is connected with the virtual connection wiring, a section of resistor is connected in parallel to the negative power supply signal line, so that the impedance of the negative power supply signal line can be effectively reduced, the voltage drop of the negative power supply signal line is reduced, and the stable transmission of the negative power supply signal is facilitated.

Alternatively, referring to fig. 1, 3, 4 and 7 in combination, the connection trace 2 includes a first connection part 201 and a second connection part 202, the first connection part 201 and the second connection part 202 are connected, the first connection part 201 extends along a first direction X, and the second connection part 202 extends along a second direction Y; the first direction X is the same as the arrangement direction of the plurality of data lines 1, and the second direction Y is the same as the extending direction of the data lines 1; the signal transmission trace 10 is arranged in the same layer as the first connection section 201.

The arrangement of the connection trace 2 is mentioned in the above embodiment, in which one end of the first connection section 201 is electrically connected to the data line 1, the other end of the first connection section 201 is electrically connected to the second connection section 202, and the end of the second connection section 202 away from the first connection section 201 is electrically connected to the signal wiring 3. The extending direction of the second connection portion 202 is the same as the extending direction of the data line 1, and the extending direction of the first connection portion 201 is the same as the extending direction of the signal transmission trace 10.

Wherein, the first connection part 201 and the second connection part 202 can be arranged in the same layer or different layers, and when the first connection part 201 and the second connection part 202 are arranged in the same layer, both the first connection part and the second connection part are arranged in the fourth metal layer M4; when the two layers are disposed, the first connection portion 201 may be located on the fourth metal layer M4, and the second connection portion 202 may be located on the third metal layer M3.

Because the number of metal wires in the fourth metal layer M4 is relatively small, the signal transmission lines can be prepared by using the fourth metal layer M4, so that the difficulty in laying the signal transmission lines is reduced, and meanwhile, the mutual interference between the adjacent signal transmission wires 10 is avoided.

It should be noted that, in the embodiment shown in fig. 3, the signal transmission trace 10 extends along the first direction X, and thus the signal transmission trace 10 may be located in the same film layer. In other embodiments, as shown in fig. 7, the signal transmission trace 10 may be composed of a first section 101 connected along the first direction X and a second section 102 extending along the second direction Y. In this arrangement, the first portion 101 and the first connection portion 201 may be arranged in the same layer, and the second portion 102 and the second connection portion 202 may be arranged in the same layer. For example, the first portion 101 and the first connection portion 201 are both located on the fourth metal layer M4, and the second portion 102 and the second connection portion 202 are both located on the third metal layer M3, so that the same metal layer only includes the metal traces with the same extending direction.

Optionally, fig. 12 is a schematic view of a partial cross-sectional structure of a display panel according to an embodiment of the present invention, referring to fig. 12, in a possible embodiment, the display panel may further include a package structure 37 located on a side of the first light emitting element 7 away from the first pixel circuit 8, where the package structure 37 includes an organic package layer 38; the display panel further comprises a retaining wall structure 39 located in the non-display area NA, the retaining wall structure 39 surrounds the display area AA, and the retaining wall structure 39 comprises a ring of retaining wall sub-structures 40; the barrier rib substructure 40 is used to block the organic material in the organic encapsulation layer 38 from extending to the edge of the display panel, and the barrier rib substructure 40 is used to define the placement boundaries of the metal traces in the display area AA.

Specifically, as shown in fig. 12, the display panel further includes a package structure 37 and a wall structure 39, and the package structure 37 is located on a side of the first light emitting element 7 away from the first pixel circuit 8. The wall structure 39 is disposed in the non-display area NA at the frame of the display panel and surrounds the display area AA. The encapsulation structure 37 may include the organic encapsulation layer 38, but is not limited thereto, and may also include the organic encapsulation layer 38 and the inorganic encapsulation layer 41, etc. which are stacked. The packaging structure 37 is used for blocking water and oxygen and external pollution particles, so as to prevent the water and oxygen or the external pollution particles from invading the display panel, and the normal operation and the display effect of the pixel circuit or the light-emitting element are affected. The organic encapsulation layer 38 also can slow down the stress of the adjacent film layers when the display panel is bent, and also serves as planarization.

The material forming the organic encapsulation layer 38 may include epoxy resin, acrylate, metaacrylic or methacrylic, etc., but is not limited thereto; the organic encapsulation layer 38 may be prepared by ink-jet printing, again without limitation. The material forming the inorganic encapsulation layer 41 may include silicon nitride or silicon oxide, etc., but is not limited thereto; the inorganic encapsulation layer 41 may be prepared by an atomic layer deposition process, a chemical vapor deposition process, or the like, and is not limited thereto.

In this embodiment, as shown in fig. 12, the retaining wall structure 39 is formed by a retaining wall substructure 40 disposed along a circle around the display area AA. The barrier rib substructure 40 is provided to block the outflow of organic material during the ink jet printing process to form the organic encapsulation layer 38, thereby avoiding the epitaxy of the organic material. Meanwhile, the retaining wall substructure 40 may also serve as a cut-off boundary of various metal traces d in the display area AA, where the metal traces d may include electrode traces in the first light emitting element 7, metal film layer wirings in the first pixel circuit 8, and metal film layer wirings in the pixel driving circuit. The metal trace d in the display area AA extends from the display area AA to a side of the retaining wall substructure 40 adjacent to the display area AA. Of course, the retaining wall substructure 40 may also serve as a cut-off boundary of various metal traces d in the non-display area NA, and the metal traces d in the non-display area NA extend from a side of the non-display area NA adjacent to the display area AA to a side of the retaining wall substructure 40 adjacent to the non-display area NA.

In this embodiment, the retaining wall substructure 40 is utilized to simultaneously block the organic encapsulation layer 38 and the metal trace d, so that the reliability of the display panel can be ensured, the NA area of the non-display area can be further reduced, and the narrow frame effect can be improved.

The embodiment of the present invention is not limited to the specific shape, material, etc. of the retaining wall substructure 40, and those skilled in the art can set the parameters according to actual requirements. Optionally, any structure known to those skilled in the art, such as a buffer layer, a planarization layer, an optical adhesive layer, etc., may be further included in the display panel provided in the present application, which will not be described herein.

Based on the same inventive concept, the embodiment of the invention also provides a display device. Fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 13, the display device includes the display panel 100 provided by any embodiment of the present invention, so the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, and will not be described herein. The display device may be, for example, an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A display panel, comprising a display area and a non-display area;

2. The display panel of claim 1, wherein the first display area comprises two of the first pixel circuit arrangement areas;

the first pixel driving circuit arrangement region is located between two first pixel circuit arrangement regions.

3. The display panel according to claim 1, wherein the display region further includes a second display region including a second light emitting element arrangement region provided with a plurality of second light emitting elements and a second pixel circuit arrangement region provided with a plurality of second pixel circuits electrically connected to the first pixel driving circuit and the second light emitting elements, respectively; and the second light emitting element setting region overlaps with the second pixel circuit setting region in a thickness direction of the display panel;

the second display area is positioned at one side of the first pixel circuit setting area far away from the first pixel driving circuit setting area.

4. A display panel according to claim 3, wherein the first pixel circuit comprises at least two first electronic components, the at least two first electronic components comprising at least one first transistor and at least one first storage capacitor;

the second pixel circuit comprises at least two second electronic components, and the at least two second electronic components comprise at least one second transistor and at least one second storage capacitor;

the channel width-to-length ratio of at least one first transistor is smaller than that of the second transistor, the area of at least one first storage capacitor is smaller than that of the second storage capacitor, and/or the distance between two adjacent first electronic elements is smaller than that between two adjacent second electronic elements along the first direction; the first direction is the same as the arrangement direction of the plurality of data lines.

5. The display panel according to claim 1, wherein the first pixel circuit arrangement region includes a plurality of first sub-pixel circuit arrangement regions provided with first sub-pixel circuits and a plurality of second sub-pixel circuit arrangement regions provided with second sub-pixel circuits;

The first light-emitting element arrangement region comprises a first sub-light-emitting element arrangement region and a second sub-light-emitting element arrangement region, the first sub-light-emitting element arrangement region is provided with a first sub-light-emitting element, and the second sub-light-emitting element arrangement region is provided with a second sub-light-emitting element;

the first sub-pixel circuit is directly and electrically connected with the first sub-light emitting element or is electrically connected with the first sub-light emitting element through a first signal transmission wiring, the second sub-pixel circuit is electrically connected with the second sub-light emitting element through a second signal transmission wiring, and the length of the second signal transmission wiring is longer than that of the first signal transmission wiring.

6. The display panel of claim 5, wherein the first subpixel circuit arrangement area is located on a side of any of the second subpixel circuit arrangement areas remote from the first pixel driving circuit.

7. The display panel of claim 5, wherein there is the first sub-pixel circuit arrangement region between adjacent two of the second sub-pixel circuit arrangement regions, and wherein there is the second sub-pixel circuit arrangement region between adjacent two of the first sub-pixel circuit arrangement regions.

8. The display panel of claim 7, wherein the first subpixel circuit arrangement areas alternate cyclically with the second subpixel circuit arrangement areas along a first direction; the first direction is the same as the arrangement direction of the plurality of data lines.

9. The display panel of claim 1, wherein a plurality of the first pixel circuits are arranged in an array;

the first pixel driving circuit includes a scan driving circuit;

the display panel also comprises a light-emitting control driving circuit positioned in the non-display area, wherein the light-emitting control driving circuit comprises a light-emitting control unit which is arranged in a multistage cascade manner;

the light-emitting control unit is electrically connected with n rows of the first pixel circuits which are adjacently arranged, and overlaps with the n rows of the first pixel circuits which are adjacently arranged along a first direction; the first direction is the same as the arrangement direction of the plurality of data lines; wherein n is more than or equal to 2 and n is an integer.

10. The display panel according to claim 1, wherein a plurality of the first pixel circuit groups are arranged in an array, and the display panel includes a plurality of first pixel circuit groups, the plurality of first pixel circuit groups being arranged in a second direction, each of the first pixel circuit groups including 2*n rows of the first pixel circuit arranged adjacently in the second direction; the second direction is the same as the extending direction of the data line, n is more than or equal to 2, and n is an integer;

The first pixel driving circuit includes a scan driving circuit;

the non-display area comprises a first non-display area and a second non-display area which are positioned at two sides of the display area which are oppositely arranged; the display panel further comprises a first light-emitting control driving circuit positioned in the first non-display area and a second light-emitting control driving circuit positioned in the second non-display area, wherein the first light-emitting control driving circuit comprises a multi-stage first light-emitting control unit, and the second light-emitting control driving circuit comprises a multi-stage second light-emitting control unit;

the first light-emitting control unit of the ith stage is electrically connected with the first pixel circuit row of the first pixel circuit group, the second light-emitting control unit of the ith stage is electrically connected with the first pixel circuit row of the first pixel circuit group of the second pixel circuit group of the ith stage, and the light-emitting control signal output end of the first light-emitting control unit of the ith stage is electrically connected with the enabling signal receiving end of the second light-emitting control unit of the ith stage; and in the first direction, the first light-emitting control unit of the ith stage and the second light-emitting control unit of the ith stage are overlapped with the first pixel circuit group of the ith group; the first direction is the same as the arrangement direction of the plurality of data lines.

11. The display panel of claim 1, wherein a plurality of the first pixel circuits are arranged in an array;

the first pixel driving circuit comprises a light-emitting control driving circuit, and the light-emitting control driving circuit comprises a light-emitting control unit which is arranged in a multistage cascade manner;

12. The display panel of claim 1, wherein a plurality of the first pixel circuits are arranged in an array;

the display panel further comprises a plurality of initialization signal lines, wherein the initialization signal lines are connected with the first pixel circuit columns in the same column; the initialization signal lines extend along a second direction, and a plurality of the initialization signal lines are arranged along a first direction; the first direction is the same as the arrangement direction of the plurality of data lines, and the second direction is the same as the extending direction of the data lines.

13. The display panel of claim 12, further comprising an initialization signal bus located in the non-display region, the initialization signal bus extending in the first direction;

The initialization signal lines are electrically connected with the initialization signal bus.

14. The display panel according to claim 12, wherein the initialization signal line is provided in the same layer as the data line;

or, the connection trace includes a first connection part and a second connection part, the first connection part and the second connection part are connected, the first connection part extends along the first direction, and the second connection part extends along the second direction; the initialization signal line and the second connection subsection are arranged in the same layer.

15. A display panel according to claim 3, further comprising a virtual connection trace in the second display area, the virtual connection trace being co-layered with and insulated from the connection trace;

the virtual connection wiring is electrically connected with the fixed potential signal structure.

16. The display panel of claim 15, wherein the fixed potential signal structure comprises at least one of a positive power signal line, a negative power signal line, and an initialization signal line.

17. The display panel of claim 1, wherein the connection trace comprises a first connection section and a second connection section, the first connection section and the second connection section being connected, and the first connection section extending in a first direction and the second connection section extending in a second direction; the first direction is the same as the arrangement direction of the plurality of data lines, and the second direction is the same as the extension direction of the data lines;

The signal transmission wiring and the first connection part are arranged on the same layer.

18. The display panel of claim 1, further comprising an encapsulation structure on a side of the first light emitting element remote from the first pixel circuit, the encapsulation structure comprising an organic encapsulation layer;

the display panel also comprises a retaining wall structure positioned in the non-display area, wherein the retaining wall structure surrounds the display area, and the retaining wall structure comprises a circle of retaining wall substructure;

the retaining wall substructure is used for blocking the organic material in the organic encapsulation layer from extending to the edge of the display panel, and the retaining wall substructure is used for limiting the setting boundary of the metal routing in the display area.

19. A display device comprising the display panel of any one of claims 1-18.