CN116207074A - Electronic device - Google Patents

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Publication number
CN116207074A
CN116207074A CN202310338305.2A CN202310338305A CN116207074A CN 116207074 A CN116207074 A CN 116207074A CN 202310338305 A CN202310338305 A CN 202310338305A CN 116207074 A CN116207074 A CN 116207074A
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CN
China
Prior art keywords
metal layer
layer
insulating layer
electronic device
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310338305.2A
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Chinese (zh)
Inventor
洪堂钦
丁景隆
韦忠光
高克毅
王东荣
谢志勇
黄浩榕
李宜音
何家齐
林宜宏
周政旭
曾嘉平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innolux Display Corp filed Critical Innolux Display Corp
Priority claimed from CN202010411348.5A external-priority patent/CN112310041B/en
Publication of CN116207074A publication Critical patent/CN116207074A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/93—Variable capacitance diodes, e.g. varactors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure provides an electronic device. The electronic device comprises a first metal layer, a second metal layer, a first insulating layer and an electronic component. The first metal layer has an opening. The first insulating layer is located between the first metal layer and the second metal layer. The electronic component is electrically connected with the first metal layer, and the first insulating layer is positioned between the electronic component and the first metal layer. The opening of the first metal layer is overlapped with the second metal layer.

Description

Electronic device
The invention is a divisional application of an invention patent application with the application number of 202010411348.5 and the invention name of electronic device and manufacturing method thereof, which is proposed by 5/15/2020.
Technical Field
The present disclosure relates to devices, and more particularly, to an electronic device.
Background
As electronic devices become finer, active components are more difficult to fabricate directly on a substrate, film or glass. In addition, due to the limitation of line width and line spacing in the semiconductor process, a multi-layer wiring structure is required to be fabricated on a general circuit substrate to enable the active device to be disposed on the circuit substrate, thus resulting in an increase in the size and the process cost of the electronic device. In view of this, several embodiments of the solution are presented below.
Disclosure of Invention
The present disclosure is directed to an electronic device that can provide or manufacture an electronic structure including transistor circuitry and single-sided or double-sided redistribution process (Redistribution Layer, RDL) routing.
According to an embodiment of the disclosure, an electronic device includes a first metal layer, a second metal layer, a first insulating layer, and an electronic component. The first metal layer has an opening. The first insulating layer is located between the first metal layer and the second metal layer. The electronic component is electrically connected with the first metal layer, and the first insulating layer is positioned between the electronic component and the first metal layer. The opening of the first metal layer is overlapped with the second metal layer.
Based on the above, the electronic device of the present disclosure can realize an electronic device with a smaller size and a lower manufacturing cost by the redistribution process wiring with a smaller number of layers and the transistor circuit.
The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and for the sake of brevity of the drawings, various drawings in the present disclosure depict only a portion of the apparatus, and the specific components in the drawings are not necessarily drawn to scale. Furthermore, the number and size of the components in the figures are illustrative only and are not intended to limit the scope of the present disclosure.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
Fig. 1 is a schematic cross-sectional view illustrating a structure of an electronic device according to a first embodiment of the disclosure;
fig. 2A and 2B are flowcharts illustrating a method for manufacturing an electronic device according to a first embodiment of the disclosure;
FIGS. 3A-3D are schematic cross-sectional views of the structure at various stages during the fabrication method of FIGS. 2A and 2B;
fig. 4 is a schematic cross-sectional view illustrating a structure of an electronic device according to a second embodiment of the disclosure;
fig. 5A and 5B are flowcharts illustrating a method for manufacturing an electronic device according to a second embodiment of the disclosure;
FIGS. 6A-6D are schematic cross-sectional views of the structure at various stages during the fabrication methods of FIGS. 5A and 5B;
fig. 7 is a schematic cross-sectional view illustrating a structure of an electronic device according to a third embodiment of the disclosure;
FIG. 8 is a flowchart of a method for manufacturing an electronic device according to a third embodiment of the disclosure;
9A-9D are schematic cross-sectional views of the structure at various stages during the manufacturing method of FIG. 8;
fig. 10 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fourth embodiment of the disclosure;
FIG. 11 is a flowchart of a method for manufacturing an electronic device according to a fourth embodiment of the present disclosure;
FIGS. 12A-12D are schematic cross-sectional views of the structure at various stages during the manufacturing method of FIG. 11;
fig. 13 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fifth embodiment of the disclosure;
fig. 14 is a schematic cross-sectional view illustrating a structure of an electronic device according to a sixth embodiment of the disclosure;
fig. 15 is a schematic cross-sectional view illustrating a structure of an electronic device according to a seventh embodiment of the disclosure.
Description of the reference numerals
100. 400, 700, 1000, 1300, 1400, 1500;
110. 310, 410, 610, 710, 910, 1010, 1210, 1310, 1410, 1510: a first metal layer;
111. 311, 411, 611, 1311, 1411, 1511;
120. 320, 420, 620, 720, 920, 1020, 1220, 1320, 1420, 1520: a first insulating layer;
130. 330, 430, 630, 730, 930, 1030, 1230, 1330, 1430, 1530: a second metal layer;
140. 340, 440, 640, 740, 940, 1040, 1240, 1340, 1440, 1540;
150. 350, 450, 650, 750, 950, 1050, 1250, 1350, 1450, 1550: transistor circuitry;
160. 360, 460, 660, 760, 960, 1060, 1260, 1360, 1460, 1560 a second insulating layer;
170. 370, 370', 470, 670', 770, 970, 1070, 1270, 1370, 1470, 1570;
171. 172, 371, 372, 471, 472, 671, 672, 771, 772, 971, 972, 1071, 1072, 1251, 1271, 1272, 1351, 1371, 1372, 1452, 1471, 1472, 1553, 1571, 1572;
180. 380, 480, 680, 780, 980, 1080, 1280, 1380, 1480, 1580;
181. 381, 481, 681, 781, 981, 1081, 1281, 1381, 1481, 1581;
182. 382, 482, 682, 782, 982, 1082, 1282, 1382, 1482, 1582;
301. 303, 601, 603, 901, 903, 1203;
302. 602, 902, 1202 a connection layer;
312-316, 612-616 electrodes
690. 390 a passive component;
s1, a first surface;
s2, a second surface;
steps S201 to S213, S501 to S513, S801 to S811, and S1101 to S1111;
d1, a first direction;
d2, a second direction;
d3, third direction.
Detailed Description
Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that display device manufacturers may refer to a component by different names. It is not intended to distinguish between components that differ in function but not name. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …".
In some embodiments of the disclosure, terms such as "connected," "interconnected," and the like, with respect to joining, connecting, and the like, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures being disposed between the two structures, unless otherwise specified. And the term coupled, connected, may also include situations where both structures are movable, or where both structures are fixed. Furthermore, the term "coupled" includes any direct or indirect electrical connection.
When it is stated that a first material layer is disposed on or over a second material layer, this includes the case where the first material layer is in direct contact with the second material layer. Alternatively, one or more other material layers may be spaced apart, in which case there may not be direct contact between the first material layer and the second material layer. In some embodiments of the disclosure, terms such as "connected," "interconnected," and the like, with respect to joining, connecting, and the like, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures being disposed between the two structures, unless otherwise specified. And the term coupled, connected, may also include situations where both structures are movable, or where both structures are fixed.
As used herein, the terms "about," "substantially" and "approximately" generally mean within 15%, such as within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The amounts given herein are about amounts, i.e., where "about", "substantially" or "substantially" is not specifically recited, the meaning of "about", "substantially" or "substantially" may still be implied.
Although terms such as "first," "second," "third," etc. may be used to describe or name different components, such components are not limited by these terms. Such terms are used merely to distinguish one element from another element in the specification, regardless of the order in which such elements are manufactured. The same terms may not be used in the claims and may be substituted for "first," "second," "third," etc. in the order in which the elements of the claims were recited. Accordingly, in the following description, a first member may be a second member in the claims. In the present disclosure, unless specifically stated otherwise, components (e.g., transistor circuit 150, transistor circuit 350) of the same name may have the same or similar properties in different embodiments or figures, and may not be described again for brevity.
It should be understood that the following embodiments may be used to replace, reorganize, and mix features of several different embodiments to accomplish other embodiments without departing from the spirit of the present disclosure.
Fig. 1 is a schematic cross-sectional view illustrating a structure of an electronic device according to a first embodiment of the disclosure. Referring to fig. 1, an electronic device 100 may include an electronic structure with double sided redistribution process routing such that associated electronic or circuit units may be disposed on both sides of a substrate, but is not limited thereto. Specifically, the electronic device 100 may include a first metal layer 110, a first insulating layer 120, a second metal layer 130, a wiring layer 140, a transistor circuit 150, a second insulating layer 160, an electronic component 170, and a control circuit 180. The Transistor circuit 150 may include, for example, one or more transistors, such as Thin-Film transistors (TFTs), and the types of the plurality of transistors may be, for example, bottom gate (Bottom gate) transistors, top gate (Top gate) transistors, or Double gate (Double gate) transistors. The transistor circuit 150 may be electrically connected to the first metal layer 110 and/or the electronic component 170, but is not limited thereto. In the present embodiment, the first insulating layer 120 includes a first surface S1 and a second surface S2, where the first surface S1 is opposite to the second surface S2. The first surface S1 and the second surface S2 may be substantially parallel to a plane formed by the extension of the first direction D1 and the second direction D2, respectively. The first surface S1 faces a direction opposite to the third direction D3, and the second surface S2 faces the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other. In the present embodiment, the first insulating layer 120 may be a soft material, such as Polyimide (PI), but the disclosure is not limited thereto. In some embodiments, the first insulating layer 120 may also include a hard material (e.g., glass, ceramic, sapphire, or other suitable materials), a flexible material (e.g., polymer material, or other suitable materials), or a plastic circuit board, for example.
In the present embodiment, the first metal layer 110 has an opening 111 and is formed on the first surface S1 of the first insulating layer 120. The opening 111 may extend in the second direction D2 and be a slot structure. The second metal layer 130 is formed on the second surface S2 of the first insulating layer 120. In the present embodiment, the projection of the opening 111 onto the second surface S2 in the third direction D3 overlaps the projection of the second metal layer 130 onto the second surface S2 in the opposite direction to the third direction D3. It is noted that the first metal layer 110 may include a circuit component or a metal component structure of at least one of an electrode pad, a Bonding pad (Bonding pad), a wiring (Routing), or a Heat sink (Heat sink), and the second metal layer 130 may also include a circuit component or a metal component structure of at least one of an electrode pad, a Bonding pad, or a wiring. In this embodiment, the wiring layer 140 and the transistor circuit 150 may also be formed on the second surface S2 of the first insulating layer 120, wherein the wiring layer 140 may include a plurality of circuit traces. The transistor circuit 150 is electrically connected to the wiring layer 140. In some embodiments, the second metal layer 130, the wiring layer 140 and the transistor circuit 150 may be formed on the same layer on the second surface S2 of the first insulating layer 120, or formed between another plurality of insulating layers on the second surface S2 of the first insulating layer 120 to have different distances from the second surface S2 of the first insulating layer 120, respectively.
In the present embodiment, a second insulating layer 160 covering the second metal layer 130, the wiring layer 140, and the transistor circuit 150 is further formed on the second surface S2 of the first insulating layer 120. The electronic component 170 may be disposed on the second insulating layer 160. The electronic component 170 may be electrically connected to the first metal layer 110 and the second metal layer 130 through the conductive member 171 and the conductive member 172, but is not limited thereto. The conductive member 171 may be in the form of a Via (Via) penetrating the first insulating layer 120 and the second insulating layer 160, and the conductive member 172 may be in the form of a Via penetrating the second insulating layer 160, wherein the material of the conductive members 171, 172 may comprise a metallic conductive material, such as tin-lead alloy. In the present embodiment, the electronic component 170 may include a PN junction (PN junction) component, a Solar cell (Solar cell), an integrated circuit (Intergrated Circuit, IC), a Light-Emitting Diode (LED) component, a Sensor (Sensor), or the like, but the disclosure is not limited thereto. In some embodiments, the PN junction element includes a tunable capacitor (Variable capacitor), such as a varactor (varactor), but is not limited thereto. In some embodiments, the first metal layer 110 on the first surface S1 of the first insulating layer 120 may be further provided with or electrically connected to a passive component, a thin film battery (Thin film battery), a sensor, a light emitting diode, or the like, but the disclosure is not limited thereto. In the present embodiment, the control circuit 180 may be disposed on the carrier 181 and electrically connected to the wiring layer 140 via the conductive material 182 to be electrically connected to the transistor circuit 150 through the wiring layer 140, but is not limited thereto. The conductive material 182 may be anisotropic conductive paste (Anisotropic Conductive Film) or other suitable conductive material, but is not limited thereto. In the present embodiment, the control circuit 180 is configured to provide the electric signals such as the related control signals, the driving signals, etc. to the electronic component 170 via the transistor circuit 150 to control or drive the electronic component 170. Therefore, the electronic device 100 of the present embodiment may have a double-sided redistribution process wiring and an architecture provided with the transistor circuit 150, and the electronic component 170 disposed on the substrate may be controlled or driven by the transistor circuit 150. In one embodiment, the carrier 181 may include a flexible printed circuit (Flexible printed circuit, FPC) or other suitable circuit board, but is not limited thereto. In other embodiments, the control circuit 180 may be electrically connected to the transistor circuit 150, but not through the carrier plate 181 and/or the conductive material 182.
In the present embodiment, the electronic device 100 may include a display apparatus, an electromagnetic wave adjusting device, a sensing device or a splicing device, but is not limited thereto. The electronic device 100 may be a bendable or flexible electronic device. The electronic device 100 may include, for example, a liquid crystal (LED), and the LED may include, for example, an inorganic LED, an organic LED (organic light emitting diode, OLED), a sub-millimeter LED (mini LED), a micro LED (micro LED), or a Quantum Dot (QD) such as a QLED, a QDLED, a fluorescent (fluorescence), a phosphorescent (phosphorescence), or other suitable materials, and the materials thereof may be arranged and combined arbitrarily, but not limited thereto. The electromagnetic wave adjusting device can be used for receiving or transmitting electromagnetic waves, but is not limited thereto. The splicing device can be, for example, a display splicing device or a splicing device of an electromagnetic wave adjusting device, but is not limited thereto. It should be noted that the electronic device 100 may be any of the above arrangements, but is not limited thereto.
Fig. 2A and 2B are flowcharts illustrating a method for manufacturing an electronic device according to a first embodiment of the disclosure. Fig. 3A-3D are schematic cross-sectional views of the structure at various stages during the fabrication methods of fig. 2A and 2B. The following steps of the present embodiment may be implemented by corresponding one or a combination of multiple semiconductor processing means, and the following structures of fig. 3A to 3D formed by each intermediate step may each be implemented independently as some specific electronic devices, and are not limited to the electronic devices produced by the implementation to the final step. Referring to fig. 2A and 3A, the fabrication method of fig. 2A may result in an electronic device having an electronic structure with double sided redistribution process routing. In step S201, a carrier substrate 301 is provided, and the carrier substrate 301 may be, for example, a hard board or a soft board, which is not limited in the present disclosure. In step S202, a first metal layer 310 having an opening 311 is formed on a carrier substrate 301. The opening 311 may be formed by a semiconductor etching process, and the first metal layer 310 may also be formed by a semiconductor etching process to form metal or circuit components such as the electrode 312, the electrode 313, the electrode 314, the electrode 315, and the electrode 316 shown in fig. 3A. In an embodiment, one or more of the electrodes 312, 313, 314, 315, and 316 may be omitted, but is not limited thereto. In step S203, a first insulating layer 320 may be formed on the first metal layer 310 such that the first surface S1 of the first insulating layer 320 is in contact with the first metal layer 310. In step S204, the second metal layer 330 is formed on the first insulating layer 320 such that the second surface S2 of the first insulating layer 320 is in contact with the second metal layer 330. The first surface S1 is opposite to the second surface S2. It is noted that the projection of the opening 311 on the second surface S2 may overlap the projection of the second metal layer 330 on the second surface S2. In the present disclosure, "overlapping" may include both full overlapping and partial overlapping unless specifically stated otherwise. In step S205, a transistor circuit 350 may be formed on the first insulating layer 320. In step S206, the wiring layer 340 may be formed on the first insulating layer 320, and the wiring layer 340 may be electrically connected to the transistor circuit 350. In step S207, a second insulating layer 360 covering the second metal layer 330, the wiring layer 340, and the transistor circuit 350 is formed on the first insulating layer 320.
Referring to fig. 2A and 3B, in step S208, the electronic component 370 is disposed on the second insulating layer 360, and the electronic component 370 is electrically connected to the transistor circuit 350, the first metal layer 310 and the second metal layer 330. The electronic component 370 may be electrically connected to the first metal layer 310 and the second metal layer 330 via the conductive members 371 and 372 by a surface mount technology (Surface Mount Technology, SMT) process, and electrically connected to the transistor circuit 350 via additional traces. The conductive member 371 may be in the form of a via through the first insulating layer 320 and the second insulating layer 360, and the conductive member 372 may also be in the form of a via through the second insulating layer 360. In step S209, the control circuit 380 is electrically connected to the wiring layer 340. The control circuit 380 may be fabricated on the carrier 381 by using Chip On Film (COF) packaging technology or Chip On Glass (COG) packaging technology, wherein the carrier 381 may be a Film or a Glass. The wiring layer 340 may include Fan-out wiring (Fan-out wiring), and a via or opening above the wiring layer 340 may correspond to the second insulating layer 360, but is not limited thereto. In the present embodiment, the control Chip formed by the control circuit 380 and the carrier 381 may be placed above the wiring layer 340 in a Chip face down (Chip face down) manner, and the wiring layer 340 may be electrically connected by a surface bonding technique or bonding by anisotropic conductive adhesive (Anisotropic Conductive Film, ACF), but is not limited thereto. For example, the control circuit 380 may be electrically connected to the wiring layer 340 via the circuits on the carrier 381 and the conductive material 382, and electrically connected to the transistor circuit 350 through the wiring layer 340. The control circuit 380 may control or drive the electronic components 370 through the transistor circuit 350.
For example, the electronic component 370 may include a tunable capacitance, and the control circuit 380 may regulate the capacitance value of the tunable capacitance through the transistor circuit 350, so that the capacitance value between the first metal layer 310 and the second metal layer 330 may be correspondingly adjusted. Accordingly, an electromagnetic wave radiating member or an electromagnetic wave radiating modulator (Radiation modulator) may be formed between the opening 311 of the first metal layer 310 and the second metal layer 330, but is not limited thereto.
However, referring to fig. 3C, in some embodiments, step S208 may further include disposing another electronic component 370 'on the second insulating layer 360, and the electronic component 370' may be electrically connected to the second metal layer 330. Referring to fig. 2B and 3C, in step S210, a connection layer 302 covering the electronic components 370, 370' and the control circuit 380 is formed on the second insulating layer 360, and another carrier substrate 303 is disposed on the connection layer 302. The carrier substrate 303 may be a hard or soft plate, and the material of the connection layer 302 may, for example, comprise a temporary connection material. In step S211, the carrier substrate 301 is removed. The carrier substrate 301 may be removed, for example, by laser, heat, or light, and the disclosure is not limited thereto. In this regard, since the material of the first insulating layer 320 may be, for example, a flexible circuit board material, in order to reduce the damage to the structures and components on both sides of the first insulating layer 320 when the carrier substrate 301 is removed, another carrier substrate 303 and the connection layer 302 are formed on the second insulating layer 360 first, and then the carrier substrate 301 is removed. Referring to fig. 2B and 3D, in step S212, the passive element 390 may be disposed under the first metal layer 310, and the passive element 390 is electrically connected to the first metal layer 310. In step S213, the connection layer 302 and the carrier substrate 303 are removed. The connection layer 302 may be removed by laser, heating, or irradiation, for example, so that the carrier substrate 303 may be separated from the second insulating layer 360, but is not limited thereto. In addition, steps S210 to S213 of fig. 2B may also be implemented in the structure of fig. 3B to effectively remove the carrier substrate 301 of fig. 3B.
For example, the electronic component 370 may comprise an integrated circuit and the other electronic component 370' may comprise a solar cell. The integrated circuit may for example comprise an associated modulation circuit, such as a rectifier. The passive elements 390 may be thin film batteries. Therefore, the solar cell can provide electric energy to the integrated circuit through the first metal layer 310, and after voltage or current modulation, the modulated electric energy is provided to the second metal layer 330 to store the electric energy of the thin film battery, but the disclosure is not limited thereto.
Fig. 4 is a schematic cross-sectional view illustrating a structure of an electronic device according to a second embodiment of the disclosure. Fig. 4 is a schematic cross-sectional view illustrating a structure of an electronic device according to a second embodiment of the disclosure. The electronic device 400 may be an electronic structure with double sided redistribution process routing such that associated electronic or circuit units may be disposed on both sides of the substrate. Specifically, the electronic device 400 includes a first metal layer 410, a first insulating layer 420, a second metal layer 430, a wiring layer 440, a transistor circuit 450, a second insulating layer 460, an electronic component 470, and a control circuit 480. The transistor circuit 450 may, for example, include one or more transistors, and the type of the plurality of transistors may, for example, be bottom gate transistors, top gate transistors, or double gate transistors. In the present embodiment, the first insulating layer 420 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. In the present embodiment, the first insulating layer 420 may be a flexible circuit board material, but the disclosure is not limited thereto. In some embodiments, the material of the first insulating layer 420 may be, for example, the above hard material, flexible material, or plastic circuit board, which will not be described herein. It is noted that the transistor circuit 450 of the present embodiment may be a Die (Die) having a plurality of transistor circuits, so that the transistor circuit 450 is electrically connected to the wiring layer 440 by electrically connecting the transistor circuit 450 integrated on the Die to the wiring layer 440. For example, the transistor circuit 450 may include a substrate (not shown) and at least one transistor, the material of the substrate may include glass or other suitable material, the at least one transistor is disposed on the substrate, and the transistor circuit 450 is electrically connected with the wiring layer 440.
In the present embodiment, the first metal layer 410 may have an opening 411, and the first metal layer 410 is formed on the first surface S1 of the first insulating layer 420. For example, the opening 411 may extend in the second direction D2, and may be a slot structure, but is not limited thereto. The second metal layer 430 may be formed on the second surface S2 of the first insulating layer 420. In the present embodiment, the projection of the opening 411 onto the second surface S2 in the third direction D3 may overlap with the projection of the second metal layer 430 onto the second surface S2 in the opposite direction to the third direction D3. It is noted that the first metal layer 410 may include a circuit component or a metal component structure of at least one of an electrode pad, a bonding pad, a wire or a heat sink, and the second metal layer 430 may also include a circuit component or a metal component structure of at least one of an electrode pad, a bonding pad or a wire, but is not limited thereto. In this embodiment, a wiring layer 440 may also be formed on the second surface S2 of the first insulating layer 420, wherein the wiring layer 440 may include a plurality of circuit traces. In some embodiments, the second metal layer 430 and the wiring layer 440 may be formed on the same layer on the second surface S2 of the first insulating layer 420. In other embodiments, the second metal layer 430 and/or the wiring layer 440 may have different distances from the second surface S2 of the first insulating layer 420, and at least one insulating layer may be disposed between the second metal layer 430 and the wiring layer 440, but is not limited thereto.
In the present embodiment, a second insulating layer 460 covering the second metal layer 430 and the wiring layer 440 is further formed on the second surface S2 of the first insulating layer 420. The transistor circuit 450 and the electronic component 470 are disposed on the second insulating layer 460. The transistor circuit 450 may be electrically connected to the wiring layer 440 via the conductive member 451. The electronic component 470 can be electrically connected to the first metal layer 410 and the second metal layer 430 through the conductive members 471, 472. The conductive members 451, 471 may be in the form of through holes penetrating at least part of the first insulating layer 420 and/or at least part of the second insulating layer 460, and the conductive member 472 may be in the form of through holes penetrating the second insulating layer 460, wherein the conductive members 451, 471, 472 may be a metallic conductive material, such as tin-lead alloy. In the present embodiment, the electronic component 470 may include a PN junction component, a solar cell, an integrated circuit, a light emitting diode component, a sensor, other suitable electronic components, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the PN junction assembly includes a tunable capacitor. In some embodiments, the first metal layer 410 on the first surface S1 of the first insulating layer 420 may be further provided with or electrically connected to a passive component, a thin film battery, a sensor, a light emitting diode, or the like, but the disclosure is not limited thereto. In the present embodiment, the control circuit 480 may be disposed on the carrier 481 and electrically connected to the wiring layer 440 via the conductive material 482 so as to be electrically connected to the transistor circuit 450 through the wiring layer 440. In the present embodiment, the control circuit 480 is configured to provide electrical signals such as related control signals, driving signals, etc. to the electronic component 470 via the transistor circuit 450 to control or drive the electronic component 470. The transistor circuit 450 may be electrically connected to the first metal layer 410 and the electronic component 470, but is not limited thereto. Therefore, the electronic device 400 of the present embodiment may have a dual-sided redistribution process wiring and an architecture provided with the transistor circuit 450, and the electronic component 470 disposed on the substrate may be controlled or driven by the transistor circuit 450.
Fig. 5A and 5B are flowcharts illustrating a method for manufacturing an electronic device according to a second embodiment of the disclosure. Fig. 6A to 6D are schematic cross-sectional views of the structure at various stages during the manufacturing method of fig. 5A and 5B. The following steps of the present embodiment may be implemented by corresponding one or a combination of multiple semiconductor processing means, and the following structures of fig. 3A to 3D formed by each intermediate step may each be implemented independently as some specific electronic devices, and are not limited to the electronic devices produced by the implementation to the final step. Referring to fig. 5A and 6A, the manufacturing method of fig. 5A may produce an electronic device with a double-sided redistribution process wiring structure, but is not limited thereto. In step S501, a carrier substrate 601 is provided, and the carrier substrate 601 may be, for example, a hard board or a soft board, which is not limited in the present disclosure. In step S502, a first metal layer 610 having an opening 611 is formed on a carrier substrate 601. The opening 611 may be formed, for example, by a semiconductor etching process, and the first metal layer 610 may also be formed, for example, by a semiconductor etching process, as shown in fig. 6A, of metal or circuit components such as the electrode 612, the electrode 613, the electrode 614, the electrode 615, and the electrode 616, but is not limited thereto. In some embodiments, one or more of the above-described electrodes 613-616 may be omitted. In step S503, the first insulating layer 620 is formed on the first metal layer 610, for example, the first surface S1 of the first insulating layer 620 is in direct or indirect contact with the first metal layer 610, but is not limited thereto. In step S504, the second metal layer 630 may be formed on the first insulating layer 620, for example, the second surface S2 of the first insulating layer 620 is in direct or indirect contact with the second metal layer 630. The first surface S1 is opposite to the second surface S2. It is noted that the projection of the opening 611 on the second surface S2 may overlap with the projection of the second metal layer 630 on the second surface S2. In step S505, a wiring layer 640 is formed on the first insulating layer 620, and the wiring layer 640 is electrically connected to the transistor circuit 650. In step S506, a second insulating layer 660 covering the second metal layer 630 and the wiring layer 640 is formed on the first insulating layer 620.
Referring to fig. 5A and 6B, in step S507, the transistor circuit 650 is disposed on the second insulating layer 660 and electrically connected to the wiring layer 640. The transistor circuit 650 may be electrically connected to the wiring layer 640 through the conductive member 651 by using a surface bonding process, but is not limited thereto. The conductive element 651 may be in the form of a via extending through at least a portion of the second insulating layer 660. In step S508, the electronic component 670 may be disposed on the second insulating layer 660, and the electronic component 670 is electrically connected to the transistor circuit 650, the first metal layer 610, and the second metal layer 630. The electronic component 670 may be electrically connected to the first metal layer 610 and the second metal layer 630 through the conductive members 671 and 672 by a surface soldering process, and electrically connected to the transistor circuit 650 through additional traces, but is not limited thereto. The conductive member 671 may be in the form of a via that extends through at least a portion of the first insulating layer 620 and/or at least a portion of the second insulating layer 660, and the conductive member 672 may likewise be in the form of a via that extends through at least a portion of the second insulating layer 660. In step S509, the control circuit 680 may be electrically connected to the wiring layer 640. The control circuit 680, the conductive material 682, and the wiring layer 640 may be similar to the control circuit 180, the conductive material 182, and the wiring layer 140 described above, and will not be described again. For example, the electronic component 670 may be similar to the electronic component 170 described above, and will not be described herein.
However, referring to fig. 6C, in some embodiments, step S508 may further include disposing another electronic component 670 'on the second insulating layer 660, and the electronic component 670' is electrically connected to the second metal layer 630. Referring to fig. 5B and 6C, in step S510, a connection layer 602 covering the electronic components 370, 370', the transistor circuit 650, and the control circuit 680 is on the second insulating layer 660, and another carrier substrate 603 is disposed on the connection layer 602. Step S510 may be similar to step S210 described above, and will not be described again.
Fig. 7 is a schematic cross-sectional view illustrating a structure of an electronic device according to a third embodiment of the disclosure. Referring to fig. 7, the electronic device 700 may be an electronic structure with single-sided redistribution process wiring such that the associated electronic and circuit units may be disposed on one side of the substrate. Specifically, the electronic device 700 may include a first metal layer 710, a first insulating layer 720, a second metal layer 730, a wiring layer 740, a transistor circuit 750, a second insulating layer 760, a PN junction element 770, and a control circuit 780. The transistor circuit 750 may, for example, include one or more transistors, and the type of the plurality of transistors may, for example, be bottom gate transistors, top gate transistors, or double gate transistors. In the present embodiment, the first insulating layer 720 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. In the present embodiment, the first insulating layer 720 may be a flexible circuit board material, but the disclosure is not limited thereto. In some embodiments, the first insulating layer 720 may also be a material such as a hard, flexible, or plastic circuit board.
In the present embodiment, the first metal layer 710 and the second metal layer 730 may be formed on the second surface S2 of the first insulating layer 720. It is noted that the first metal layer 710 may include a circuit element or a metal element structure of at least one of an electrode, a pad, a wire, or a heat sink, and the second metal layer 730 may also include a circuit element or a metal element structure of at least one of an electrode, a pad, or a wire. In this embodiment, the wiring layer 740 and the transistor circuit 750 may also be formed on the second surface S2 of the first insulating layer 720. The transistor circuit 750 may be electrically connected to the wiring layer 740, and the wiring layer 740 includes a plurality of circuit traces. In some embodiments, the first metal layer 710, the second metal layer 730, the wiring layer 740, and the transistor circuit 750 may be formed on the same layer on the second surface S2 of the first insulating layer 720. In other embodiments, the first metal layer 710, the second metal layer 730, and the wiring layer 740 may have different distances from the second surface S2 of the first insulating layer 720, but is not limited thereto.
In the present embodiment, a second insulating layer 760 covering the first metal layer 710, the second metal layer 730, the wiring layer 740, and the transistor circuit 750 is further formed on the second surface S2 of the first insulating layer 720. The PN junction device 770 is disposed on the first surface S1 of the first insulating layer 720 and electrically connected to the first metal layer 710 and the second metal layer 730 through the conductive members 771 and 772. The conductive members 771, 772 may be in the form of vias through the first insulating layer 720, wherein the conductive members 771, 772 may be a metallic conductive material, such as tin-lead alloy. In this embodiment, the PN junction element 770 may include a tunable capacitance. In the present embodiment, the control circuit 780 is disposed on the carrier 781 and is electrically connected to the wiring layer 740 via the conductive material 782, so as to be electrically connected to the transistor circuit 750 through the wiring layer 740. In this embodiment, the control circuit 780 is configured to provide electrical signals such as related control signals, driving signals, etc. to the PN junction device 770 via the transistor circuit 750 to control or drive the PN junction device 770. Therefore, the electronic device 700 of the present embodiment may have a single-sided redistribution process wiring and a structure provided with the transistor circuit 750, and the PN junction device 770 disposed on the substrate may be controlled or driven by the transistor circuit 750.
Fig. 8 is a flowchart of a method for manufacturing an electronic device according to a third embodiment of the disclosure. Fig. 9A to 9D are schematic cross-sectional views of the structure at various stages during the manufacturing method of fig. 8. The following steps of the present embodiment may be implemented by corresponding one or a combination of multiple semiconductor processing means, and the structures of fig. 9A to 9D formed by the intermediate steps may be implemented as specific electronic devices, respectively, and are not limited to the electronic devices produced by the final steps. Referring to fig. 8 and 9A, the fabrication method of fig. 8 may result in an electronic device having an electronic structure with single sided redistribution process routing. In step S801, a carrier substrate 901 is provided, and the material of the carrier substrate 901 may include, for example, the material of the hard board or the soft board described above, which is not limited in the disclosure. In step S802, a first insulating layer 920 is formed on a carrier substrate 901. In step S803, a first metal layer 910 and a second metal layer 930 may be formed on the first insulating layer 920. The first metal layer 910 and the second metal layer 930 may be formed with metal or circuit components such as pads, heat sinks, wires, electrode pads, etc., for example, through a semiconductor etching process, but the disclosure is not limited thereto. In step S804, the transistor circuit 950 is formed on the first insulating layer 920, and the transistor circuit 950 is electrically connected to the second metal layer 930. In step S805, a wiring layer 940 is formed on the first insulating layer 920, and the wiring layer 940 is electrically connected to the transistor circuit 950. In step S806, a second insulating layer 960 covering the first metal layer 910, the second metal layer 930, the wiring layer 940, and the transistor circuit 950 is formed on the first insulating layer 920.
Referring to fig. 8 and 9B, in step S807, the control circuit 980 is electrically connected to the wiring layer 940. The control circuit 980 may be fabricated on the carrier 981, for example, using a flip-chip on film technique or a flip-chip on glass technique, wherein the material of the carrier 981 may comprise a film, glass, or other suitable material. The wiring layer 940 may include fan-out type wirings, and a via or opening over the wiring layer 940 may correspond to the second insulating layer 960. In the present embodiment, the control chip formed by the control circuit 980 and the carrier 981 may be placed above the wiring layer 940 with the chip facing down, and the wiring layer 940 may be electrically connected by a surface welding technique or by anisotropic conductive adhesive, but is not limited thereto. For example, the control circuit 980 may be electrically connected to the wiring layer 940 via the conductive material 982, and to the transistor circuit 950 through the wiring layer 940.
Referring to fig. 8 and 9C, in step S808, a connection layer 902 covering the control circuit 980 is formed on the second insulating layer 960, and another carrier substrate 903 is formed on the connection layer 902. The carrier substrate 903 may comprise a hard plate, a soft plate, or a combination thereof, and the connection layer 902 may comprise a temporary connection material, for example. In step S809, the carrier substrate 901 is removed. The carrier substrate 901 may be removed, for example, by laser, heating, or irradiation, which is not limited in this disclosure. In this regard, since the first insulating layer 920 may comprise the soft material, the other carrier substrate 903 and the connection layer 902 may be formed on the second insulating layer 960 before the carrier substrate 901 is removed, but not limited thereto, in order to reduce the damage to the structures and components on both sides of the first insulating layer 920 when the carrier substrate 901 is removed. In step S810, the electronic component 970 is disposed under the first insulating layer 920 (on the first surface S1), and the electronic component 970 is electrically connected to the first metal layer 910 and the second metal layer 930. The electronic component 970 can be electrically connected to the first metal layer 910 and the second metal layer 930 via the conductive members 971, 972, and electrically connected to the transistor circuit 950. The conductive members 971, 972 may be in the form of vias extending through at least a portion of the first insulating layer 920. In step S811, the connection layer 902 and the other carrier substrate 903 are removed. The connection layer 902 may be removed, for example, by laser, heat, or light, and the carrier substrate 903 may be separated from the second insulating layer 960.
Fig. 10 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fourth embodiment of the disclosure. Referring to fig. 10, an electronic device 1000 may include an electronic structure with single sided redistribution process routing such that associated electronic and circuit units may be disposed on one side of a first insulating layer 1020. Specifically, the electronic device 1000 includes a first metal layer 1010, a first insulating layer 1020, a second metal layer 1030, a wiring layer 1040, a transistor circuit 1050, a second insulating layer 1060, an electronic component 1070 (e.g., a PN junction component), and a control circuit 1080. The transistor circuit 1050 may include, for example, one or more transistors, and the type of the plurality of transistors may be, for example, a bottom gate transistor, a top gate transistor, or a double gate transistor. In the present embodiment, the first insulating layer 1020 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. In the present embodiment, the first insulating layer 1020 may comprise a soft material, but the disclosure is not limited thereto. In some embodiments, the first insulating layer 1020 may also comprise materials such as rigid, flexible, or plastic circuit boards. It is noted that the transistor circuit 1050 of the present embodiment may include a substrate (not shown) and at least one transistor disposed on the substrate. The at least one transistor may be electrically connected to the electronic component 1070 and/or the second metal layer 1030.
In the present embodiment, the first metal layer 1010 and the second metal layer 1030 may be formed on the second surface S2 of the first insulating layer 1020. It is noted that the first metal layer 1010 may include a circuit element or a metal element structure of at least one of an electrode, a pad, a wire or a heat sink, and the second metal layer 1030 may also include a circuit element or a metal element structure of at least one of an electrode, a pad or a wire, but is not limited thereto. In the present embodiment, the wiring layer 1040 may also be formed on the second surface S2 of the first insulating layer 1020. In some embodiments, the first metal layer 1010, the second metal layer 1030, and the wiring layer 1040 may be formed on the same layer on the second surface S2 of the first insulating layer 1020. In other embodiments, the first metal layer 1010, the second metal layer 1030, and the wiring layer 1040 may have different distances from the second surface S2 of the first insulating layer 1020, respectively.
In the present embodiment, a second insulating layer 1060 covering the first metal layer 1010, the second metal layer 1030, and the wiring layer 1040 is also formed on the second surface S2 of the first insulating layer 1020. The transistor circuit 1050 is disposed on the second insulating layer 1060, and the transistor circuit 1050 is electrically connected to the wiring layer 1040 via the conductive member 1051. The conductive member 1051 may be in the form of a via penetrating the second insulating layer 1060. An electronic component 1070 (e.g., a PN junction component) is disposed on the first surface S1 of the first insulating layer 1020. The conductive members 1071, 1072 may be in the form of vias through the first insulating layer 1020, wherein the conductive members 1071, 1072 may be a metallic conductive material, such as a tin-lead alloy. In the present embodiment, the control circuit 1080 is disposed on the carrier 1081 and can be electrically connected to the wiring layer 1040 via the conductive material 1082 to be electrically connected to the transistor circuit 1050 through the wiring layer 1040.
Fig. 11 is a flowchart of a method for manufacturing an electronic device according to a fourth embodiment of the disclosure. Fig. 12A to 12D are schematic cross-sectional views of the structure at various stages during the manufacturing method of fig. 11. The following steps of the present embodiment may be implemented by corresponding one or a combination of multiple semiconductor processing means, and the following structures of fig. 12A to 12D formed by the intermediate steps may each be implemented as some specific electronic devices independently, and are not limited to the electronic devices produced by the final steps. Referring to fig. 11 and 12A, the fabrication method of fig. 11 may result in an electronic device having an electronic structure with single sided redistribution process routing. In step S1101, a carrier substrate 1201 is provided, and the carrier substrate 1201 may be, for example, a hard board or a soft board, but the disclosure is not limited thereto. In step S1102, a first insulating layer 1220 is formed on a carrier substrate 1201. In step S1103, a first metal layer 1210 and a second metal layer 1230 are formed on the first insulating layer 1220. In step S1104, a wiring layer 1240 is formed on the first insulating layer 1220, and the wiring layer 1240 is electrically connected to the transistor circuit 1250. In step S1105, a second insulating layer 1260 covering the first metal layer 1210, the second metal layer 1230, and the wiring layer 1240 is formed on the first insulating layer 1220.
Referring to fig. 11 and 12B, in step S1106, a transistor circuit 1250 is disposed on the second insulating layer 1260 and electrically connected to the wiring layer 1240. The transistor circuit 1250 can be electrically connected to the wiring layer 1240 via the conductive member 1251. In step S1107, the control circuit 1280 is electrically connected to the wiring layer 1240. Referring to fig. 11 and 12C, in step S1108, a connection layer 1202 covering the control circuit 1280 and the transistor circuit 1250 is formed on the second insulating layer 1260, and another carrier substrate 1203 is formed on the connection layer 1202. In step S1109, the carrier substrate 1201 is removed. In step S1110, an electronic component 1270 (e.g., a PN junction device with adjustable capacitance) is disposed under the first insulating layer 1220 (on the first surface S1), and the electronic component 1270 is electrically connected to the first metal layer 1210 and the second metal layer 1230. In step S1111, the connection layer 1202 and the other carrier substrate 1203 are removed. The connection layer 1202 may be removed, for example, by laser, heat, or light, so that the carrier substrate 1203 may be separated from the second insulating layer 1260.
Fig. 13 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fifth embodiment of the disclosure. Referring to fig. 13, an electronic device 1300 may include an electronic structure with single sided redistribution process routing such that associated electronic and circuit elements may be disposed on one side of a first insulating layer 1320. Specifically, the electronic device 1300 includes a first metal layer 1310, a first insulating layer 1320, a second metal layer 1330, a wiring layer 1340, a transistor circuit 1350, a second insulating layer 1360, electronic components 1370 (e.g., PN junction components), and a control circuit 1380.
Specifically, the second metal layer 1330 and the wiring layer 1340 are formed on the second surface S2 of the first insulating layer 1320. In some embodiments, the second metal layer 1330 and the wiring layer 1340 may be formed on the same layer or different layers on the second surface S2 of the first insulating layer 1320. In this embodiment, a second insulating layer 1360 is also formed on the second surface S2 of the first insulating layer 1320 to cover the second metal layer 1330 and the wiring layer 1340, and the first metal layer 1310 having the opening 1311 is formed on the second insulating layer 1360. It is noted that the projection of the opening 1311 on the second surface S2 may overlap the projection of the second metal layer 1330 on the second surface S2. In the present embodiment, the transistor circuit 1350 can be electrically connected to the second metal layer 1330 through the conductive member 1351. In the present embodiment, the electronic component 1370 is disposed on the first surface S1 of the first insulating layer 1320, and may be electrically connected to the first metal layer 1310 and the second metal layer 1330 through the conductive elements 1371, 1372.
In the present embodiment, the control circuit 1380 is configured to provide electrical signals such as control signals and driving signals to the electronic component 1370 via the transistor circuit 1350 so as to control or drive the electronic component 1370. For example, the electronic component 1370 may include a PN junction device, and the control circuit 1380 may regulate the capacitance value through the transistor circuit 1350 such that the capacitance value between the first metal layer 1310 and the second metal layer 1330 may be adjusted accordingly. An electromagnetic wave radiation device or an electromagnetic wave radiation modulator may be formed between the opening 1311 of the first metal layer 1310 and the second metal layer 1330, for example. Fig. 14 is a schematic cross-sectional view illustrating a structure of an electronic device according to a sixth embodiment of the disclosure. Referring to fig. 14, the electronic device 1400 may be an electronic structure with single-sided redistribution process wiring such that related electronic and circuit units may be disposed on one side of the first insulating layer 1420. Specifically, the electronic device 1400 includes a first metal layer 1410, a first insulating layer 1420, a second metal layer 1430, a wiring layer 1440, a transistor circuit 1450, a second insulating layer 1460, an electronic component 1470, and a control circuit 1480.
In this embodiment, the transistor circuit 1450 may be electrically connected to the second metal layer 1430 via the conductive member 1452. The conductive element 1452 may be in the form of a via penetrating at least a portion of the first insulating layer 1420. In the present embodiment, the control circuit 1480 is configured to provide electrical signals such as control signals, driving signals, etc. to the electronic component 1470 via the transistor circuit 1450 to control or drive the electronic component 1470. In an embodiment, the control circuit 1480 may be electrically connected to the electronic component 1470 through the second metal layer 1430, the transistor circuit 1450, and/or the wiring layer 1440.
Fig. 15 is a schematic cross-sectional view illustrating a structure of an electronic device according to a seventh embodiment of the disclosure. Referring to fig. 15, an electronic device 1500 may be an electronic structure with single sided redistribution process routing. Specifically, the electronic device 1500 may include a first metal layer 1510, a first insulating layer 1520, a second metal layer 1530, a wiring layer 1540, a transistor circuit 1550, a second insulating layer 1560, an electronic component 1570, and a control circuit 1580.
In this embodiment, the transistor circuit 1550 may be formed on the first surface S1 of the first insulating layer 1520 and may be electrically connected to the PN junction device 1570 through the conductive member 1553. Conductive element 1553 is formed on first surface S1 of first insulating layer 1520 and connects transistor circuit 1550 with PN junction element 1570, wherein conductive element 1553 may comprise a metallic conductive material. In an embodiment, control circuitry 1580 may be electrically connected to electronic component 1570 through second metal layer 1530, transistor circuitry 1550, and/or routing layer 1540, but is not limited thereto.
In summary, the electronic device of the present disclosure can provide an electronic structure with single-sided or multi-sided redistribution process wiring and a transistor circuit, and can control or drive an electronic component disposed on a substrate through the transistor circuit, wherein the single-sided or multi-sided redistribution Cheng Buxian architecture of the present disclosure can be implemented through a less-layer architecture, so as to effectively reduce the size and the process cost of the electronic device.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, but not limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (9)

1. An electronic device, comprising:
a first metal layer having an opening;
a second metal layer;
a first insulating layer located between the first metal layer and the second metal layer; and
An electronic component electrically connected with the first metal layer and the first insulating layer is positioned between the electronic component and the first metal layer,
wherein the opening of the first metal layer overlaps the second metal layer.
2. The electronic device of claim 1, wherein the electronic component comprises an integrated circuit.
3. The electronic device of claim 1, wherein the second metal layer comprises a bond pad.
4. The electronic device of claim 1, further comprising:
the conductive piece penetrates through the first insulating layer and is electrically connected with the electronic component and the first metal layer.
5. The electronic device of claim 1, wherein the electronic component is electrically connected to the second metal layer.
6. The electronic device of claim 1, wherein the second metal layer is located between the electronic component and the first insulating layer.
7. The electronic device of claim 1, further comprising:
and the second insulating layer is positioned between the electronic component and the second metal layer.
8. The electronic device of claim 7, wherein the first insulating layer and the second insulating layer each have a different thickness.
9. The electronic device of claim 1, wherein the opening of the first metal layer overlaps the electronic component.
CN202310338305.2A 2019-07-29 2020-05-15 Electronic device Pending CN116207074A (en)

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