CN116207035A

CN116207035A - Memory forming method and memory

Info

Publication number: CN116207035A
Application number: CN202211166823.2A
Authority: CN
Inventors: 李辉辉; 张云森; 王桂磊; 赵超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2023-06-02
Anticipated expiration: 2042-09-23
Also published as: CN116207035B

Abstract

The disclosure provides a memory forming method and a memory, and relates to the technical field of semiconductors, wherein the memory forming method comprises the following steps: providing a base comprising a silicon substrate and an unpatterned stack disposed on the silicon substrate; patterning the stack to form a plurality of first trenches to isolate a plurality of memory cells; forming a first dielectric layer in the first groove; forming two concave grooves which are oppositely arranged and concave in the side wall of the silicon substrate; forming source lines in each inner concave groove respectively, and forming a second dielectric layer in the first groove; forming a plurality of columnar semiconductor layers based on the patterned stack; a gate electrode is formed around the side surface of the columnar semiconductor layer. In the method, the first dielectric layer is preferentially formed in the deeper first groove, only the substrate is needed to be etched in the forming process of the first groove, the etching environment is single and not complex, the process difficulty is reduced, metal impurities are fewer, and the isolation effect of the semiconductor is improved.

Description

Memory forming method and memory

Technical Field

The disclosure relates to the technical field of memories, and in particular relates to a memory forming method and a memory.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and thus, as the element density and integration level of the transistors are increased, in order to better adapt to the demand of scaling down the device size, semiconductor processes gradually start to transition from planar transistors to three-dimensional transistors with higher efficiency, such as Gate-All-Around (GAA) transistors, which include Lateral All-Around (LGAA) transistors and Vertical All-Around (VGAA) transistors with respect to a substrate, wherein the layout and connection of the VGAA devices may promote scaling of integrated circuits, but the VGAA process flow needs to be further simplified.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a memory forming method and a memory.

A first aspect of the present disclosure provides a method for forming a memory, the memory including a plurality of memory cells distributed in an array, each of the memory cells including a vertical gate-all-around transistor, and a source line connected to a source of the vertical gate-all-around transistor, a word line connected to a gate, and a bit line connected to a drain; the method comprises the following steps:

providing a substrate, wherein the substrate comprises a silicon substrate and an unpatterned laminated layer arranged on the silicon substrate, and the laminated layer comprises a first conductive layer, a semiconductor layer and a second conductive layer which are arranged in a laminated manner from bottom to top;

patterning the laminated layer to form a plurality of first grooves, wherein the first grooves extend to the silicon substrate along the direction perpendicular to the silicon substrate through the laminated layer, and the first grooves extend along the column direction in a plane parallel to the silicon substrate so as to isolate a plurality of storage units;

forming a first dielectric layer, wherein the first dielectric layer fills a silicon substrate area of the first groove to isolate a source line to be formed in a silicon substrate, and the top surface of the first dielectric layer is lower than the top surface of the silicon substrate by a preset distance, and the preset distance is smaller than the thickness of the source line to be formed; the first dielectric layer fills the first groove and then exposes part of the side wall of the silicon substrate;

Patterning the exposed side wall of the silicon substrate in the first groove to form two concave grooves which are arranged in opposite directions and concave in the side wall of the silicon substrate, wherein all or part of the area of the first conductive layer at the bottom of each of two adjacent laminated layers on the silicon substrate is exposed by the concave grooves;

forming source lines in each inner groove, wherein the source lines are connected with the first conductive layer exposed in the bottom of the laminated layer, and the two source lines are separated from each other and are not connected;

forming a second dielectric layer, wherein the second dielectric layer is positioned in the first groove, the second dielectric layer covers the exposed side wall of the source line and the top surface of the first dielectric layer, and the upper surface of the second dielectric layer is flush with the upper surface of the first conductive layer;

forming a second trench on the stack along a direction perpendicular to the first trench based on the patterned stack, the first trench and the second trench surrounding to form a plurality of columnar semiconductor layers;

and forming a grid electrode which surrounds and covers the side face of the columnar semiconductor layer.

The method for forming the unpatterned laminated layer arranged on the silicon substrate comprises the following steps:

Sequentially forming an unpatterned first conductive layer, a semiconductor layer and a second conductive layer on the silicon substrate by adopting an epitaxial process;

the first conductive layer and the second conductive layer are both N-type doped layers, and the semiconductor layer is a SiGe layer.

Patterning the laminated layer to form a plurality of first grooves, wherein the first grooves comprise:

forming a patterned first mask layer on the surface of the second conductive layer, and forming a side wall layer on the side wall of the first mask layer in the row direction parallel to the silicon substrate;

and removing the first mask layer, and sequentially etching the second conductive layer, the semiconductor layer and the first conductive layer by taking the plurality of side wall layers as masks, wherein the first mask layer extends to a set distance from the top surface of the silicon substrate to form a plurality of first grooves, and the set distance is more than or equal to 2 times of the thickness of the source line.

Wherein, forming a first dielectric layer includes:

forming a first dielectric layer in the first groove, wherein the first dielectric layer fills the first groove and covers the top surface of the second conductive layer;

and etching the first dielectric layer back to a preset distance lower than the top surface of the silicon substrate to form the first dielectric layer.

The patterning treatment is performed on the side wall of the silicon substrate exposed from the side wall of the first groove to form two opposite concave grooves which are concave in the side wall of the silicon substrate, and the patterning treatment comprises the following steps:

forming a protective layer on the side wall of the first groove and the top surface of the first dielectric layer by adopting an ALD (atomic layer deposition) process;

removing the protective layer on the side wall of the first groove by utilizing a selective etching process, and exposing the area from above the top surface of the first dielectric layer to below the top of the first conductive layer;

and etching the exposed silicon substrate and the first conductive layer by using the reserved protective layer as a mask to form the concave groove which is concave towards the side wall of the silicon substrate.

Wherein forming a second dielectric layer comprises:

depositing an insulating layer on the protective layer, the top surface of the first dielectric layer and the exposed surface of the source line;

and etching the protective layer and the insulating layer back to a position flush with the upper surface of the first conductive layer, wherein the reserved protective layer and the insulating layer form the second dielectric layer together.

The method for forming the columnar semiconductor layers comprises the following steps:

etching the side wall of the semiconductor layer by adopting a selective process to form a channel region in the laminated layer;

Forming an epitaxial layer of silicon on the surface of the channel region by adopting an epitaxial process, and selectively etching part of the epitaxial layer to form a channel layer, wherein the channel layer extends along a column direction in a plane parallel to the silicon substrate;

taking a second mask layer with a plurality of first grooves and second groove patterns as a mask, and etching until the top surface of the second dielectric layer is exposed based on the first grooves; etching the laminated layer and the channel layer to the top surface of the silicon substrate based on the second groove to form a second groove, wherein the reserved second conductive layer, the reserved channel layer and the reserved first conductive layer form columnar semiconductor layers, and the columnar semiconductor layers are distributed in an array; wherein a plurality of the first grooves extend in a direction parallel to the first grooves, and a plurality of the second grooves extend in a direction perpendicular to the first grooves.

Wherein forming the gate comprises:

covering a gate insulating layer on the surface of the channel layer in a conformal manner;

and forming an unpatterned second metal material on the surface of the gate insulating layer, patterning the second metal material to form the gate, and annularly covering the surface of the gate insulating layer by the gate.

A second aspect of the present disclosure provides a memory comprising

A plurality of memory cells, wherein a plurality of memory cell arrays are distributed on a silicon substrate, and each memory cell comprises a vertical gate-all-around transistor, a source line connected with a source electrode of the vertical gate-all-around transistor, a word line connected with a grid electrode and a bit line connected with a drain electrode;

a plurality of first trenches, each of the first trenches extending into the silicon substrate through a thickness of the vertical transistor; the distance between the bottom wall of the first groove and the top surface of the silicon substrate is greater than or equal to 2 times of the thickness of the source line.

An isolation layer located in the first trench, an upper surface of the isolation layer being flush with an upper surface of a source electrode of the vertical gate-all-around transistor to isolate the plurality of memory cells;

and the source line is positioned in two concave grooves which are oppositely arranged and concave in the side wall of the silicon substrate, and extends along the column direction parallel to the silicon substrate.

The isolation layer comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer and the second dielectric layer are overlapped in the first groove from bottom to top;

The distance between the highest point of the top surface of the first dielectric layer and the top surface of the silicon substrate is smaller than the thickness of the source line; the second dielectric layer covers the surface of the source line exposed by the first groove and the top surface of the first dielectric layer, and the upper surface of the second dielectric layer is flush with the upper surface of the source electrode.

In the memory forming method and the memory, the deeper first groove is formed in advance in the process of forming the memory so as to form the first dielectric layer in the substrate preferentially, and the substrate is only required to be etched in the process of etching the first groove, so that the etching environment is single and not complex, the etching process is simple, the forming process difficulty of the isolation layer is reduced, metal impurities are fewer, and the isolation effect is improved.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart illustrating a method of forming a memory according to an exemplary embodiment.

Fig. 2 is a schematic diagram illustrating a first mask layer formed during formation of a memory device according to an example embodiment.

Fig. 3 is a schematic structural diagram of a memory device according to an exemplary embodiment after a sidewall layer is formed during formation of the memory device.

Fig. 4 is a schematic diagram illustrating a structure after forming a first trench in a process of forming a memory according to an exemplary embodiment.

Fig. 5 is a schematic diagram of a structure of a memory filled with a first dielectric layer during formation of the memory according to an exemplary embodiment.

Fig. 6 is a schematic diagram illustrating a structure after a first dielectric layer is formed during formation of a memory according to an exemplary embodiment.

Fig. 7 is a schematic diagram showing a structure after forming a protective layer in the formation process of a memory according to an exemplary embodiment.

Fig. 8 is a schematic diagram showing a structure after removing a part of the protective layer in the formation process of the memory according to an exemplary embodiment.

Fig. 9 is a schematic diagram illustrating a structure after forming a concave trench in a process of forming a memory according to an exemplary embodiment.

Fig. 10 is a schematic diagram illustrating a structure after source lines are formed during formation of a memory according to an exemplary embodiment.

Fig. 11 is a schematic diagram illustrating a structure of a memory filled with a second dielectric layer during formation of the memory according to an exemplary embodiment.

Fig. 12 is a schematic diagram illustrating a structure after forming a second dielectric layer during formation of a memory according to an exemplary embodiment.

Fig. 13 is a schematic view showing a structure of forming a sacrificial semiconductor layer in the formation process of a memory device according to an exemplary embodiment.

Fig. 14 is a schematic diagram illustrating a structure after forming a channel region during formation of a memory device according to an exemplary embodiment.

Fig. 15 is a schematic diagram showing a structure after an epitaxial layer is formed in the formation process of a memory according to an exemplary embodiment.

Fig. 16 is a schematic diagram showing a structure after forming a channel layer in the formation process of a memory according to an exemplary embodiment.

Fig. 17 is a schematic diagram showing a structure after a filling layer is formed in the formation process of a memory according to an exemplary embodiment.

Fig. 18 is a pattern distribution diagram of a second mask layer in the Y direction during formation of a memory device according to an exemplary embodiment.

Fig. 19 is a schematic diagram showing a structure after etching the stack and the channel layer in the Y direction during formation of the memory device according to an exemplary embodiment.

Fig. 20 is a pattern distribution diagram of a first mask layer in an X direction during formation of a memory device according to another exemplary embodiment.

Fig. 21 is a schematic diagram illustrating a structure after etching the stack and the first trench layer in the X-direction during formation of the memory device according to an exemplary embodiment.

Fig. 22 is a schematic diagram showing a structure after removing the sacrificial semiconductor layer in the first trench during formation of the memory device according to an exemplary embodiment.

Fig. 23 is a schematic diagram showing a structure of a gate insulating layer during formation of a memory according to an exemplary embodiment.

Fig. 24 is a schematic structural view of a second metal material layer during formation of a memory device according to an example embodiment.

Fig. 25 is a schematic diagram illustrating a structure after forming a third mask layer in a process of forming a memory according to an exemplary embodiment.

Fig. 26 is a schematic diagram showing a structure of a gate in a Y direction during formation of a memory according to an exemplary embodiment.

Fig. 27 is a schematic diagram showing the structure of gates and word lines in the X direction during formation of a memory according to an exemplary embodiment.

Fig. 28 is a schematic diagram illustrating a structure after a dielectric layer is formed during formation of a memory according to an exemplary embodiment.

Fig. 29 is a schematic view showing a structure of a contact hole in an X direction during formation of a memory according to an exemplary embodiment.

Fig. 30 is a schematic diagram showing a structure of a memory according to an exemplary embodiment.

Reference numerals:

10. a first mask layer; 11. a side wall layer; 100. a substrate; 110. a substrate; 111. a top surface of the substrate; 121. a first conductive layer; 122. a semiconductor layer; 123. a second conductive layer; 124. a sacrificial semiconductor layer; 125. a channel region; 1251. a first recess; 1252. a second notch; 120. laminating; 126. a first sidewall; 127. a second sidewall; 130. a first trench; 150. an opening;

20. a third mask layer; 21. spin-coating a hard mask layer; 22. a photoresist layer; 210. a third groove; 30. a bit line; 300. an isolation layer; 310. a first dielectric layer; 311. a top surface of the first dielectric layer; 320. a second dielectric layer; 321. a protective layer; 322. an insulating layer; 400. a source line; 410. a first metal material; 420. a metal silicide; 50. a second mask layer; 510. a first groove; 520. a second groove; 60. a dielectric layer; 61. a filling layer; 62. a second filler layer; 600. a channel layer; 610. a first channel layer; 620. a second channel layer; 70. an epitaxial layer; 800. a gate; 810. a second metal material; 90. a dielectric layer; 900. and a columnar semiconductor layer.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In an exemplary embodiment of the present disclosure, a method for forming a memory is provided, as shown in fig. 1, fig. 1 shows a flowchart of the method for forming a memory provided in accordance with an exemplary embodiment of the present disclosure, fig. 2 to fig. 30 are schematic diagrams of respective stages of the method for forming a memory, and the method for forming a memory is described below with reference to fig. 2 to fig. 30. The memory structure formed in this embodiment does not constitute a complete memory, but is merely a process of forming memory cells of the memory.

The present embodiment is not limited to the memory, and the transistor in the memory will be described by taking a vertical gate-all-around transistor as an example, and the vertical gate-all-around transistor can be applied to the driving transistors of the logic devices and the memory devices such as DRAM (Dynamic Random Access Memory) and MRAM (Magnetic Random Access Memory), but the present embodiment is not limited thereto. The memory includes a plurality of memory cells distributed in an array, as shown in FIG. 30, the memory is illustratively shown to include two memory cells 80, each memory cell 80 including a vertical gate-all transistor, and a source line 400 connected to the source of the vertical gate-all transistor (formed of the first conductive layer 121), a word line 500 connected to the gate 800, and a bit line 30 connected to the drain (formed of the second conductive layer 123)

As shown in fig. 1, an exemplary embodiment of the present disclosure provides a method for forming a memory, as shown in fig. 30. The method for forming the memory comprises the following steps:

step S110: a substrate is provided, the substrate including a silicon substrate and an unpatterned stack disposed on the silicon substrate, the stack including a first conductive layer, a semiconductor layer, and a second conductive layer disposed in a bottom-to-top stack.

Illustratively, as shown in fig. 3, the substrate 100 serves as a support member for supporting other components disposed thereon as a platform for subsequent processes. The base 100 includes a silicon substrate 110, and the silicon substrate 110 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.

The base 100 further includes a stack 120 of a plurality of unpatterned material layers on the silicon substrate 110, the stack 120 including a first conductive layer 121, a semiconductor layer 122, and a second conductive layer 123 stacked in this order from bottom to top. Stack 120 is the initial material layer of the vertical gate-all-around transistor formed in a subsequent process.

Illustratively, the first conductive layer 121 and the second conductive layer 123 are each an N-type doped material layer (n+si layer) formed by doping N impurities with monocrystalline silicon, and the doping concentration may be doped according to actual requirements. The semiconductor layer 122 is, for example, a silicon germanium material layer (SiGe layer). Illustratively, the N-type impurity may be phosphorus or arsenic.

The first conductive layer 121 may be a material layer of a source of the vertical gate-all-around transistor, the second conductive layer 123 may be a material layer of a drain of the vertical gate-all-around transistor, and the semiconductor layer 122 may be a space occupying layer of a channel of the vertical gate-all-around transistor.

In some exemplary embodiments, as shown in fig. 3, an unpatterned first conductive layer 121, semiconductor layer 122, and second conductive layer 123 are formed sequentially on a silicon substrate 110 using an epitaxial process to form an unpatterned stack 120 on the silicon substrate 110 in preparation for subsequent formation of a vertical gate-all-around transistor,

in this embodiment, an epitaxial process is used to form an initial material layer for forming a vertical gate-all-around transistor, and the process is simple, thereby simplifying the VGAA formation process. In addition, the epitaxial process is adopted to grow the laminated layer, so that the epitaxial flatness of each layer and the thickness of each layer can be uniformly controlled, and the thickness of the semiconductor layer can be controlled, so that the channel length and the thickness of a channel of a vertical gate-all-around transistor formed by a subsequent process are controlled, the uniformity of the channel is improved, and the process precision of the vertical gate-all-around transistor and the performance of each storage unit in a memory are improved. In addition, the channel of VGAA extends in the direction perpendicular to the surface of the silicon substrate, which is beneficial to improving the area utilization efficiency of the silicon substrate, and therefore, is beneficial to realizing further feature size reduction.

Illustratively, the thickness of the first conductive layer 121 may be controlled to 5 to 20nm, the thickness of the second conductive layer 123 may be controlled to 5 to 20nm, and the thickness of the semiconductor layer 122 may be controlled to 5 to 20nm.

Step S120: the stacked layer is subjected to patterning treatment to form a plurality of first grooves, the first grooves penetrate through the stacked layer and extend to the silicon substrate along the direction perpendicular to the silicon substrate, and the first grooves extend along the column direction in the plane parallel to the silicon substrate so as to isolate a plurality of memory cells.

Illustratively, as shown in fig. 3 and 4, X may be a row direction in a plane parallel to the silicon substrate 110 shown in fig. 4, and Z may be a direction along the top surface of the silicon substrate 110 to the bottom surface of the silicon substrate 110 in fig. 4, the X direction and the Z direction being perpendicular to each other.

Referring to fig. 4, the unpatterned stack 120 on the silicon substrate 110 is patterned using a self-aligned etch process to form a first trench for isolating a plurality of memory cells.

As shown in fig. 4, in the X direction, a plurality of first trenches 130 are spaced apart, each first trench 130 extending through the thickness of the stack 120 and extending in the Z direction to a set distance H1 from the top surface of the silicon substrate 110. As shown in fig. 11, the distance from the bottom wall of the first trench 130 to the top surface of the silicon substrate 110 is denoted as H1 (based on the position shown in the drawing), and H1 is 2 times greater than or equal to the thickness H3 of the source line, so that the plurality of first trenches effectively isolate a plurality of memory cells to be formed later.

In this embodiment, during the process of forming the vertical gate-all-around transistor of the accessor, the deeper first trench 130 is preferentially formed in the substrate 100, so that the bottom wall of the first trench 130 is located deeper in the silicon substrate 110, and during the process of etching the first trench 130, the environment of the silicon substrate 110 is simple and uncomplicated, so that the etching process is simple, the process difficulty of forming the isolation layer by the subsequent process is reduced, and the metal impurities in the first trench are fewer, thereby effectively improving the isolation effect

In this embodiment, as shown in fig. 2-4, patterning the unpatterned stack 120 disposed on the silicon substrate 110 using a self-aligned etch process may include:

as shown in fig. 2, a patterned first mask layer 10 is formed on the top surface of the second conductive layer 123. The first mask layer 10 includes a plurality of mask units (not shown in the drawings), which are spaced apart in a row direction X parallel to the silicon substrate, extend in a column direction Y parallel to the silicon substrate,

as shown in fig. 3, a sidewall layer 11 of a preset thickness is formed on the sidewall of each mask unit of the first mask layer 10, and then the first mask layer 10 is removed. Illustratively, a silicon oxide material may be used as a mask unit, and silicon nitride may be used as the sidewall layer 11, so that the capability of the self-aligned etching hole etching process is enhanced by using a double-layer sidewall layer, i.e., a silicon nitride sidewall, to improve the quality of the first trench etching, and facilitate reducing the space between two adjacent memory cells.

As shown in fig. 4, the stack 120 is etched along the Z direction from the top surface to the bottom surface of the silicon substrate 110 using the plurality of sidewall layers 11 as masks. Referring to fig. 4, the second conductive layer 123, the semiconductor layer 122 and the first conductive layer 121 are sequentially etched from top to bottom and extend to a position at a set distance H1 from the bottom surface of the silicon substrate to stop etching, thereby forming a plurality of first trenches 130, and the patterned stack 120 is used to form vertical gate-all-around transistors of each memory cell.

In the embodiment, under the condition of defining smaller feature sizes by adopting a self-aligned etching process, the condition that the feature sizes become smaller can be reduced, the etching precision can be ensured, and the process precision of the memory is improved.

As shown in fig. 4, the bottom wall of the first trench 130 is located at a set distance H1 from the top surface of the silicon substrate 110, and the set distance H1 is, for example, 100nm to 200nm, for example, 120nm, 150nm.

Step S130: forming a first dielectric layer, wherein the first dielectric layer fills the first groove to isolate a source line to be formed, the distance between the top surface of the first dielectric layer and the top surface of the silicon substrate is smaller than the thickness of the source line to be formed, and part of the side wall of the silicon substrate is exposed after the first dielectric layer fills the first groove;

As shown in fig. 6, the first dielectric layer 310 is located in the first trench 130, and the first trench 130 exposes a portion of the surface area of the silicon substrate 110. Wherein, the top surface 311 of the first dielectric layer 310 is located at a position lower than the preset distance D1 of the top surface 111 of the silicon substrate 110, and the preset distance D1 is smaller than the thickness H3 of the source line formed later (refer to fig. 11). Referring to fig. 6, the height H2 of the first dielectric layer 310 is lower than the height H1 (shown in fig. 4) from the bottom wall of the first trench 130 to the top surface of the silicon substrate, and thus, the difference between H1 and H2 is smaller than H3.

Illustratively, the forming of the first dielectric layer may include the steps of:

referring to fig. 4 to 6, a first dielectric layer 310 may be deposited into the first trench 130 by using a suitable deposition process such as chemical vapor deposition, low-pressure chemical vapor deposition, physical vapor deposition, etc., until the first trench 130 is filled, the first dielectric layer 310 may also cover the top surface of the stack 120, then an etching back process may be performed on the redundant first dielectric layer 310, to remove the top surface of the stack 120 and a part of the first dielectric layer 310 in the first trench 130, and etching back until the highest point of the top surface 311 of the first dielectric layer 310 is lower than the top surface 111 of the silicon substrate 110 by a preset distance D1, and then etching is stopped, wherein a part of the first dielectric layer 310 is retained in the first trench 130 to isolate the memory cell.

As shown in fig. 9, a certain loss is generated on the top of the first dielectric layer 310 during the subsequent formation of the concave groove, so that the top surface of the first dielectric layer 310 is curved, for example, arc-shaped. In order not to influence the isolation effect, in the process of forming the first dielectric layer, the etching degree of the back etching first dielectric layer can be controlled, so that the preset distance D1 from the top surface of the back etching first dielectric layer to the top surface of the silicon substrate meets the requirement, and the distance from the highest point of the top surface of the finally formed first dielectric layer to the top surface of the silicon substrate is smaller than the thickness of the source line. The preset distance D1 is in the range of 5nm to 30nm, for example.

The highest point of the top surface of the first dielectric layer may be located on the top surface of the first dielectric layer, and the point with the greatest distance from the bottom wall of the first trench, for example, is the top point of the top of the first dielectric layer.

Illustratively, the first dielectric layer 310 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, for example, the first dielectric layer 310 is silicon oxide.

In this embodiment, as shown in fig. 6, the first dielectric layer 310 is preferentially formed in the first trench 130 located in the silicon substrate 110, and since the etched first trench 130 has almost no metal impurities, the first dielectric layer 310 having a good isolation effect is formed, thereby improving the isolation effect between memory cells.

As shown in fig. 6, a region of the first trench 130 not filled with the first dielectric layer 310 exposes a portion of the sidewalls of the silicon substrate 110, and sidewalls of the first conductive layer 121, the semiconductor layer 122, and the second conductive layer 123.

Step S140: and patterning the side wall of the silicon substrate exposed in the first groove to form two opposite concave grooves which are concave in the side wall of the silicon substrate, wherein the concave grooves expose the bottoms of adjacent laminated layers on the silicon substrate.

As shown in fig. 6, the first dielectric layer 310 plays a role of isolating the surface of the covered silicon substrate 110, and the areas where the first trenches 130 are not filled expose the sidewalls of the stack 120 and part of the sidewall surface of the silicon substrate 110. As shown in fig. 8 and 9, the surface area of the silicon substrate 110 exposed along the bottom of the stack 120 to the top surface of the first dielectric layer 310 may be etched to form concave trenches 150 in the silicon substrate 110 on both sides of the top of the first dielectric layer 310.

Referring to fig. 9, the concave groove 150 formed in the silicon substrate is indented inward toward the sidewall of the silicon substrate 110, and two concave grooves 150 adjacent to each other are disposed opposite under the stack 120 in preparation for the subsequent formation of the source line.

Illustratively, the patterning process is performed on the sidewall of the silicon substrate exposed by the sidewall of the first trench, and the process of forming two oppositely disposed concave trenches concave in the sidewall of the silicon substrate may be as follows: as shown in fig. 6 and 7, a protective layer 321 is formed on the surface of the stack 120 and the top surface of the first dielectric layer 310 in advance by using an ALD (Atomic Layer Deposition) process, and the protective layer 321 covers the top surface of the stack 120 and the sidewalls of the first trench 130, so that the protective layer 321 protects the top surface of the stack 120 and the sidewalls of the first trench 130 in a subsequent etching process. The protective layer 321 does not fill the first trench 130, and a slit 131 is formed in the first trench 130.

Referring to fig. 7 and 8, next, the protective layer 321 covering the top surface of the first dielectric layer 310 to the bottom of the first conductive layer 121 may be removed using a selective etching process, thereby exposing the bottom of the stack 120 and a portion of the sidewall surface of the silicon substrate 110. Illustratively, the protective layer 321 is made of an oxide, nitride, or the like, for example, the protective layer 321 is silicon oxide.

As shown in fig. 8 and 9, with the remaining protective layer 321 as a mask, etching is performed along the exposed sidewall of the first conductive layer 121 and the sidewall surface of the silicon substrate 110 in a direction in which the sidewall of the silicon substrate 110 is recessed, forming a concave trench 150 recessed into the silicon substrate 110 toward the sidewall of the first trench 130, the concave trench 150 extending in a column direction (a direction perpendicular to the plane of the paper, i.e., a direction parallel to the plane of the silicon substrate and perpendicular to the X direction) parallel to the plane of the silicon substrate 110, and the concave trench 150 exposing a part of the surface of the silicon substrate 110 and the bottom surface of the first conductive layer 121. The cross-section of each concave groove 150 may be arc-shaped, and two concave grooves 150 located under the same lamination 120 are isolated from each other and not communicated with each other.

In other embodiments, the cross section of the concave groove may have other shapes, such as a semicircle, a rectangle, etc., which are not particularly limited herein.

Referring to fig. 9, in the process of forming the concave groove 150, loss occurs in different situations to the exposed top surface of the first dielectric layer 310, and, for example, as shown in fig. 9, an arc structure appears on the top of the first dielectric layer 310.

Step S150: source lines are respectively formed in each inner concave groove, the source lines are connected with the bottom of the laminated layer, and the two source lines are separated from each other and are not connected.

As shown in fig. 10, a first metal material 410 may be deposited in the recessed trench 150 using atomic layer deposition (Atomic Layer Deposition, ALD) or other deposition process, the first metal material 410 covering the surface of the recessed trench 150 and filling the area of the recessed trench 150 and being in contact with the exposed surface of the first conductive layer 121.

Then, the first metal material 410 is annealed at a high temperature, and the first metal material 410 in contact with the surface of the silicon substrate 110 is subjected to a process such as heating and annealing at a high temperature, and reacts with the surface of the silicon substrate 110 to generate a metal silicide 420, and the unreacted first metal material 410 and the metal silicide 420 together form the source line 400, as shown in fig. 10. For example, when the silicon substrate 110 is a silicon material, the metal silicide 420 is a hard compound formed by the first metal material 410 and silicon, has stable chemical composition and good oxidation resistance, and can reduce interface resistance.

Referring to fig. 10, two source lines 400 under the same stack 120 are both in contact connection with both ends of the bottom of the first conductive layer 121 in the stack 120, and the two source lines 400 are spaced apart by the silicon substrate 110. In the X-direction, the first dielectric layer 310 isolates the source line 400 under two adjacent stacks 120 to isolate subsequently formed memory cells.

Referring to fig. 10, in an exemplary process of forming the first metal material 410 in the concave groove 150, the first metal material 410 is also deposited in other areas outside the concave groove 150, so that in this embodiment, a selective atomic layer deposition process is used to selectively deposit the first metal material 410 in the concave groove 150, so that the first metal material 410 is effectively grown on the surface of the concave groove 150 by a locally selective ALD process, thereby achieving the purpose of rapidly growing the first metal material 410 in the concave groove 150, and reducing the time and the process time of the back etching process.

Illustratively, the first metallic material includes, for example, any one including titanium (Ti), tantalum (Ta), hafnium (Hf), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), or any one of alloys thereof.

Step S160: and forming a second dielectric layer, wherein the second dielectric layer is positioned in the first groove, the second dielectric layer covers the exposed side wall of the source line and the top surface of the first dielectric layer, and the upper surface of the second dielectric layer is flush with the upper surface of the first conductive layer.

Referring to fig. 10 and 11, the remaining protective layer 321 exposes sidewalls of the source line 400 and a top surface of the first dielectric layer 310. To completely isolate the source line 400, the second dielectric layer 320 is continuously formed on the top surface of the first dielectric layer 310 to form the complete isolation layer 300 (refer to fig. 12).

Illustratively, the step of forming the second dielectric layer may be as follows:

as shown in fig. 10 and 11, the CVD (Chemical Vapor Deposition ) process is used to continue depositing the insulating layer 322 in the region above the top surface of the first dielectric layer 310. Illustratively, the insulating layer 322 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride, e.g., the insulating layer 322 is silicon oxide. Illustratively, the insulating layer 322 and the protective layer 321 may be the same or different materials.

As shown in fig. 10 and 11, the insulating layer 322 fills the slit 131 region in the first trench 130 and covers the exposed sidewall of the source line 400, the top surface of the first dielectric layer 310, and the top surface of the protective layer 321, and the insulating layer 322 covering the stack 120 and the first trench 130 may be processed using a CMP (Chemical Mechanical Polishing ) process to form a planar surface in preparation for a subsequent process.

Referring to fig. 11 and 12, the insulating layer 322 and the protective layer 321 are etched back to a position where the top surfaces of the protective layer 321 and the insulating layer 322 are flush with the top surface of the first conductive layer 121, a portion of the protective layer 321 and a portion of the insulating layer 322 located in the first trench 130 (shown in fig. 10) are left, the remaining protective layer 321 and insulating layer 322 form a second dielectric layer 320 in the first trench 130, and an upper surface of the second dielectric layer 320 is flush with an upper surface of the first conductive layer 121.

Referring to fig. 12, the first dielectric layer 310 and the second dielectric layer 320 may be used together as an isolation layer 300 to isolate a memory cell formed in a subsequent process. The isolation layer 300 extends along a column direction in a plane parallel to the silicon substrate 110, and the top of the isolation layer 300 is connected to the sidewall of the first conductive layer 121. Illustratively, the upper surface of the isolation layer 300 is flush with the upper surface of the first conductive layer 121.

Step S170: forming a second trench on the stack along a direction perpendicular to the first trench based on the patterned stack, the first trench and the second trench surrounding to form a plurality of columnar semiconductor layers.

As shown in fig. 12, after the isolation layer 300 is formed in the first trench 130 (shown in fig. 6), the patterned stack is divided to prepare for a subsequent process to form a pillar-shaped semiconductor layer. In this embodiment, the forming process of the plurality of columnar semiconductor layers may include: as shown in fig. 12 and 13, after the isolation layer 300 is formed in the first trench 130 (shown in fig. 6), the sidewalls of the second conductive layer 123 and the sidewalls of the semiconductor layer 122 are exposed by the unfilled first trench 130.

As shown in fig. 12 and 14, the semiconductor layer 122 is etched along the exposed sidewall of the semiconductor layer 122, and is recessed and recessed toward the sidewall of the stack 120 until the semiconductor layer 122 reaches a set width, so that a channel region 125 is formed between the first conductive layer 121, the semiconductor layer 122, and the second conductive layer 123, and the channel region 125 is a region for forming the channel layer 600 (refer to fig. 16) in a subsequent process.

As shown in fig. 13, the cross-sectional width D2 of the semiconductor layer 122 is smaller than the cross-sectional width of the second conductive layer 123, the remaining semiconductor layer 122 is located between the first conductive layer 121 and the second conductive layer 123, a sacrificial semiconductor layer 124 is formed, the cross-sectional width of the sacrificial semiconductor layer 124 is denoted as D2 and the cross-sectional width of the second conductive layer 123 is denoted as D3 in a row direction X in a plane parallel to the silicon substrate, wherein D3X 2/5 < D2 < D3X 4/5. Illustratively, the sacrificial semiconductor layer 124 is located in the middle of the stack 120, with the sacrificial semiconductor layer 124 extending in a column direction Y (shown in fig. 2) in a plane parallel to the silicon substrate.

Referring to fig. 13 and 14, a channel region 125 is formed between the sidewall of the sacrificial semiconductor layer 124 and the first and second

conductive layers

121 and 123, and the sacrificial semiconductor layer 124 has a first sidewall 126 and a second sidewall 127, the first and

second sidewalls

126 and 127 being opposite to each other in a row direction X in a plane parallel to the silicon substrate. Wherein the first sidewall 126 forms a first recess 1251 with the top surface of the first conductive layer 121 and the bottom surface of the second conductive layer 123; the second sidewall 127 forms a second recess 1252 with the top surface of the first conductive layer 121 and the bottom surface of the second conductive layer 123, the opening of the first recess 1251 facing opposite to the opening of the second recess 1252; the first recess 1251 and the second recess 1252 together form a channel region 125, thereby forming a multi-channel region structure within the stack 120 that facilitates the fabrication of high performance vertical gate-all-around transistors.

As shown in fig. 15, an epitaxial layer 70 of silicon is formed on the surfaces of the first conductive layer 121, the sacrificial semiconductor layer 124, and the second conductive layer 123 using an epitaxial process; epitaxial layer 70 covers the surface of the non-channel region, including the surface area of second conductive layer 123, as well as the surface of channel region 125. As shown in fig. 16, a portion of the epitaxial layer 70 covering the non-channel region is selectively etched, leaving the epitaxial layer 70 between the first conductive layer 121 and the second conductive layer 123, forming a channel layer 600, the channel layer 600 extending in a column direction parallel to the silicon substrate 110. Illustratively, the channel layer 600 may also be recessed inwardly of the sidewalls of the stack 120.

As shown in fig. 14 and 16, a first channel layer 610 is formed at the first recess 1251; forming a second channel layer 620 at the second recess 1252; wherein the first channel layer 610 and the second channel layer 620 together constitute the channel layer 600. In this step, a vertical gate-all-around transistor structure having multiple channels is formed by forming multiple channels in the multiple channel region, thereby improving the driving capability and the turn-on speed of the vertical gate-all-around transistor.

Illustratively, a silicon material is selected as the epitaxial layer to form a silicon epitaxial layer as the channel layer, with the silicon epitaxial layer being used as the channel layer to facilitate control of the thickness of the channel layer and the channel length.

Illustratively, as shown in fig. 16, the first channel layer 610 of the square pillar structure may be formed by controlling the deposition thickness of the first channel layer 610 such that the sidewalls of the first channel layer 610 are on the same line in the direction from the top surface of the silicon substrate to form a gate electrode of uniform thickness around the surface of the first channel layer 610 in a subsequent process. Similarly, the second channel layer 620 has the same structure as the first channel layer 610, so that a gate having a uniform thickness is formed on the surface of the second channel layer 620 in a subsequent process, which is advantageous for controlling the transistor.

Then, the stack and the channel layer are etched to the top surface of the silicon substrate using a self-aligned etch process. Referring to fig. 17 to 21, a filling layer 61 is formed in advance on the surface of the stack 120 and in the first trench 130, so that an unfilled region is filled up with the filling layer 61, a patterned second mask layer 50 is formed on the surface of the filling layer 61, the second mask layer 50 being located above each stack, and the projection of the second mask layer 50 on the silicon substrate 110 is illustratively in the form of an array-distributed grid.

As shown in fig. 18 and 20, the patterned second mask layer 50 has first grooves 510 and second grooves 520 in a row direction X and a column direction Y, respectively, in a plane parallel to the silicon substrate, and the second mask layer 50 defines a plurality of first grooves 510 and a plurality of second grooves 520 as shown in conjunction with fig. 18 to 21. Wherein the plurality of first grooves 510 are arranged at intervals in a row direction X in a plane parallel to the silicon substrate and extend in a column direction (direction perpendicular to the paper surface) in the plane parallel to the silicon substrate, and the extending direction of the first grooves 510 is the same as the extending direction of the first grooves 130.

As shown in fig. 20, the first grooves 510 are located right above the second dielectric layer 320, and the opening cross-sectional dimensions of the first grooves 510 are identical to those of the first trenches 130, so that a plurality of sidewall trenches exposing the channel layer 600 are formed in the row direction X in a plane parallel to the silicon substrate based on the plurality of first grooves 510.

As shown in fig. 18, a plurality of second grooves 520 are arranged at intervals in a column direction Y in a plane parallel to the silicon substrate and extend in a row direction (direction perpendicular to the paper surface) in the plane parallel to the silicon substrate, and the extending direction of the second grooves 520 perpendicularly intersects with the first groove direction. To form a plurality of trenches exposing sidewalls of the channel layer 600 in a column direction Y in a plane parallel to the silicon substrate based on the plurality of second grooves 520.

As shown in fig. 18 and 19, the filling layer 61, the second conductive layer 123, the channel layer 600, and the first conductive layer 121 are sequentially etched along the second groove 520, exposing a portion of the surface of the source line 400, forming a plurality of second trenches 140. As shown in fig. 20 and 21, during etching along the second groove 520, the filling layer 61 located above the surface of the second dielectric layer 320 may also be removed along the first groove 510 at the same time, so that the stack 120 is divided into stacks distributed in an array by the first trench 130 and the second trench 140.

In this embodiment, the second mask layer is used as a hard mask layer, and the first grooves and the second grooves are etched, and meanwhile, the original first grooves are utilized to divide the laminated layer in the direction parallel to the row direction and the column direction of the silicon substrate, so that the process steps are saved.

As shown in fig. 21 and 22, the sacrificial semiconductor layer 124 in the stack is removed by a selective etching process, and the remaining second conductive layer 123, channel layer 600 and first conductive layer 121 form a columnar semiconductor layer 900, and the columnar semiconductor layer 900 is arranged in an array on the silicon substrate 1110.

Step S180: and forming a grid electrode which surrounds and covers the side face of the columnar semiconductor layer.

Before forming the gate electrode, as shown in fig. 19 and 25, in order to isolate the source line 400 from the second metal material 810 formed in the subsequent process, a dielectric layer 90 is formed on the exposed surface of the source line 400 before removing the sacrificial semiconductor layer 124, the dielectric layer 90 covers the exposed surface of the source line 400, and then the dielectric layer 90 is planarized, the dielectric layer 90 functioning as an insulating isolation between the adjacent first conductive layers 121.

As shown in fig. 26 and 27, after the pillar-shaped semiconductor layers 900 are formed, the gate electrode 800 is formed around the channel layer 600 of each pillar-shaped semiconductor layer 900, the gate electrode 800 surrounds the surfaces of the first channel layer 610 and the second channel layer 620 that cover each pillar-shaped semiconductor layer 900, and fills up the region enclosed between the first channel layer 610, the first conductive layer 121, the second channel layer 620, and the second conductive layer 123 within the pillar-shaped semiconductor layer 900.

The process of forming the gate electrode will be described in detail with reference to fig. 23 and 24. First, a deposition process may be used to cover the gate insulating layer 820 on the surface of the channel layer 600, where the gate insulating layer 820 also covers the area enclosed by the first conductive layer 121, the second conductive layer 123, and the channel layer 600. An unpatterned second metal material 810 is formed on the surface of the gate insulating layer 820, and the second metal material 810 serves as a material layer of a gate electrode formed later.

As shown in fig. 25 and 26, the second metal material 810 is patterned to form an independent gate around the pillar-shaped semiconductor layer 900, and the step of forming the independent gate 800 includes: as shown in fig. 25, a patterned third mask layer 20 is formed over the pillar-shaped semiconductor layer 900 and over the second metal material 810, and the third mask layer 20 covers the surface of the filling layer 61, the sidewalls of the pillar-shaped semiconductor layer 900, and the top surface of the second metal material 810.

Referring to fig. 25, wherein the third mask layer 20 includes a spin-on hard mask layer 21, a photoresist layer 22, and a plurality of third grooves 210 spaced apart in the Y direction, each third groove 210 extending in a row direction in a plane parallel to the silicon substrate 110. As shown in fig. 25 and 26, the second metal material 810 and the dielectric layer 90 are etched along the plurality of third grooves 210, so that the second metal material 810 is divided into a plurality of gates 800 in a column direction Y in a plane parallel to the silicon substrate, and the columnar semiconductor layer 900 and the gates 800 together form a vertical gate-all-around transistor in the same direction perpendicular to the silicon substrate 110. As shown in fig. 26, the second conductive layer 123 in the columnar semiconductor layer 900 is the drain of the vertical gate-all-around transistor, the first conductive layer 121 is the source of the vertical gate-all-around transistor, and the gate electrode 800 is insulated from the source and the drain by the gate insulating layer, respectively.

In this embodiment, the gate 800 surrounds the region where the channel of the vertical gate-all-around transistor is located, and has a higher channel control capability, so that the short channel effect can be better suppressed.

As shown in fig. 29, the gate structure 800 may be a gate-all-around structure, and the projected area of the gate structure 800 on the substrate 110 is larger than the projected area of the channel layer 600 on the substrate 110.

In the method for forming the memory, the deeper first groove is formed in the substrate in the process of forming the VGAA transistor structure so as to form the first dielectric layer in the substrate preferentially, so that the process flow is optimized, and the substrate is only etched in the process of etching the first groove, so that the metal impurity etching environment is single and not complex, the process difficulty and the manufacturing cost of forming the isolation layer between the transistors are reduced, and the isolation effect is improved.

In some example embodiments, as shown in fig. 27, the second metal material may simultaneously serve as a word line material layer in forming the gate electrode. The wordline material layer is patterned using conventional spin-on, photolithographic processes to form the wordline 500, the wordline 500 forming an electrical connection with the gate 800.

The exemplary embodiment of the present disclosure illustrates a method for forming a memory, and the method provided in the present embodiment adds a method for forming a bit line on the basis of the method illustrated in fig. 1, and the method of the present embodiment may include:

step S210: a second filling layer 62 is formed on the surfaces of the filling layer, the columnar semiconductor layer, and the gate electrode.

As shown in fig. 27 and 28, a second filling layer 62 is formed over the columnar semiconductor layers 900 and on the surface of the gate electrode 800 to fill up the semiconductor structure for subsequent processing, the second filling layer 62 serving as an isolation and insulation between the columnar semiconductor layers 900.

Illustratively, after forming the gate, a filling layer on the top surface of the columnar semiconductor layer may be retained, so as to reduce the time of forming the dielectric layer by the subsequent process and reduce the time cost. Referring to fig. 28, the filler layer 61 and the second filler layer 62, which are not removed, together form a dielectric layer 60.

Step S220: and removing part of the second filling layer and the filling layer in sequence, exposing the surface of the second conductive layer, and forming a contact hole.

As shown in fig. 29, an opening pattern may be formed on the surface of the dielectric layer 60 by conventional development, exposure, or the like, and a portion of the second filling layer 62 and a portion of the filling layer 61 may be sequentially removed based on the opening pattern to form a contact hole 200, where the contact hole 200 exposes the top surface of the second conductive layer 123 of the columnar semiconductor layer 900, and the contact hole 200 is a bit line contact hole as shown in fig. 29.

Step S230: a bit line is formed in the contact hole, and the bit line is in contact connection with the second conductive layer.

As shown in fig. 30, a third metal material is continuously deposited in the contact hole 200, the third metal material covers the exposed surface of the second conductive layer 123 and fills the contact hole 200, and the deposited third metal material is annealed at a high temperature to form the bit line 30, so as to reduce the interface resistance between the bit line 30 and the second conductive layer 123 serving as the drain electrode, and improve the conductivity between the bit line 30 and the vertical gate-all-around transistor.

In an exemplary embodiment of the present disclosure, a memory is provided, as shown in fig. 30, which shows a schematic diagram of the memory provided according to an exemplary embodiment of the present disclosure, the memory includes:

a plurality of memory cells 80, the plurality of memory cells 80 being arranged in an array on the silicon substrate 110, each memory cell 80 comprising a vertical gate-all-around transistor, and a source line 400 connected to the source of the vertical gate-all-around transistor, a word line 500 connected to the gate 800, and a bit line 30 connected to the drain. As shown in fig. 30, the vertical gate-around transistor includes a columnar semiconductor layer 900 and a gate electrode 800, wherein the first conductive layer 121 is a source electrode and the second conductive layer 123 is a drain electrode.

A plurality of first trenches 130, each first trench 130 extending into the silicon substrate 110 through the thickness of the vertical transistor; the bottom wall of the first trench 130 is spaced from the top surface of the silicon substrate 110 by a distance greater than or equal to 2 times the thickness of the source line 400.

An isolation layer 300, the isolation layer 300 being located in the first trench, an upper surface of the isolation layer 300 being flush with an upper surface of the source of the vertical gate-all-around transistor to isolate the plurality of memory cells 80;

the source lines 400 are located in two oppositely disposed concave grooves 150 (refer to fig. 9) recessed in the side walls of the silicon substrate 110, and extend in a column direction in a plane parallel to the silicon substrate.

In some exemplary embodiments, as shown in connection with fig. 6 and 30, the isolation layer 300 includes a first dielectric layer 310 and a second dielectric layer 320, the first dielectric layer 310 and the second dielectric layer 320 being stacked in the first trench 130 from bottom to top;

wherein, the top surface of the first dielectric layer 310 is lower than the top surface of the silicon substrate 110 by a preset distance D1 (refer to fig. 6), and the preset distance D1 is smaller than the thickness H3 of the source line 400 (refer to fig. 11); the second dielectric layer 320 covers the surface of the source line 400 exposed by the first trench 130 and the top surface of the first dielectric layer 310, and the upper surface of the second dielectric layer 320 is flush with the upper surface of the source electrode.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for forming a memory, wherein the memory comprises a plurality of memory cells distributed in an array, each memory cell comprising a vertical gate-all-around transistor, a source line connected to a source of the vertical gate-all-around transistor, a word line connected to a gate, and a bit line connected to a drain; the method comprises the following steps:

patterning the laminated layer to form a plurality of first grooves, wherein the first grooves penetrate through the laminated layer and extend into the silicon substrate along the direction vertical to the silicon substrate, and the first grooves extend along the column direction in a plane parallel to the silicon substrate so as to isolate a plurality of storage units;

2. The method of forming a memory according to claim 1, wherein the method of forming an unpatterned stack provided on the silicon substrate comprises:

3. The method of claim 1, wherein patterning the stack to form a plurality of first trenches comprises:

4. A method of forming a memory according to any one of claims 1 to 3, wherein forming a first dielectric layer comprises:

5. The method of claim 4, wherein patterning the exposed sidewall of the silicon substrate to form two oppositely disposed recessed trenches recessed in the sidewall of the silicon substrate comprises:

6. The method of forming a memory of claim 5, wherein forming a second dielectric layer comprises:

7. The method of forming a memory according to claim 1, wherein the method of forming a plurality of columnar semiconductor layers comprises:

etching the second mask layer with the first grooves and the second grooves as masks until the top surfaces of the second dielectric layers are exposed based on the first grooves; etching the laminated layer and the channel layer to the top surface of the silicon substrate based on the second grooves to form a plurality of second grooves, wherein the reserved second conductive layers, the reserved channel layer and the reserved first conductive layers form columnar semiconductor layers, and the columnar semiconductor layers are distributed in an array; wherein a plurality of the first grooves extend in a direction parallel to the first grooves, and a plurality of the second grooves extend in a direction perpendicular to the first grooves.

8. The method of forming a memory of claim 7, wherein forming a gate comprises:

9. A memory, wherein the memory comprises

10. The memory of claim 9, wherein the isolation layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer being stacked in the first trench from bottom to top;

the top surface of the first dielectric layer is lower than the top surface of the silicon substrate by a preset distance, and the preset distance is smaller than the thickness of the source line; the second dielectric layer covers the surface of the source line exposed by the first groove and the top surface of the first dielectric layer, and the upper surface of the second dielectric layer is flush with the upper surface of the source electrode.