CN116205198A - Circuit schematic diagram module column ordering method, equipment and medium based on dynamic programming - Google Patents
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Abstract
The invention relates to the technical field of integrated circuits, in particular to a circuit schematic diagram module column ordering method, equipment and medium based on dynamic programming, wherein the method comprises the following steps: step S1, setting V 1,z =0, k=2; s2, acquiring the first k modules listed in the kth column module L based on a preset dynamic transfer equation k The (r) th arrangement D k,r Minimum value V of the number of crossing points of lower signal line k,r And V k,r Corresponding toA sequence of the ordering modes of the first k module columns; step S3, if k<K=k+1 is set, the process returns to step S2, and if k=k, V is acquired k,r And will V k,r The current ordering mode sequence of the first k module columns corresponding to the minimum value of the module columns is determined to be the ordering of the module columns of the target circuit schematic diagram. The invention reduces the number of signal line crossing points between the signal lines and improves the readability of the circuit schematic diagram.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, and a medium for ordering a circuit schematic module column based on dynamic programming.
Background
With the rapid development of very large scale integrated circuit technology, chip designs are becoming more and more complex. In the chip design process, debugging and verification are needed by means of a circuit diagram visualization tool so as to assist a user in discovering potential problems in the design and improve development efficiency. The circuit diagram is generated by determining the sequence of the module columns, and then, the route planning of the circuit diagram is carried out, wherein the route planning of the circuit diagram refers to the fact that the connection relation among the modules is represented by a plurality of horizontal or vertical signal lines through specific algorithms and constraints among given two or more circuit modules, so that a user can conveniently know the logic and hierarchical structure design among the modules. The circuit diagram in the debugging and verifying tool is different from the wiring layout diagram at the rear end, so that the minimum space is used for completing the route planning of all signal lines, the circuit diagram serves the design verification stage, the space is required, the connection relation between all modules in the chip design can be clearly and accurately described, and the hierarchical structure of the whole design is required to be clearly presented. The fewer signal line intersections between different signal lines of the circuit diagram are, the higher the readability of the circuit diagram is, the different module column sequences can correspond to the number of the signal line intersections between different signal lines, and the technical problem to be solved is to reduce the signal line intersections between the signal lines and improve the readability of the circuit diagram.
Disclosure of Invention
The invention aims to provide a circuit schematic diagram module column ordering method, equipment and medium based on dynamic programming, which reduce the number of signal line intersections between signal lines and improve the readability of a circuit schematic diagram.
According to a first aspect of the present invention, there is provided a method for ordering module columns of a circuit schematic diagram based on dynamic programming, the circuit schematic diagram including K module columns { L } 1 ,L 2 ,…,L k ,…,L K }, wherein L k For the kth module column, L k Comprises f (k) modules, and the kth module column comprises f (k) ≡! Seed arrangement { D } k,1 ,D k,2 ,…,D k,x ,…,D k,f(k)！ }，D k,x For the x-th arrangement of the kth module column, the value of x ranges from 1 to f (k) +.! F (k) ≡! Representing the factorial of f (k);
the method comprises the following steps:
step S1, setting V 1,z ＝0，k＝2；
S2, acquiring the first k modules listed in the kth column module L based on a preset dynamic transfer equation k The (r) th arrangement D k,r Minimum value V of the number of crossing points of lower signal line k,r And V k,r A corresponding ordering sequence of the first k module columns (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) The preset dynamic transfer equation is as follows:
V k,r ＝min{V k-1,z +X k-1,z,r |z＝1,2,…,f(k-1)！}
wherein V is k-1,z For the first k-1 module columns in the k-1 module column L k-1 In the z-th arrangement D k-1,z Minimum value of the lower signal line crossing point; x is X k-1,z,r For the k-1 th module column L k-1 In the z-th arrangement D k-1,z Next, the kth module column L k In the (r) th arrangement D k,r Next, the k-1 th module column L k-1 And the kth module column L k The number of signal line intersections therebetween; min { } represents the minimum value in brackets; r ranges from 1 to f (k) +.! The method comprises the steps of carrying out a first treatment on the surface of the D (D) v,xv Is V (V) k,r The corresponding ordering mode of the corresponding v-th module column, the value range of v is 1 to k, the value range of xv is 1 to f (v) +.! One of the values in (a);
step S3, if k<K=k+1 is set, the process returns to step S2, and if k=k, V is acquired k,r And will V k,r A sequence of the current top k module columns (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) And determining the sequence of the module columns of the target circuit schematic diagram.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the circuit schematic diagram module column ordering method, the device and the medium based on dynamic programming can achieve quite technical progress and practicality, and have wide industrial utilization value, and the method has at least the following beneficial effects:
the method optimizes the ordering method of the modules in the module column based on the dynamic programming mode, effectively reduces the number of the crossing points among different signal line connecting lines, improves the readability of a circuit schematic diagram, and further greatly improves the verification and debugging efficiency of a user on chip design.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for sequencing circuit schematic module columns based on dynamic programming according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit that is not optimized according to the present invention;
fig. 3 is a schematic circuit diagram of fig. 2 optimized according to the present invention according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a circuit diagram module column ordering method based on dynamic programming, wherein the circuit diagram comprises K module columns { L } 1 ,L 2 ,…,L k ,…,L K }, wherein L k For the kth module column, L k The number of modules f (k) is included, and it is understood that when f (k) is a variable value, that is, k takes different values, the values of f (k) may be different, that is, the number of modules in different module columns may be different or the same. The kth module column includes f (k) +.! Seed arrangement { D } k,1 ,D k,2 ,…,D k,x ,…,D k,f(k)！ }，D k,x For the x-th arrangement of the kth module column, the value of x ranges from 1 to f (k) +.! F (k) ≡! Represents the factorization of f (k), f (k) +! =f (k) ×f (k) -1]*[f(k)-2]* … x 2*1. It should be noted that the circuit schematic merely establishes a connection between modules between adjacent module columns, and does not establish a connection across module columns.
As shown in fig. 1, the method comprises the steps of:
step S1, setting V 1,z ＝0，k＝2。
Wherein V is 1,z For the first 1 column module at the 1 st column module L 1 In the z-th arrangement of the number of signal line intersections, it will be appreciated that there is only one column of modules, no intersection, and thus, V 1,z ＝0。
S2, acquiring the first k modules listed in the kth column module L based on a preset dynamic transfer equation k The (r) th arrangement D k,r Minimum value V of the number of crossing points of lower signal line k,r And V k,r A corresponding ordering sequence of the first k module columns (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) The preset dynamic transfer equation is as follows:
V k,r ＝min{V k-1,z +X k-1,z,r |z＝1,2,…,f(k-1)！}
wherein V is k-1,z For the first k-1 module columns in the k-1 module column L k-1 In the z-th arrangement D k-1,z Minimum value of the lower signal line crossing point; x is X k-1,z,r For the k-1 th module column L k-1 In the z-th arrangement D k-1,z Next, the kth module column L k In the (r) th arrangement D k,r Next, the k-1 th module column L k-1 And the kth module column L k The number of signal line intersections therebetween; min { } represents the minimum value in brackets; r ranges from 1 to f (k) +.! The method comprises the steps of carrying out a first treatment on the surface of the D (D) v,xv Is V (V) k,r The corresponding ordering mode of the corresponding v-th module column, the value range of v is 1 to k, the value range of xv is 1 to f (v) +.! Is a value of (a).
Step S3, if k<K=k+1 is set, the process returns to step S2, and if k=k, V is acquired k,r And will V k,r A sequence of the current top k module columns (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) And determining the sequence of the module columns of the target circuit schematic diagram.
It should be noted that, the unordered module columns may generate a large number of signal line intersections with adjacent module columns, and the invention simplifies the process of reducing the ordering of the signal line intersections into a multi-stage state optimization problem, and divides the multi-stage state optimization problem into a plurality of substructures by a dynamic programming mode to solve the problem. It will be appreciated that (V) can be determined by a predetermined dynamic transfer equation k-1,z +X k-1,z,r ) Is determined as V k,r Based on (V) k-1,z +X k-1,z,r ) Can determine the k column module L k The (r) th arrangement D k,r Minimum value V of the number of crossing points of lower signal line k,r When k=k, the K column module L can be calculated through the preset dynamic transfer equation K The minimum crossing point number of the first K module columns corresponding to each arrangement mode of the (B) module, and then the minimum crossing point number of the first K module columns corresponding to all arrangement modes of the K module columnsSelecting the sequence of the sorting modes of the first k module columns corresponding to the minimum number of the crossing points from the number of the points (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) And sequencing the module columns of the target circuit schematic diagram.
As an embodiment, the step S2 further includes:
step S21, obtaining the k-1 th module column L k-1 In the order of D k-1,z The kth module column L k In the order of D k，r At the time, the (k-1) th module column L k-1 The ith module and the kth module column L k Connection identifier C of the j-th module of (2) i,j And the k-1 th module column L k-1 The s-th module and the k-th module column L k Connection identifier C of the t-th module of (C) s,t Wherein s is>i,j>t, L k-1 If the two modules are connected, the corresponding connection identifier is 1, and if the two modules are not connected, the corresponding connection identifier is 0.
The (k-1) th module row L k-1 The ith module is always arranged before the ith module, and the kth module column L k Always arranged before the jth module, such that only in the kth-1 module column L k-1 The ith module and the kth module column L k Is connected to the j-th module of (1) and is arranged in the k-1-th module row L k-1 S modules and the kth module column L k When the t th module of (C) is connected i,j And C s,t The multiplication result of (1) is 1, and the corresponding module column L is in the (k-1) th module column k-1 And the kth module column L k A signal line crossing point is generated therebetween, otherwise C i,j And C s,t And the multiplication result of (2) is 0, all C can be traversed through the formula in the step S322 i,j And C s,t Determining when the k-1 th module column L k-1 In the order of D k-1,z The kth module column L k In the order of D k，r At the time, the (k-1) th module column L k-1 And the kth module column L k Total number of signal line intersections between.
Step S22, based on C i,j And C s,t Determination of X k-1,z,r ：
Wherein f (k-1) is the number of modules in the kth-1 module row, and f (k) is the number of modules in the kth module row.
It will be appreciated that the k-1 th module column L can be determined by step S322 k-1 And the total number of signal line crossing points corresponding to the kth module column under any permutation and combination.
All of the acquisitions C existing i,j And C s,t All falling within the scope of the present invention, in order to further enhance the acquisition of C i,j And C s,t As an embodiment, the step S21 includes:
step S211, obtaining the k-1 th module column L k-1 In the order of D k-1,z The kth module column L k In the order of D k，r At the time, the (k-1) th module column L k-1 And the kth module column L k Adjacent matrix C between k-1 ：
Wherein C in the adjacency matrix m,n For the k-1 th module column L k-1 M-th module and k-th module row L of (c) k If the connection identifier of the nth module is the (k-1) th module column L k-1 M-th module and k-th module row L of (c) k Is connected to the nth module of (C) m,n =1, if the k-1 th module column L k-1 M-th module and k-th module row L of (c) k Is not connected with the nth module of (C) m,n The value range of m is 1 to f (k-1), the value range of n is 1 to f (k), and the connection relationship between any two modules is a known parameter.
Step S212, based on the k-1 th module column L k-1 And the kth dieBlock column L k Adjacent matrix C between k-1 Obtaining C i,j And C s,t 。
C can be accurately and rapidly acquired through an adjacent matrix i,j And C s,t 。
As an example, the method further comprises:
s0, acquiring all circuit modules corresponding to the circuit schematic diagram, dividing the circuit modules into different layers, wherein modules with the same layers belong to the same module column, and generating K module columns { L } according to the arrangement sequence of the module columns 1 ,L 2 ,…,L k ,…,L K }。
It should be noted that, all the existing modes of reasonably dividing the circuit modules into layers according to the connection relationship between the circuit modules fall within the protection scope of the present invention, and will not be described here.
As an example, in the step S3, the current top k module columns are sequenced (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) Determining a rank order for a target circuit schematic module, comprising:
step S31, v takes on value from 1 until v=k, according to D v,xv And sequencing the modules of the v module column to generate the v module column.
And S32, carrying out left alignment adjustment on the modules in the K ordered module columns to generate K target module columns of the circuit schematic diagram.
The modules in the module columns of the circuit schematic diagram can be ordered more orderly in real time by adjusting left alignment of the modules in the K ordered module columns, so that the readability of the finally generated circuit schematic diagram is improved.
As an example, the step S3 further includes:
and step S33, establishing signal line connection between the modules of the adjacent target module columns based on the signal line connection relation between the modules of the adjacent target module columns, and generating a target circuit schematic diagram.
All the existing signal line connection relations between modules based on adjacent target module columns are established, and the mode of establishing signal line connection between modules of the adjacent target module columns falls into the protection scope of the invention, and the invention is not repeated one by one. It will be appreciated that the process of establishing signal line connections between modules based on adjacent target module columns should follow constraints such as minimum number of interconnections between different signal line connection lines, minimum number of signal line connection line bends, minimum number of signal line connection line branches, etc. It can be appreciated that the number of signal line intersections that may be generated in the module column sorting stage is reduced as much as possible in the embodiment of the present invention, and the number of signal line intersections may be further reduced in the signal line routing stage based on the signal line routing manner, which is not further limited in the present invention.
The present invention will be further described with reference to a specific embodiment, and the circuit schematic includes 4 module columns, each including 3 modules, as shown in fig. 2, where the number of modules in each module column is equal in the example shown in fig. 2, but the number of modules may be set to be unequal in practical application. In the example shown in fig. 2, the first module column (module column 1 in fig. 2) comprises modules 1.1, 1.2 and 1.3. The second module column (module column 2 in fig. 2) comprises modules 2.1, 2.2 and 2.3. The third module column (module column 3 in fig. 2) comprises modules 3.1, 3.2 and 3.3. The fourth module column (module column 4 in fig. 2) comprises modules 4.1, 4.2 and 4.3. Fig. 2 is a connection relationship between modules without optimization of the present invention, coexisting at 11 signal line intersections.
In the case of the module arrangement shown in fig. 2, the corresponding adjacency matrix can be obtained through step S211:
the corresponding connection matrix in the case of other module arrangements can also be obtained in step S211, which is not listed.
Since there are 3 modules per module column, there are 3 ≡ for the kth module column! =6 arrangements:
D k,1 ＝m k1 m k2 m k3 D k,2 ＝m k1 m k3 m k2
D k,3 ＝m k2 m k1 m k3 D k,4 ＝m k2 m k3 m k1
D k,5 ＝m k3 m k1 m k2 D k,6 ＝m k3 m k2 m k1
wherein D is k,x The x-th arrangement mode of the k-th module column, m ki An ith module of the kth module column. It should be noted that, no matter how the module order of the module columns is adjusted, the connection relationship between the modules is always unchanged. The arrangement shown in FIG. 2 is (D 1,1 ，D 2,1 ，D 3,1 ，D 4,1 ) The results of the ordering under the combination.
The step S2 can be calculated by the invention:
V 1,1 ＝0,V 1,2 ＝0,V 1,3 ＝0,V 1,4 ＝0,V 1,5 ＝0,V 1,6 ＝0
V 2,1 ＝0,V 2,2 ＝0,V 2,3 ＝1,V 2,4 ＝0,V 2,5 ＝1,V 2,6 ＝0
V 3,1 ＝0,V 3,2 ＝1,V 3,3 ＝1,V 3,4 ＝1,V 3,5 ＝1,V 3,6 ＝0
V 4,1 ＝2,V 4,2 ＝4,V 4,3 ＝2,V 4,4 ＝4,V 4,5 ＝2,V 4,6 ＝2
from this, it can be seen that V 4,r When there are a plurality of minima, the minimum value of (2) is selected from the arrangement order corresponding to one minimum value, in this example, V is selected 4,1 The corresponding current rank order sequence of the first k module columns (D 1,2 ，D 2,5 ，D 3,4 ，D 4,1 ) Based on (D) 1,2 ，D 2,5 ，D 3,4 ，D 4,1 ) A corresponding circuit schematic is generated as shown in fig. 3. As can be seen from comparing fig. 2 and fig. 3, the sorting mode of the module columns optimized by the invention reduces the number of signal line intersections from 11 to 2, thereby effectively improving the readability of the circuit schematic diagram.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The method optimizes the ordering method of the modules in the module column based on the dynamic programming mode, effectively reduces the number of the crossing points among different signal line connecting lines, improves the readability of a circuit schematic diagram, and further greatly improves the verification and debugging efficiency of a user on chip design.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. A circuit schematic diagram module column ordering method based on dynamic programming is characterized in that,
the circuit schematic comprises K module columns { L } 1 ,L 2 ,…,L k ,…,L K }, wherein L k For the kth module column, K has a value ranging from 1 to K, L k Comprises f (k) modules, and the kth module column comprises f (k) ≡! Seed arrangement { D } k,1 ,D k,2 ,…,D k,x ,…,D k,f(k)！ }，D k,x For the x-th arrangement of the kth module column, the value of x ranges from 1 to f (k) +.! F (k) ≡! Representing the factorial of f (k);
the method comprises the following steps:
step S1, setting V 1,z ＝0，k＝2；
S2, acquiring the first k modules listed in the kth column module L based on a preset dynamic transfer equation k The (r) th arrangement D k,r Minimum value V of the number of crossing points of lower signal line k,r And V k,r A corresponding ordering sequence of the first k module columns (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) The preset dynamic transfer equation is as follows:
V k,r ＝min{V k-1,z +X k-1,z,r |z＝1,2,…,f(k-1)！}
wherein V is k-1,z For the first k-1 module columns in the k-1 module column L k-1 In the z-th arrangement D k-1,z Minimum value of the lower signal line crossing point; x is X k-1,z,r For the k-1 th module column L k-1 In the z-th arrangement D k-1,z Next, the kth module column L k In the (r) th arrangement D k,r Next, the k-1 th module column L k-1 And the kth module column L k The number of signal line intersections therebetween; min { } represents the minimum value in brackets; r ranges from 1 to f (k) +.! The method comprises the steps of carrying out a first treatment on the surface of the D (D) v,xv Is V (V) k,r The corresponding ordering mode of the corresponding v-th module column, the value range of v is 1 to k, the value range of xv is 1 to f (v) +.! One of the values in (a);
step S3, if k<K=k+1 is set, the process returns to step S2, and if k=k, V is acquired k,r And will V k,r A sequence of the current top k module columns (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) And determining the sequence of the module columns of the target circuit schematic diagram.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S2 further includes:
step S21, obtaining the k-1 th module column L k-1 In the order of D k-1,z The kth module column L k In the order of D k，r At the time, the (k-1) th module column L k-1 The ith module and the kth module column L k Connection identifier C of the j-th module of (2) i,j And the k-1 th module column L k-1 The s-th module and the k-th module column L k Connection identifier C of the t-th module of (C) s,t Wherein s is>i,j>t, if the two modules are connected, the corresponding connection identifier is 1, and if the two modules are not connected, the corresponding connection identifier is 0;
step S22, based on C i,j And C s,t Determination of X k-1,z,r ：
Wherein f (k-1) is the number of modules in the kth-1 module row, and f (k) is the number of modules in the kth module row.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the step S21 includes:
step S211, obtaining the k-1 th module column L k-1 In the order of D k-1,z First, thek module columns L k In the order of D k，r At the time, the (k-1) th module column L k-1 And the kth module column L k Adjacent matrix C between k-1 ：
Wherein C in the adjacency matrix m,n For the k-1 th module column L k-1 M-th module and k-th module row L of (c) k If the connection identifier of the nth module is the (k-1) th module column L k-1 M-th module and k-th module row L of (c) k Is connected to the nth module of (C) m,n =1, if the k-1 th module column L k-1 M-th module and k-th module row L of (c) k Is not connected with the nth module of (C) m,n =0, m is in the range of 1 to f (k-1), n is in the range of 1 to f (k), and the connection relationship between any two modules is a known parameter;
step S212, based on the k-1 th module column L k-1 And the kth module column L k Adjacent matrix C between k-1 Obtaining C i,j And C s,t 。
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the method further comprises the steps of:
s0, acquiring all circuit modules corresponding to the circuit schematic diagram, dividing the circuit modules into different layers, wherein modules with the same layers belong to the same module column, and generating K module columns { L } according to the arrangement sequence of the module columns 1 ,L 2 ,…,L k ,…,L K }。
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the step S3, the current order of the top k module columns is set to (D 1,x1 ,D 2,x2 ,…,D v,xv ,…,D k,r ) The sequence of the module columns is determined as the target circuit schematic,comprising the following steps:
step S31, v takes on value from 1 until v=k, according to D v,xv The modules of the v-th module column are ordered to generate the v-th module column;
and S32, carrying out left alignment adjustment on the modules in the K ordered module columns to generate K target module columns of the circuit schematic diagram.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S3 further includes:
and step S33, establishing signal line connection between the modules of the adjacent target module columns based on the signal line connection relation between the modules of the adjacent target module columns, and generating a target circuit schematic diagram.
7. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.
8. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-6.
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