CN116205175A - Integrated circuit optimization system and method based on multiphase level sensitive latch - Google Patents
Integrated circuit optimization system and method based on multiphase level sensitive latch Download PDFInfo
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Abstract
Integrated circuit optimization systems and methods based on multiphase level sensitive latches. The present invention relates to an integrated circuit optimization system and method that includes converting edge-triggered sequential elements (e.g., flip-flops) into equivalent blocks containing multiphase level-sensitive latches, followed by optimization techniques based on the level-sensitive latches, such as level-sensitive latch retiming, and signal transmission through the level-sensitive latches based on prediction or detection, over worst-case designs. The invention also relates to an integrated circuit comprising: an edge triggered sequential element; multiphase level sensitive latches deployed on critical timing paths; and a logic net between the multiphase level sensitive latches, the input signals of the logic net coming from a first set of level sensitive latches with the same or similar phase, the output signals of the logic net being sent to a second set of level sensitive latches with the same or similar phase, the first set of level sensitive latches and the second set of level sensitive latches being different in phase.
Description
The present application is a divisional application of Chinese patent application with application date of 2019, 9, 26, 201910917462.2 and entitled "integrated circuit optimization System and method based on multiphase level sensitive latch".
RELATED APPLICATIONS
The present application is based on U.S. provisional patent application US62/743,248 entitled "Integrated Circuit Optimization System and Method Based on Transformation from Edge-Triggered Sequential Elements to Level-Sensitive Latches" filed on 10/9 of 2018, and U.S. provisional patent application US 62/833,127 entitled "Integrated Circuit Optimization System and Method Based on Transformation from Edge-Triggered Sequential Elements to Level-Sensitive Latches" filed on 12 of 4/2019. The entire contents of these applications are hereby incorporated by reference as if set forth herein in their entirety.
Technical Field
The invention relates to an integrated circuit design optimization technology.
Background
The synchronous sequential circuit includes sequential elements and a combinational logic network. Combinational logic constitutes a logic stage between sequential elements. The sequential elements are typically clock edge-triggered flip-flops. The logic expression is first generated by logic synthesis into a network of logic gates in the cell library, after which optimization techniques such as logic optimization or register retiming can be employed. Logic optimization finds equivalent implementations of the same logic through logic conversion while achieving specific design metrics such as timing performance. The register or latch retiming better balances the critical signal propagation paths in two adjacent logic stages by shifting one clock edge triggered flip-flop or level sensitive latch in the circuit structure.
Conventional integrated circuits based on flip-flops require that the data signal arrive at the flip-flop earlier than the clock signal. Conventional static timing analysis verifies this by checking whether the worst-case signal propagation delay in the combinational logic network is less than the clock period (details include signal setup time, hold time, clock drift, uncertainty, etc.). The timing requirements of the level sensitive latch are different from the flip-flop, e.g., the level sensitive latch allows the data signal to arrive later than the latch enable signal.
In static timing analysis, time borrowing occurs when the data signal arrives at the level sensitive latch later than the latch enable signal. This is not a timing error because the latch is transparent allowing the signal to pass through. The borrowed time or the part of the data signal that arrives later than the latch enable signal needs to be reimbursed in the subsequent signal transmission, which signal needs to be completed in the subsequent logic stage in the subsequent clock cycle. In particular, static timing analysis verifies that the same timing requirements as for flip-flops are applied to level sensitive latches, i.e., the signal transmission path delay must be less than a clock period, but the time that a level sensitive latch borrows needs to be included in the delay of the signal transmission path from the latch. The related art can be found in U.S. patent No. 2009/0055786 A1 entitled "Method for Verifying Timing of a Circuit" filed on 8/5 of 2008 by Mau-Chung Chang.
Integrated circuit process advances have resulted in significant increases in manufacturing process, supply voltage, on-chip temperature, and other parameter perturbations. Thus, even if the normal value of a parameter decreases as the process progresses, the optimum and worst values of the parameter do not decrease proportionally. This has impacted integrated circuit performance advances because conventional synchronous sequential circuit design approaches require that logic operations in one logic stage must complete within one clock cycle, including the worst case. This requirement applies equally to level sensitive latches, taking into account borrowing time and compensating time.
Another approach to integrated circuit design is to go beyond worst case designs to achieve performance improvements, power consumption reduction, and/or area reduction. For example, it is not required that the logic operation must complete within one clock cycle. In some applications, such as image and speech processing, a certain error rate is acceptable, so that approximate calculations can be used to achieve power consumption, performance, and area improvement. One simple approximate calculation technique is over-clocking, which allows some critical signal transmission paths to be delayed beyond the clock period. If the error rate so brought is acceptable, an over-clocking technique can be employed. In other applications, the system guarantees zero error rate by detecting and correcting errors or predicting and preventing errors. Specific techniques include the use of error detection codes or error correction codes in integrated circuits, or error detection timing designs such as the Razor design, see U.S. patent No. 10/392,382 entitled "Error Detection and Recovery Within Processing Stages of an Integrated Circuit" filed 3/20/2003, peter a. Beerel, melvin Breuer, benmao Cheng, and the Dylan Hand, U.S. patent No. 14/702,426 entitled "Timing Violation Resilient Asynchronous Template" filed 5/2015/1.
A practical timing error prediction scheme is described in U.S. De, A.B. Kahng, T.Karnik, B.Liu, M.Maleki and L.Wang, published in ACM Journal on Emerging Technologies in Computing Systems (JETC) -Special Issue on Cross-Layer System Design and Regular Papers,12 (3), 9, 2015, pages 21:1-21:19, entitled "Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design".
Disclosure of Invention
The present invention relates to an integrated circuit optimization system and method that includes converting edge-triggered sequential elements (e.g., flip-flops) into equivalent blocks containing multi-phase level-sensitive latches, followed by optimization techniques based on the level-sensitive latches, such as level-sensitive latch retiming, and predicting or detecting signal transmission through the level-sensitive latches over worst-case designs, the optimized integrated circuit including the multi-phase level-sensitive latches, the edge-triggered sequential elements, and a combinational logic network that are separated from one another.
In one embodiment of the invention, the integrated circuit timing performance improvement results from level sensitive latch retiming, or shifting the level sensitive latch at the beginning or end of the timing critical signal transmission path in the circuit structure can reduce signal transmission path delay. In contrast, existing register retiming techniques, or techniques that shift clock edge triggered flip-flops in a circuit configuration, can balance signal transmission path delays at the input and output of the flip-flop, but can achieve limited timing performance improvements. Converting the flip-flop to an equivalent module comprising master and slave latches provides additional degrees of freedom for circuit optimization, and moving one of the level sensitive latches in the circuit structure reduces the delay of the signal transmission path connected thereto without affecting the signal transmission path connected to the other level sensitive latch.
In one embodiment of the invention, the time at which the data signal arrives at a level sensitive latch is compared to the time at which the latch close signal arrives, which is determined by the signal transmission path. This timing requirement, unlike conventional time borrowing based timing requirements, can provide additional space for integrated circuit performance optimization.
The retiming of the level sensitive latch results in many signal transmission paths through the level sensitive latch through which signals are transmitted as a small probability event. Disregarding these small probability events in integrated circuit optimization may improve power consumption, performance, and area; predicting or detecting and processing such small probability events can ensure that the system functions properly. In one embodiment of the invention, the transmission of the predicted signal through the critical path is based on observing certain edge inputs of the path. In another embodiment of the invention, detecting a timing error is accomplished by comparing the input output of a level sensitive latch with the input output of the level sensitive latch when the latch preceding it is closed.
According to a first aspect of the present invention there is provided an optimisation method for an integrated circuit comprising edge triggered sequential elements, the optimisation method comprising the steps of: a. converting the edge triggered sequential elements into an equivalent module comprising multiphase level sensitive latches; b. one of the level sensitive latches is shifted in a circuit configuration of the integrated circuit.
According to a second aspect of the present invention there is provided an apparatus comprising a finite state machine inputting signals from a plurality of combinational logic stages and outputting signals to display signal transmission through a timing critical path through a level sensitive latch.
According to a third aspect of the present invention there is provided an apparatus comprising a comparator that compares input and output signals of level sensitive latches when both the level sensitive latches and all previous level sensitive latches are opaque in an integrated circuit comprising multiphase level sensitive latches.
According to a fourth aspect of the present invention there is provided a computer readable medium for storing computer instructions which, when executed by a computer, carry out a method according to the first aspect of the present invention.
Drawings
The advantages of the invention are presented in the following description of the invention and the accompanying drawings.
Fig. 1 shows a schematic diagram of a conventional trigger retiming technique.
Fig. 2 shows a schematic diagram of a conventional level sensitive latch retiming technique.
Fig. 3 shows a schematic diagram of converting an edge trigger to an equivalent module comprising two level sensitive latches that are transparent at two opposite clock phases, respectively, according to an embodiment of the invention.
Fig. 4 shows a schematic diagram of one example of an example integrated circuit optimization method, according to an embodiment of the invention.
Fig. 5 shows a schematic diagram of another example of an integrated circuit optimization method according to an embodiment of the invention.
Fig. 6 shows a schematic diagram of yet another example of an integrated circuit optimization method according to an embodiment of the invention.
Fig. 7 shows a schematic diagram of yet another example of an integrated circuit optimization method according to an embodiment of the invention.
Fig. 8 is a schematic diagram showing a conventional static timing analysis method for a synchronous digital system.
Fig. 9 is a schematic diagram showing a time borrowing method in the existing static timing analysis.
FIG. 10 illustrates a set of timing constraints for an integrated circuit containing a dual phase level sensitive latch according to an embodiment of the present invention.
FIG. 11 illustrates a set of timing constraints for an integrated circuit containing four-phase level-sensitive latches, according to an embodiment of the invention.
FIG. 12 shows a block diagram of a timing error prediction apparatus in the form of a finite state machine, according to an embodiment of the invention.
Fig. 13 shows a block diagram of a timing error detection apparatus according to an embodiment of the present invention.
Fig. 14 shows a flow chart of an integrated circuit optimization method according to an embodiment of the invention.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown in the drawings and will be described in detail. The drawings may not be to scale. It should be understood that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Detailed Description
It is to be understood that the present invention is not limited to particular devices or systems, which, of course, vary from one another. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
Fig. 1 shows a schematic diagram of a conventional trigger retiming technique. The timing performance improvement results from a better balancing of delays in signal transmission paths ending and starting at a certain flip-flop. Similarly, FIG. 2 shows a schematic diagram of a conventional level sensitive latch retiming technique. The timing performance improvement results from a better balancing of delays in signal transmission paths ending and starting at a level sensitive latch.
Fig. 3 shows a schematic diagram of an equivalent module for converting an edge-triggered sequential element to contain a multi-phase level-sensitive latch according to an embodiment of the present invention. Specifically, the D flip-flop is converted into a pair of master-slave latches that are transparent in two opposite clock phases, respectively. More complex edge-triggered sequential elements can be similarly converted to equivalent modules that include multi-phase level-sensitive latches.
Fig. 4 shows a schematic diagram of one example of an integrated circuit optimization method that includes performing sequential element transitions and moving a latch from an input of a nand logic gate to an output of the logic gate, in accordance with an embodiment of the invention. Specifically, in the method shown in fig. 4, two edge-triggered flip-flops are converted to level-sensitive latches, then the two level-sensitive latches are removed from the input of the nand gate, a new level-sensitive latch is inserted at the output of the nand gate, and at the same time another level-sensitive latch is inserted at the fan-out node of the fan-in cone of the nand gate, i.e., the input of the not gate.
Fig. 5 shows a schematic diagram of another example of an integrated circuit optimization method according to an embodiment of the invention, which may include the steps of inserting level sensitive latches in a timing critical path, performing timing element transitions and level sensitive latch removals at the fan-in-cone input of the inserted latches a, and inserting latches at the fan-in-cone output, which may be used after converting edge triggered timing elements into level sensitive latches. Specifically, in the method shown in fig. 5, first, timing critical paths that need to be shortened are identified, for example, for establishing time constraints. Second, the flip-flop at the beginning of the path is converted to an equivalent module containing level sensitive latches. Still second, the level sensitive latch is moved from the beginning of the critical path to a new location. The new location (1) meets timing constraints and (2) costs such as chip area and/or power consumption are minimized. Next, the gate level network is traversed from the newly inserted latch (a) to the initial input to obtain the fan-in cone of latches. The input to the fan-in cone is a set of sequential elements, each of which edge-triggered sequential elements needs to be converted to an equivalent module containing level sensitive latches (including level sensitive latches b and c). Each level-sensitive latch at the input of the fan-in cone is then removed while a level-sensitive latch (including d, e, and f) is inserted at each fan-out node of the fan-in cone, so that no signal transmission path continues through the two simultaneously transparent level-sensitive latches, even after converting the edge-triggered sequential elements into equivalent modules containing the level-sensitive latches.
Fig. 6 illustrates a schematic diagram of yet another example of an integrated circuit optimization method that may include performing sequential element transitions and moving latches from the output of one nand logic gate to the input of the logic gate, in accordance with an embodiment of the invention. Specifically, in the method shown in fig. 6, two flip-flops are converted to level sensitive latches, then the two level sensitive latches are removed from the output of the nand gate's fan-out cone, two new level sensitive latches are inserted at the input of the nand gate, while the other level sensitive latch is inserted at a fan-in node of the nand gate's fan-out cone, which is also an input of the and gate.
Fig. 7 illustrates a schematic diagram of yet another example of an integrated circuit optimization method according to an embodiment of the invention, which may include the steps of inserting level sensitive latches in a timing critical path, performing timing element transitions and level sensitive latch removals at the output of the fan-out cone of inserted latches a, and inserting latches at the input of the fan-out cone, which may be used after converting an edge-triggered timing element into a level sensitive latch. Specifically, in the method shown in fig. 7, first, timing critical paths that need to be shortened are identified, for example, for establishing time constraints. Second, the flip-flop at the termination end of the path is converted to an equivalent module containing level sensitive latches. Still second, the level sensitive latch is moved from the termination end of the critical path to a new location. The new location (1) meets timing constraints and (2) costs such as chip area and/or power consumption are minimized. Next, the gate level network is traversed from the newly inserted latch (a) to the initial output to obtain the fan-out cone of latches. The output of the fan-out cone is a set of sequential elements, each of which edge-triggered sequential elements needs to be converted into an equivalent module (including level sensitive latches b and c) containing level sensitive latches. Next, each level-sensitive latch at the output of the fan-out cone is removed while one level-sensitive latch (including d) is inserted at each fan-in node of the fan-out cone, so that no signal transmission path continues through two simultaneously transparent level-sensitive latches, even after converting an edge-triggered sequential element into an equivalent module containing level-sensitive latches.
Integrated circuits are limited by timing constraints. Fig. 8 is a schematic diagram showing a conventional static timing analysis method for a synchronous digital system. In the method of fig. 8, the signal arrival time is constrained by the signal setup time and the signal hold time. In addition, in the example of fig. 8, the flip-flop is rising clock edge triggered. Specifically, FIG. 8 shows the signal setup time and hold time constraints in a conventional flip-flop based synchronous sequential circuit, where d is the signal propagation delay in a logic stage, T c Is clock period, T hold Is a signal hold time constraint, T setup Is the signal setup time constraint. In the conventional static timing analysis method, logic gates and interconnect delays are accumulated in each logic stage, and the resulting signal transmission path delays are compared with signal setup and hold time constraints of the flip-flops that accept the signals.
Fig. 9 is a schematic diagram showing a time borrowing method in the existing static timing analysis. In the method of FIG. 9, the time at which the signal arrives at the level sensitive latch is adjusted by borrowing time, which is the time at which the signal arrives beyond the arrival time of the latch-on clock edgeIn part, while the signal setup time and hold time of the latch are relative to the latch closing clock edge, the maximum borrowing time comes from the setup time constraint, any borrowing time needs to be compensated at the next logic level. The level sensitive latch is transparent when the clock signal is high, and the clock signal is high for half a clock cycle. In particular, fig. 9 shows the setup and hold times of an integrated circuit based on a single phase level sensitive latch, wherein the signal is transmitted through a series of level sensitive latches controlled by a single phase clock signal. d is the signal transmission delay in the logic stage, T c Is clock period, T hold Is a signal hold time constraint, T setup Is the signal setup time constraint. The level sensitive latch is shown transparent when the clock signal phi is high, which is high for half a clock cycle. Each level sensitive latch has a setup time and a hold time with respect to the latch disable signal or the off clock edge, i.e., the minimum time that the data signal must remain stable before and after the latch disable signal or the off clock edge. Time borrowing occurs when a signal reaches the data end of a level sensitive latch after a latch enable signal or an open clock edge. Borrowing time T borrow Is the portion of the data signal arrival time that exceeds the latch enable signal or the on clock signal arrival time. The maximum borrow time is the time between the latch enable signal arrival time and the disable signal arrival time or the time between the on clock edge arrival time and the off clock edge arrival time after the setup time is removed. Compensation time T compensate Is the borrowing time of the signal at the latch input of the transmit signal or the output of the previous logic stage. In conventional static timing analysis, logic gates and interconnect delays in each logic stage accumulate. The latest signal arrival time from all possible paths to the receiving-side level-sensitive latch is used to calculate the borrowing time or the compensation time of the level-sensitive latch. For signal transmission paths starting at level sensitive latches and ending at edge-triggered flip-flops, path delay checking is based on the setup and hold times of the signal to the edge-triggered flip-flops, which are the same as those shown in FIG. 8Also, any compensation time of the start-end level sensitive latch needs to be taken into account in the signal transmission path delay.
In multi-phase latch based integrated circuits, signals are transferred through a series of level sensitive latches that are opened by a set of multi-phase clock signals. In a typical design, the clock signal causes the latch to become transparent, through which the data signal passes (typically through a combinational logic network) to the latch that is transparent at the next clock cycle. If the signal arrives before the accept latch is transparent, the signal waits for the next stage to transmit. If the signal arrives when the accept latch is transparent, time borrowing occurs and the signal continues to pass through the next logic stage. If the signal arrives after the receiving-side latch is transparent and then opaque, the signal cannot pass through the latch. The signal must wait one more clock cycle before it can pass through the latch, during which time the logic computation of the next clock cycle may destroy the signal and cause a logic error.
Thus, the signal needs to arrive before the receiver latch becomes opaque. The setup time describes the minimum allowed time between the time the signal arrives at the level sensitive latch and the arrival time of the clock edge that makes the level sensitive latch opaque. The data signal needs to remain stable after the clock edge makes the level sensitive latch opaque. The hold time describes the minimum time interval that the data signal needs to remain stable after the clock edge that makes the level sensitive latch opaque.
FIG. 10 illustrates a set of timing constraints for an integrated circuit containing a dual phase level sensitive latch according to an embodiment of the present invention. In this figure n is the number of logic stages through which the signal transmission path passes. In particular, fig. 10 shows signal setup and hold time constraints in a dual phase level sensitive latch based integrated circuit in which signals are transmitted through a sequence of level sensitive latches alternately controlled by two clock signals of opposite phase. Wherein d is i Is the signal transmission delay in the ith logic stage, T c Is clock period, T hold Is a signal hold time constraint, T setup Is the signal setup time constraint.
FIG. 11 illustrates a set of timing constraints for an integrated circuit containing four-phase level-sensitive latches, according to an embodiment of the invention. In the figure, n is the number of logic stages through which the signal transmission path passes, k is the number of clock phases, and m is the number of phases of the high level of the clock signal. Specifically, FIG. 11 shows the setup and hold time constraints of a four-phase level-sensitive latch-based integrated circuit in which signals are transferred through a series of level-sensitive latches that are controlled by four different phase clock signals, respectively. Four different phase clock signals rise at 0, 25%,50%, and 75% of the clock cycle, and fall at 50%,75%,100%, and 25% of the clock cycle, respectively. d, d i Is the signal transmission delay in the ith logic stage, T c Is clock period, T hold Is a signal hold time constraint, T setup Is the signal setup time constraint. On any data signal transmission path, the level sensitive latches become transparent in sequence: after the level sensitive latch becomes transparent, the data signal is transmitted from it through the logic network, and the level sensitive latch receiving the signal at the output of the logic network becomes transparent at the next clock phase. Each level sensitive latch is transparent in two consecutive clock phases and opaque in two other consecutive clock phases. The delay in signal transmission through the first logic stage must be less than the setup time of the three clock phases to remove the receiver-side level-sensitive latch, so that the signal has time to setup before the receiver-side level-sensitive latch is opaque; it must also be removed by one clock cycle more than the hold time of the receiver-side level-sensitive latch so that the signal of the previous cycle is held after the receiver-side level-sensitive latch is opaque. This hold time constraint is often easily met because it requires that the signal propagation delay be greater than some negative value. Any clock drift and/or uncertainty needs to be accounted for.
FIG. 11 also presents a generalized form of setup and hold time constraint for integrated circuits based on multiphase level sensitive latches, where the signal is transmitted through a series of level sensitive latches controlled by clock signals of different phases, respectively. Let k be the number of clock phases, m be the number of clock phases in which the level sensitive latch is opaque, n be the number of logic stages through which the signal transmission path passes, and fig. 14 shows a generalized form of setup time and hold time in a multi-phase level sensitive latch based integrated circuit. Specifically, n is increased by one, and the allowable maximum and minimum data transmission path delays through n logic stages are each increased by the duration of one clock phase. This is for a multiphase level sensitive latch based circuit in which the signal is transmitted through a series of level sensitive latches controlled by a continuous phase clock signal. In some cases, some clock phases in a sequence of level sensitive latches on one signal transmission path may be missing. In a more general sense, the setup time constraint of a data signal arriving at one level sensitive latch depends on the next latch close signal, and the hold time constraint depends on the previous latch close signal. The same is true for flip-flops constructed from level sensitive latches.
The timing constraints in fig. 10 or 11 approach those in fig. 8 or 9 when the logical progression n through which the signal is transmitted approaches infinity. In practice, however, in most cases n is small, the timing constraints in fig. 10 or 11 are more relaxed than those in fig. 8 or 9, giving more room for integrated circuit performance optimization. This is because: (1) The signal transmission path passes through the level sensitive latch only when the data signal arrives at the latch later than the latch enable signal; the level sensitive latch output signal arrival time is otherwise dependent on the latch enable signal arrival time. (2) Considering parameter disturbance, when the parameter disturbance is not completely correlated, the longer the signal transmission path is, the larger the mutual cancellation effect of the parameter disturbance is, so that the worst negative time margin appears on the signal transmission path with limited length; the exception is that the signal is transmitted in a closed loop with a worst case negative time margin occurring on an infinite length signal transmission path. The above exceptions need to be considered in the timing analysis. The timing analysis does not require tracking the signal to pass through an infinite number of logic stages, since as the number of logic stages n through which the signal passes increases, each logic stage's contribution to any negative time margin decreases, so that sufficient accuracy can be obtained to finish calculating the signal arrival time at a certain point in time.
Compared to conventional static timing analysis methods employing time borrowing for level sensitive latches, the static timing analysis method based on the timing constraints of fig. 10 or 11 requires that a tracking signal be transmitted through the level sensitive latch in multiple clock phases or periods and comparing the time at which the data signal arrives at the level sensitive latch with the latch disable signal arrival time at which the latch was closed immediately after the data signal arrived in the original design. This method of timing analysis requires more computation, longer time, and more memory space to obtain signal arrival times in multiple clock cycles. However, this approach gives a complete signal transmission path across multiple logic stages, which facilitates implementation of the optimization method of the present invention, such as acknowledging the beginning and ending of the signal transmission path. Another advantage of this approach is that its timing constraints are more relaxed than conventional time-borrowed-based level sensitive latches, giving more room for performance optimization. Because in conventional time-based borrowing methods the signal transmission path does not pass through the level sensitive latch, the maximum signal arrival time at the level sensitive latch gives the borrowing time or the compensation time for all signal transmission paths starting from the level sensitive latch. This compensation time is too large for some paths.
The above timing constraints provide more room for integrated circuit performance improvement, and in addition, converting edge-triggered sequential elements to equivalent modules containing multi-phase level sensitive latches provides more degrees of freedom for optimizing integrated circuits. For example, if a timing critical path p 1 Terminating at the input of a flip-flop and another timing critical path p 2 Moving the flip-flop in the circuit configuration does not improve the performance of the circuit or shorten the clock period because the timing critical path p starting from the flip-flop is shortened 2 Inevitably causes a timing critical path p terminating in the flip-flop 1 And vice versa. After the trigger is converted into an equivalent module comprising a pair of master-slave level sensitive latches by the invention, for exampleIn other words, shifting the slave latch can reduce the timing critical path p starting from the output of the slave latch 2 Without affecting the timing critical path p terminating at the main latch input 1 The delay can be reduced in a next optimization step, e.g. moving on the timing critical path p 1 Is a starting point for the level sensitive latch of the start point.
Repeating this process may reduce the critical path-by-critical path latency. As the number of edge-triggered sequential elements that transition to equivalent blocks containing level-sensitive latches increases, so does the number of timing critical paths through the level-sensitive latches or across multiple logic stages. The probability of signal transmission through such long paths is low. Such circuits are therefore suitable for use with better than worst case integrated circuit design techniques. In one embodiment of the invention, the long signal transmission path may simply be set to a pseudo path, which may result in better power consumption, performance, and/or area in circuit optimization if the resulting error rate is acceptable. In another embodiment of the invention, to ensure zero error rate, the integrated circuit detects and then corrects or predicts and then prevents any possible timing errors.
FIG. 12 shows a block diagram of a timing error prediction apparatus in the form of a finite state machine that predicts timing errors by sampling signals in different logic stages in an integrated circuit containing multi-phase level sensitive latches, according to an embodiment of the present invention. In particular, FIG. 12 illustrates an embodiment in which the present invention is based on an advantage over worst case integrated circuit design techniques in that the signal transmission path is delayed by more than a clock cycle. To ensure zero error rate, the monitoring module generates a signal that activates a clocked logic gate at any time when the signal is transmitted in the path, giving an extra clock cycle so that too slow a logic operation is completed, and then resumes system operation.
Fig. 12 shows a monitoring module in the form of a finite state machine which extracts input signals from a combinational logic network in a plurality of clock phases. The finite state machine is constructed by first identifying a timing critical path across one or more logic stages in an integrated circuit comprising a multi-phase level sensitive latch, then selecting a portion of the edge inputs of the timing critical path, and then designing the finite state machine to output a logic 1 after a predetermined pattern of signals is received at the edge inputs at a plurality of clock phases. For a logic gate on one signal transmission path, the edge input is the logic gate input that is not on the path. For the signal to pass through the path, the edge input needs to take the non-control logic value of the logic gate. In order for a signal to propagate through a timing critical path in multiple clock phases, the edge inputs need to take specific non-control logic values at specific phases, respectively. For example, fig. 12 shows two and gates on a timing critical path across two logic stages. The two edge inputs of two and gates require a logic value of 1 at two consecutive clock phases. A finite state machine can be constructed that outputs a logical value of 1 when two edge inputs take logical value 1 at two consecutive clock phases.
The probability of a signal passing through a path depends on the probability that all edge inputs of the path take the corresponding non-control logic values, which can be estimated with some minimum probability that the edge inputs take the non-control logic values. Therefore, it is preferable to select the edge input with the smallest non-control logic value as the input to the finite state machine in the timing error prediction device so that the probability of occurrence of the timing error for the device is minimized, while selecting a small number of edge inputs reduces the silicon cost of the device. Such devices predict each event that a signal passes through a given timing critical path, any erroneous prediction results in performance degradation but not a logic error.
FIG. 13 shows a block diagram of a timing error detection apparatus that compares input and output signals of one level-sensitive latch and a previous level-sensitive latch when the level-sensitive latch is opaque in an integrated circuit that includes multiple phase level-sensitive latches, according to an embodiment of the present invention. In particular, FIG. 13 shows another embodiment of the present invention that is superior to the worst case design. In the integrated circuit shown in fig. 13, the signal is passed through a series of level sensitive latches controlled by a four phase clock signal. The latches become transparent in turn and opaque in turn. Each latch remains opaque in two consecutive clock phases. When a level sensitive latch is opaque, its previous level sensitive latch is also opaque, no signal should reach the logic network between them; otherwise, such a signal is a late signal that cannot pass through the level sensitive latch at the receiving end and will be destroyed in the following logic operation. Such late signals may be detected by a timing error detection device that includes a set of comparators, each comparator comparing the input and output of a level sensitive latch at the end of a timing critical path. Alternatively, if the signal is too late for the device at the end of the timing critical path to capture, a level sensitive latch and a timing error detection device may be inserted in the middle of the timing critical path, the inserted level sensitive latch being controlled by the same clock signal as the latch at the end of the timing critical path.
Inserting such a timing error detection device includes identifying a set of timing critical paths whose delays relative to a given set of clock signals do not exceed a given margin. Detection of a timing error invokes a timing error recovery mechanism, such as re-executing the erroneous operation, or a timing error correction mechanism, such as shifting the clock phase to capture a late signal.
The average performance of such an integrated circuit with a timing error prediction/detection device and a timing error recovery/correction mechanism depends on the occurrence probability of the event of predicting/detecting the timing error, the performance when the timing error does not occur, and the performance when the timing error occurs, including the performance degradation caused by the timing error recovery/correction. Thus, combinational logic network optimization in the integrated circuit may be directed to probabilistic targets such as average performance while taking into account the probability of occurrence of an event of a prediction/detection timing error. For example, timing critical path adaptations with small signal transmission probabilities are superior to worst case designs, timing error prediction/detection means can be inserted; timing critical paths with larger signal transmission probabilities are suitable for combinatorial logic optimization or latch removal and insertion to reduce signal transmission delays.
Fig. 14 shows a flow chart of an integrated circuit optimization method according to an embodiment of the invention, comprising the steps of: the method includes converting edge-triggered sequential elements into equivalent modules containing multiphase level-sensitive latches, performing level-sensitive latch retiming, performing more transitions to level-sensitive latches, performing level-sensitive latch retiming, and performing better than worst case design techniques. Specifically, FIG. 14 illustrates a preferred embodiment of the present invention, an integrated circuit optimization system and method, comprising the steps of: converting an edge triggered sequential element into an equivalent module containing multiphase level sensitive latches, level sensitive latches retiming, more to level sensitive latch conversion, level sensitive latch retiming, and advantages over worst case design techniques. There is typically an iterative process in which the integrated circuit is gradually optimized, and finally, all design criteria are met, to the completion of the design.
The present invention relates to an integrated circuit optimization system and method that includes converting edge-triggered sequential elements (e.g., flip-flops) into equivalent blocks containing multiphase level-sensitive latches, followed by optimization techniques based on the level-sensitive latches, such as level-sensitive latch retiming, and signal transmission through the level-sensitive latches based on prediction or detection, over worst-case designs.
This patent cites certain patents, patent applications, and other materials (such as articles). The text of these patents, patent applications, and other materials is only cited without conflict with other words and diagrams. The text of any conflicting patent, patent application and other material is not within the scope of this patent citation.
Further modifications and different embodiments of this invention in various aspects will be apparent to those skilled in the art in view of this disclosure. The purpose of this description is to illustrate and explain the general embodiments of the invention by those skilled in the art. It is to be understood that the manner of the invention shown and described is exemplary of the specific embodiments. The matters and materials shown and described may be substituted, parts and processes may be reversed, and certain functions of the invention may be utilized independently, as will be apparent to those skilled in the art from the description. Certain aspects described herein may be altered without departing from the spirit and scope of the invention as described in the following claims.
Claims (12)
1. An integrated circuit, comprising:
the edge-triggered timing element(s),
multiphase level sensitive latches deployed on critical timing paths,
a logic net between the multiphase level sensitive latches, an input signal of the logic net from a first set of level sensitive latches having the same or similar phase, an output signal of the logic net to a second set of level sensitive latches having the same or similar phase, the first set of level sensitive latches and the second set of level sensitive latches having different phases.
2. The integrated circuit of claim 1, wherein the first set of level-sensitive latches and the second set of level-sensitive latches are opposite in phase.
3. The integrated circuit of claim 2, wherein the first set of level sensitive latches and the second set of level sensitive latches, which are in opposite phases, form a flip-flop.
4. The integrated circuit of claim 1, further comprising:
a timing critical path through the at least one level sensitive latch,
a finite state machine extracts input signals from logic gates on the timing critical path, the finite state machine's output signals having determined values as signals pass through the timing critical path.
5. The integrated circuit of claim 4, wherein an output signal of the finite state machine controls a clock signal.
6. The integrated circuit of claim 1, further comprising a comparator that compares an input signal to an output signal of one level-sensitive latch when the one level-sensitive latch and all its previous level-sensitive latches are turned off.
7. The integrated circuit of claim 6, wherein an output of the comparator triggers a re-execution of an erroneous operation.
8. The integrated circuit of claim 6, wherein an output of the comparator triggers shifting a clock phase to capture a late signal.
9. An integrated circuit includes a multi-phase level sensitive latch.
10. The integrated circuit of claim 9, further comprising a logic net between the multiphase level sensitive latches.
11. The integrated circuit of claim 9, the multi-phase level-sensitive latch being disposed on a critical timing path.
12. An integrated circuit comprising any one or any combination of the features of claims 1-8.
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| US62/833,127 | 2019-04-12 | ||
| CN201910917462.2A CN111027276A (en) | 2018-10-09 | 2019-09-26 | Integrated circuit optimization system and method based on multiphase level sensitive latches |
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| SE507550C2 (en) * | 1995-10-17 | 1998-06-22 | Forskarpatent I Linkoeping Ab | Device at gates and flip-flops in the category of genuine single-phase clocked circuits |
| US6542999B1 (en) * | 1999-11-05 | 2003-04-01 | International Business Machines Corp. | System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock |
| JP4274457B2 (en) * | 2003-06-27 | 2009-06-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Transparent latch circuit |
| JP4419633B2 (en) * | 2004-03-25 | 2010-02-24 | 日本電気株式会社 | Logic circuit design system, logic circuit design method and program thereof |
| US7346861B1 (en) * | 2004-12-02 | 2008-03-18 | Altera Corporation | Programmable logic devices with two-phase latch circuitry |
| US8010923B1 (en) * | 2008-05-28 | 2011-08-30 | Xilinx, Inc. | Latch based optimization during implementation of circuit designs for programmable logic devices |
| US8305126B2 (en) * | 2011-01-13 | 2012-11-06 | Oracle International Corporation | Flop type selection for very large scale integrated circuits |
| US9558309B2 (en) * | 2014-05-09 | 2017-01-31 | University Of Southern California | Timing violation resilient asynchronous template |
| US10740519B2 (en) * | 2016-07-08 | 2020-08-11 | Trimsignal Ip Llc | Dynamic frequency boosting exploiting path delay variability in integrated circuits |
| US9954534B2 (en) * | 2016-09-16 | 2018-04-24 | Xilinx, Inc. | Methods and circuits for preventing hold time violations |
| WO2018132131A1 (en) * | 2017-01-15 | 2018-07-19 | Bao Liu | Optimization system and method for integrated circuits including multi-phase level-sensitive latches |
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