CN116192155A

CN116192155A - Viterbi decoding circuit with low time delay and automatic length adjustment of surviving path

Info

Publication number: CN116192155A
Application number: CN202211618272.9A
Authority: CN
Inventors: 吴琪; 陈谡; 刘洋
Original assignee: China Key System and Integrated Circuit Co Ltd
Current assignee: China Key System and Integrated Circuit Co Ltd
Priority date: 2022-12-15
Filing date: 2022-12-15
Publication date: 2023-05-30

Abstract

The invention discloses a Viterbi decoding circuit with low time delay and automatic length adjustment of surviving paths, which belongs to the field of digital communication and comprises a decoding control circuit, an interpolation circuit, a branch metric calculation circuit, an addition-comparison selection circuit and a surviving path backtracking circuit. The decoding control circuit generates decoding circuit control information according to the configuration; the interpolation circuit carries out interpolation operation on soft bit data with the code rate of 2/3 and 3/4 so as to restore the soft bit data into soft bit data with the code rate of 1/2; the branch metric calculating circuit calculates branch metric values corresponding to the soft bit data relative to 4 different outputs under the current node; the adding and comparing circuit calculates, compares and selects path metrics, selects surviving paths and stores node information into the SRAM; the survivor path backtracking circuit backtracks the survivor path and decodes the code word. The invention can reduce the circuit area, the pipeline decoding structure with low time delay can cope with burst data, the decoding speed and efficiency are improved, and the dynamic adjustment of the surviving path can cope with the decoding scene with unfixed packet length.

Description

Viterbi decoding circuit with low time delay and automatic length adjustment of surviving path

Technical Field

The invention relates to the technical field of digital communication, in particular to a Viterbi decoding circuit with low time delay and automatic adjustment of surviving path length.

Background

In digital communications, error correction codes (i.e., error control techniques) are effective means of improving the reliability of signal transmission and play an increasingly important role. Error correcting codes mainly include two kinds of block codes and convolutional codes. The performance of convolutional codes is better than block codes under the same code rate and encoder complexity. The decoding method of the convolution code mainly comprises algebraic decoding and probability decoding. Algebraic decoding is a code-based algebraic structure; the probability decoding is not only based on algebraic structure of the code, but also utilizes statistical characteristics of the channel, and can fully exert the characteristics of the convolution code, so that the decoding error probability is very small. The design of convolutional code decoders starts with high-performance complex decoders, whose decoding error probability can be very small as the decoding constraint length increases for initial sequence decoding of probability decoding. The Viterbi (Viterbi) decoding algorithm is one of the best probability decoding algorithms.

The Viterbi (Viterbi) decoding algorithm is a convolutional code decoding method proposed in 1967. The viterbi algorithm is a maximum likelihood decoding algorithm based on a trellis diagram of the code, i.e. the output selected by the decoder always gives the codeword with the largest log-likelihood function value. Omura demonstrates that the viterbi algorithm is equivalent to solving a dynamic programming solution for the shortest path problem through a weighted graph. When the constraint degree of the code is smaller, the Viterbi algorithm is higher in efficiency and speed than the sequence decoding algorithm, and the decoder is simpler. Therefore, since the proposal of the algorithm, the algorithm has been developed rapidly in theory and practice, and is widely applied to various digital transmission systems, particularly the fields of satellite communication, mobile communication and the like.

Disclosure of Invention

The invention aims to provide a Viterbi decoding circuit with low time delay and automatic length adjustment of surviving paths, which solves the problems of high time delay, high cache and fixed surviving paths of the prior Viterbi decoding circuit.

In order to solve the above technical problems, the present invention provides a viterbi decoding circuit with low delay and automatic adjustment of surviving path length, comprising:

a decoding control circuit for generating decoding circuit control information according to the configuration;

the interpolation circuit is used for carrying out interpolation operation on soft bit data with the code rate of 2/3 and 3/4 so as to restore the soft bit data into soft bit data with the code rate of 1/2;

the branch metric calculating circuit calculates branch metric values corresponding to the soft bit data relative to 4 different outputs under the current node;

the adding and comparing circuit is used for calculating, comparing and selecting path metrics, selecting surviving paths and storing node information of 64 paths into the SRAM;

and the surviving path backtracking circuit backtracks the surviving path and decodes the code word.

In one embodiment, the decoding control circuit outputs the decoded packet length information according to the input encoded packet length information and the encoding mode; dynamically adjusting the length of a surviving path according to the coding mode and the ending signal of the coding packet; and outputting the end signal of the decoding packet according to the end signal of the encoding packet and the working state of the decoding circuit.

In one embodiment, the surviving path length ranges from 8-48.

In one embodiment, the interpolation circuit recovers the interpolated single channel soft bit data as dual channel data.

In one embodiment, the branch metric calculation circuit calculates 4 possible branch metrics of the current node, wherein hard bit "0" is quantized into soft bit "5' b01111", and hard bit "1" is quantized into soft bit "5' b11111", and its complement is "5' b10001".

In one embodiment, the add-compare-select circuit includes an add function, a compare function, and a select function; wherein, the liquid crystal display device comprises a liquid crystal display device,

the adding function is as follows: selecting a corresponding branch metric according to the state of the current node and

inputs

0 and 1, and accumulating the selected branch metric value to the path metric value of the previous state to be used as one of the path metric values of the current state;

the ratio function is as follows: the current state generates two path metric values according to input, compares the two path metric values, selects a smaller path metric value as a unique metric value of the current state, and stores the current comparison result as node information of a path into an SRAM;

the selection function is as follows: and comparing the path metric values of 64 states under the current node, selecting the minimum metric value, and recording the State Best State where the minimum metric value is located.

In one embodiment, the surviving path backtracking circuit selects the State Best State of the final node as the backtracking starting point, reads path node information in the SRAM to backtrack, decodes 1bit code words by each node, and packages and sends the decoded code words in a single byte mode after backtracking is completed.

The Viterbi decoding circuit with low time delay and automatic length adjustment of surviving paths has the following beneficial effects:

(1) The low delay, the pipeline decoding circuit structure and the shorter surviving path length greatly reduce the delay of the decoder circuit, better deal with the data burst and effectively improve the decoding speed and efficiency;

(2) The resource consumption is low, the real-time property brought by the characteristic of the decoding circuit assembly line ensures that the soft bit data to be decoded does not need additional buffering, and the shorter surviving path length also ensures that the buffering consumed by the path node information is less, so that the resource consumption can be reduced to a great extent, and the circuit area is reduced;

(3) The surviving path length supports dynamic adjustment between 8 and 48, so that the problems caused by the fact that the size of a data block at the tail of a packet is not fixed due to the fact that the data of the same quantity are decoded into different quantities of data under different coding forms and the packet length is changed can be solved well.

Drawings

FIG. 1 is a schematic diagram of the overall architecture of a low latency, survivor path length self-adjusting Viterbi decoding circuit provided by the present invention;

FIG. 2 is a schematic diagram of a convolutional code encoding circuit;

FIG. 3 is a timing diagram of the entire Viterbi decoding circuit data path;

FIG. 4 is a schematic diagram of interpolation modes at different code rates for a data structure of a data packet;

FIG. 5 is a state transition diagram corresponding to a convolutional encoder;

fig. 6 is a schematic diagram of an add-compare-select node.

Detailed Description

The invention provides a low-delay and survivor path length automatic adjusting Viterbi decoding circuit, which is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention provides a low-delay and surviving path length automatic-adjusting Viterbi decoding circuit, the general architecture of which is shown in figure 1, comprising a decoding control Circuit (CTRL), an interpolation circuit (INST), a branch metric calculation circuit (BM), an addition and comparison circuit (ACS) and a surviving path backtracking circuit (TRB). The decoding control circuit outputs decoded packet length information (DEC_LEN) according to the input encoded packet length information (ENC_LEN) and the encoding MODE (ENC_MODE), dynamically adjusts the surviving path length according to the ENC_MODE and the END signal (ENC_END) of the encoded packet, and outputs the END signal of the decoded packet according to the END signal of the encoded packet and the working state of the decoding circuit, wherein the surviving path length ranges from 8 to 48; the interpolation circuit carries out interpolation operation on soft bit data with the code rate of 2/3 and 3/4 to restore the soft bit data into soft bit data with the code rate of 1/2, and restores the single-channel soft bit data after interpolation into double-channel data; the branch metric calculating circuit calculates Euclidean distance of soft bit data (DAT_ A, DAT _B) under the current node relative to 4 different outputs, wherein among 4 possible branch metrics of the current node, a hard bit of "0" is quantized into a soft bit of "5' B01111", a hard bit of "1" is quantized into a soft bit of "5' B11111", and the complementary code of the soft bit is "5' B10001"; the adding and comparing circuit completes calculation, comparison and selection of path metrics, selects surviving paths and stores node information of 64 paths into an SRAM; the survivor path backtracking circuit backtracks the survivor path and decodes the code word.

Fig. 2 shows a convolutional code coding circuit, 1bit input, 2bit output, and constraint length of 7. The 2bit output from the encoder is quantized into 2 5bit soft bit data, the most significant bit of the soft bit data is the sign bit, the output "0" is quantized into "5' b01111", the output "1" is quantized into "5' b11111", and its complement is "5' b10001".

Fig. 3 is a timing diagram (1/2 code rate) of the data path of the entire viterbi decoding circuit. The burst data block contains 64 pieces of 5-bit soft bit data, the selection of surviving paths is completed with very low delay through the pipeline structure of the interpolation circuit, the branch path calculation circuit and the addition and comparison circuit, and node information of 64 paths is recorded. Because of the nature of the viterbi decoding algorithm, trace-back must be performed after the selection of the surviving paths is completed and node information of 64 paths is recorded, and thus the surviving path trace-back circuit cannot join the pipeline structure, but the shorter surviving paths can also greatly reduce the delay of decoding.

Fig. 4 is a schematic diagram of a data structure of a data packet and interpolation modes at different code rates, wherein A0-A5 and B0-B5 are 2 soft bit data quantized by an output of an encoder, respectively. The data with 3/4 and 2/3 code rate needs to be interpolated by an interpolation circuit, the data is restored into the data with 1/2 code rate, and the ' 5' b00000 ' is inserted at the corresponding position, and the interpolation mode is shown in (a) and (b) of fig. 4. In fig. 4 (d), the data structure of a single data packet is shown, the data packet size is 1-1024 soft bit data, and is divided into a plurality of burst data blocks, each data block size is 64 soft bit data, and the data block size at the tail of the packet is 1-64 soft bit data.

The branch metric calculation circuit completes the branch metric calculation of the node. Specifically, the soft bit data dat_ A, DAT _b of the current node has 4 different branch metric values, namely bm_00, bm_01, bm_10 and bm_11, without knowing the state of the node and the input. Bm_00 represents the euclidean distance of data b_a with respect to "0_0", bm_01 represents the euclidean distance of data b_a with respect to "0_1", bm_10 represents the euclidean distance of data b_a with respect to "1_0", and bm_11 represents the euclidean distance of data b_a with respect to "1_1". Taking BM_11 as an example, the value of BM_11 is equal to the distance of B relative to "1" plus the distance of A relative to "1", and the distance data of A/B relative to "0/1", respectively, are shown in Table 1.

Table 1A/B distance data relative to "0/1", respectively

The decoding control circuit mainly completes automatic adjustment of the length of the surviving path. The data quantity of a data block of 64 soft bit data after interpolation recovery is different under different code rates, which also shows the difference of surviving path lengths. Specifically, under the 1/2 code rate, the data size after interpolation recovery is still 64 soft bit data, and a codeword of 32bits is decoded; under the 3/4 code rate, the data size after interpolation recovery is 96 soft bit data, and a 48bits code word is decoded; the data size after interpolation recovery under the 2/3 code rate is 80 soft bit data (the remaining 4 soft bit data without interpolation), and a 40bits codeword is decoded. The number of bits of the decoded codeword determines the size of the survivor path length. At a 1/2 code rate, the length of the surviving path is 32; at the 3/4 code rate, the length of the surviving path is 48; at 2/3 code rate, there will be 40 and 48 different surviving path lengths, because after decoding of one burst data block is completed, one burst data block will have 4 soft bit data that are not interpolated after decoding 40bits code words, two data blocks will have 8 soft bit data that are superimposed, the 8 soft bit data will be superimposed on the third data block, the third data block will have 72 soft bit data, and after interpolation recovery, 48bits code words can be decoded, i.e. the surviving path length is 48. When the size of the data block at the tail of the packet is less than 64, the length of the surviving path is determined by the pulse of the ENC_EOF signal, the length of the surviving path is 1-48, and the same processing mode is adopted under three code rates.

The adding and comparing circuit completes accumulation and comparison of path metrics, selects surviving paths according to path metric values and stores node information of 64 paths into the SRAM. FIG. 5 is a state transition diagram, root, corresponding to a convolutional encoderDetermining the next state and output according to the input ' 0/1 ' and the current state, wherein two states of the current node in the state transition diagram can only be transitioned to the state in the unbracked state in the next node, such as node ' S ₁ (S ₃₃ ) ", state S ₁ And S is ₃₃ Can be transferred to S at the next node ₂ And S is ₃ State, unable to transition to S ₃₄ And S is ₃₅ Status of the device. Specifically, the adding is mainly implemented in that a corresponding branch metric is selected according to the state of the current node and the input (0 and 1), and the selected branch metric value is added to the path metric value of the previous state to be used as one of the path metric values of the current state; the 'ratio' is mainly characterized in that the current state generates two path metric values according to input, the two path metric values are compared, a smaller path metric value is selected as a unique metric value of the current state, and the current comparison result is stored in the SRAM as node information of the path; the "selection" is mainly implemented by comparing the path metric values of 64 states under the current node, selecting the minimum metric value, and recording the State (Best State) where the minimum metric value is located.

As shown in fig. 6, which is a schematic diagram of an add-compare-select node, taking the surviving path length as 48 as an example, the branch metric value will continue to input a plurality of zero values into the add-compare-select circuit after the end of the add-compare-select (node 48) due to the coding characteristic of the convolutional code, so as to restore the decoder state, and the SRAM saves the node information of the node 7- > node 54. Regarding Best State, the following two points need to be described, and at the first point, path metric values of 64 STATEs at node 1 are all zero, and Best State (bs_start) is 63 (64 th State); second, the BEST STATE (bs_end) at node 54 is also 63 after STATE recovery.

The surviving path backtracking circuit is used for finishing backtracking of the surviving path, selecting a Best State of a final node as a backtracking starting point, reading path node information in the SRAM to backtrack, backtracking nodes 54-7, decoding 1bit code words by each node, and packaging and sending the decoded code words in a single byte mode after backtracking is finished.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A low latency, survivor path length auto-scaling viterbi decoding circuit comprising:

2. The low-latency, survivor path length automatically adjusting viterbi decoding circuit according to claim 1, wherein the decoding control circuit outputs the decoded packet length information according to the input encoded packet length information and the encoding mode; dynamically adjusting the length of a surviving path according to the coding mode and the ending signal of the coding packet; and outputting the end signal of the decoding packet according to the end signal of the encoding packet and the working state of the decoding circuit.

3. The low latency, self-adjusting survivor path length, viterbi decoding circuit according to claim 2, wherein said survivor path length ranges from 8-48.

4. The low-latency, survivor path length automatically adjusting viterbi decoding circuit according to claim 1, wherein the interpolation circuit restores the interpolated single channel soft bit data to double channel data.

5. The low-latency, survivor path length automatically adjusting viterbi decoding circuit according to claim 1, wherein the branch metric calculation circuit calculates 4 possible branch metrics for the current node, wherein hard bit "0" is quantized to soft bit "5' b01111", and hard bit "1" is quantized to soft bit "5' b11111", with the complement of "5' b10001".

6. The low latency, survivor path length automatically adjusting viterbi decoding circuit according to claim 1, wherein the add-compare-select circuit comprises an add function, a compare function, and a select function; wherein, the liquid crystal display device comprises a liquid crystal display device,

the adding function is as follows: selecting a corresponding branch metric according to the state of the current node and inputs 0 and 1, and accumulating the selected branch metric value to the path metric value of the previous state to be used as one of the path metric values of the current state;

the selection function is as follows: and comparing the path metric values of 64 states under the current node, selecting the minimum metric value, and recording the state BestState where the minimum metric value is located.

7. The low-latency, survivor path length automatically-adjusted viterbi decoding circuit according to claim 1, wherein the survivor path traceback circuit selects a state BestState of a final node as a starting point of traceback, reads path node information in the SRAM to trace back, decodes 1bit code words from each node, and packages the decoded code words in a single byte manner after the traceback is completed.