CN116191842A

CN116191842A - High-voltage integrated circuit

Info

Publication number: CN116191842A
Application number: CN202310449346.9A
Authority: CN
Inventors: 冯宇翔; 谢荣才
Original assignee: Guangdong Huixin Semiconductor Co Ltd
Current assignee: Guangdong Huixin Semiconductor Co Ltd
Priority date: 2023-04-25
Filing date: 2023-04-25
Publication date: 2023-05-30
Anticipated expiration: 2043-04-25
Also published as: CN116191842B

Abstract

The invention provides a high voltage integrated circuit, comprising: the power supply circuit, the high-side driving circuit of the 3 channels, the low-side driving circuit of the 3 channels and the PFC controller driving circuit of the 1 channels; the high-side driving circuit is electrically connected with the low-side driving circuit and the power supply circuit respectively, and the PFC controller driving circuit is electrically connected with the low-side driving circuit; the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit; the PFC controller driving circuit comprises a PFC current protection circuit and a temperature protection circuit; the PFC current protection circuit comprises a first comparator, a first MOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a second MOS tube, an inverter and a counting circuit, wherein the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series, and the positive input end of the first comparator is connected with PFC signal input. The high-voltage integrated circuit has wide application range, is convenient for improving the flexibility of the drive IC and has strong market competitiveness.

Description

High-voltage integrated circuit

Technical Field

The invention relates to the technical field of intelligent power modules, in particular to a high-voltage integrated circuit.

Background

The high voltage integrated circuit, HVIC (High Voltage Integrated Circuit), is an integrated circuit product that converts MCU signals to drive IGBT signals. The HVIC integrates the PMOS tube, the NMOS tube, the triode, the diode, the voltage stabilizing tube, the resistor and the capacitor to form circuits such as a Schmitt, a low voltage LEVELSHIFT, a high voltage LEVELSHIFT, a pulse driving circuit, a dead zone circuit, an interlocking circuit, a delay circuit, a filter circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage protection circuit and the like. On one hand, the HVIC receives the control signal of the MCU to drive the subsequent IGBT or MOS to work, and on the other hand, the HVIC sends the state detection signal of the system back to the MCU. Is a critical chip inside the IPM.

Along with the rapid development of industry, the IPM intelligent power module is widely applied to various fields, particularly in the field of white household appliances, along with the miniaturization, high reliability, safety and miniaturization trend of the volume design of a variable-frequency electric control main board of household products, the driving IC inside the traditional IPM intelligent power module has basic functions and is difficult to adapt to development requirements. With the rapid development of industry and society, the electric control system is required to have higher reliability and safety, various protection requirements are more perfect, such as over-current protection, overvoltage protection, temperature protection and other functional protection can be applicable to various application occasions, and the proper protection threshold value is intelligently selected in different application occasions.

However, the high-voltage integrated circuit has poor current protection effect, poor flexibility of the driving IC, low reliability, and poor market competitiveness.

Disclosure of Invention

Aiming at the defects of the related technology, the invention provides a high-voltage integrated circuit which has good current protection effect, is convenient for improving the flexibility, the reliability and the market competitiveness of a driving IC.

In order to solve the above technical problems, an embodiment of the present invention provides a high voltage integrated circuit, including: the power supply circuit, the high-side driving circuit of the 3 channels, the low-side driving circuit of the 3 channels and the PFC controller driving circuit of the 1 channels; the high-side driving circuit is electrically connected with the low-side driving circuit and the power supply circuit respectively, and the PFC controller driving circuit is electrically connected with the low-side driving circuit;

the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit;

the PFC controller driving circuit comprises a PFC current protection circuit and a temperature protection circuit;

the PFC current protection circuit comprises a first comparator, a first MOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a second MOS tube, an inverter and a counting circuit, wherein the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series, the positive input end of the first comparator is connected with PFC signal input, the negative input end of the first comparator is connected between the first resistor and the second resistor, the output end of the first comparator is connected with the first end of the counting circuit, and the second end of the counting circuit is connected with signal output end; the source electrode of the first MOS tube and the drain electrode of the first MOS tube are respectively connected with two ends of the third resistor, and the grid electrode of the first MOS tube is connected with the temperature protection circuit; the source electrode of the second MOS tube and the drain electrode of the second MOS tube are respectively connected with two ends of the fourth resistor, the source electrode of the second MOS tube is grounded, the grid electrode of the second MOS tube is connected with the first end of the reverser, and the second end of the reverser is connected with the output end of the first comparator.

Preferably, the high voltage integrated circuit further comprises an interlock and dead zone circuit connected between the high side drive circuit and the low side drive circuit.

Preferably, the high-voltage integrated circuit further comprises an enabling circuit, an overcurrent protection circuit and a power supply undervoltage protection circuit, wherein the enabling circuit and the overcurrent protection circuit are respectively connected with the high-side driving circuit, and the power supply undervoltage protection circuit is connected with the power supply circuit.

Preferably, the interlocking and dead zone circuit comprises a third MOS tube, a source electrode of the third MOS tube is connected with bias voltage, a drain electrode of the third MOS tube is connected with supply voltage, and a grid electrode of the third MOS tube is used for being connected with the input and output circuit.

Preferably, the high-voltage integrated circuit further comprises a VREG generation circuit, an RC filter circuit, a Schmidt trigger circuit, a low-pass filter, a level conversion circuit, a three AND gate, a pulse driving circuit, a delay circuit, a fault logic control circuit, a fault output circuit and a high-voltage region detection circuit; the VREG generation circuit is connected with the undervoltage power protection circuit, the undervoltage power protection circuit is connected with the fault logic control circuit, the RC filter circuit is sequentially connected with the level conversion circuit and the fault logic control circuit, the fault logic control circuit is respectively connected with the PFC current protection circuit, the temperature protection circuit and the input ends connected with the three AND gates, the output ends of the three AND gates are connected with the first end of the pulse driving circuit, and the second end of the pulse driving circuit is connected with the fault output circuit.

Preferably, the bootstrap circuit includes a first capacitor, a high-side power tube Q1, a low-side power tube Q2, a MOS tube Q3, a high-side driving switch for connecting a high-side driving signal, and a low-side driving switch for connecting a low-side driving signal; the first end of the high-side driving switch is respectively connected with the source electrode of the MOS tube Q3 and the first end of the first capacitor, and the second end of the high-side driving switch is connected with the base electrode of the high-side power tube Q1; the third end of the high-side driving switch is respectively connected with the second end of the first capacitor and the emitter of the high-side power tube Q1, and the collector of the high-side power tube Q1 is connected with a power supply voltage; the drain electrode of the MOS tube Q3 is connected with the power supply voltage, the grid electrode of the MOS tube Q3 is connected with the input end of the low-side driving switch, the output end of the low-side driving switch is connected with the base electrode of the low-side power tube Q2, the emitter electrode of the low-side power tube Q2 is connected with the first resistor and grounded, and the collector electrode of the low-side power tube Q2 is connected with the emitter electrode of the high-side power tube Q1.

Preferably, the overcurrent protection circuit comprises a second comparator, a fifth resistor, a sixth resistor, a seventh resistor and a fourth MOS tube; the positive input end of the second comparator is used for being connected with a current detection signal, the negative input end of the second comparator is connected between the first end of the fifth resistor and the first end of the sixth resistor, and the output end of the second comparator is connected with the fault logic control circuit; the second end of the fifth resistor is connected with a reference voltage, the second end of the sixth resistor is connected with the first end of the seventh resistor, and the second end of the seventh resistor is grounded;

the source electrode of the fourth MOS tube is connected with the second end of the seventh resistor, the drain electrode of the fourth MOS tube is connected with the first end of the seventh resistor, and the grid electrode of the fourth MOS tube is connected with the fault logic control circuit.

Preferably, the temperature protection circuit comprises a third comparator, an eighth resistor, a ninth resistor, a tenth resistor and a fifth MOS tube; the positive input end of the third comparator is used for being connected with a current detection signal, the negative input end of the third comparator is connected between the first end of the eighth resistor and the first end of the ninth resistor, and the output end of the third comparator is connected with the fault logic control circuit; the second end of the eighth resistor is connected with a reference voltage, the second end of the ninth resistor is connected with the first end of the tenth resistor, and the second end of the tenth resistor is grounded;

the source electrode of the fifth MOS tube is connected with the second end of the tenth resistor, the drain electrode of the fifth MOS tube is connected with the first end of the tenth resistor, and the grid electrode of the fifth MOS tube is connected with the fault logic control circuit.

Preferably, the counting circuit comprises a first JK trigger, a second JK trigger and an and gate, wherein the first JK trigger is connected with the second JK trigger, and the and gate is also connected with the first JK trigger and the second JK trigger respectively.

Preferably, the high-voltage integrated circuit further comprises a temperature sampling circuit, the temperature sampling circuit comprises an eleventh resistor and an adjustable resistor, a first end of the eleventh resistor is connected with the power supply voltage, a second end of the eleventh resistor is connected with the first end of the adjustable resistor, and a second end of the adjustable resistor is grounded.

Compared with the related art, the PFC controller driving circuit is electrically connected with the low-side driving circuit by electrically connecting the high-side driving circuit with the low-side driving circuit and the power supply circuit respectively; the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit; the temperature protection circuit detects the frequency of the driving signal and selects an overtemperature threshold value for realizing a protection function; the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series, the positive input end of the first comparator is connected with PFC signal input, the negative input end of the first comparator is connected between the first resistor and the second resistor, the output end of the first comparator is connected with the first end of the counting circuit, and the second end of the counting circuit is connected with the signal output end; the source electrode of the first MOS tube and the drain electrode of the first MOS tube are respectively connected with two ends of the third resistor, and the grid electrode of the first MOS tube is connected with the temperature protection circuit; the source electrode of the second MOS tube and the drain electrode of the second MOS tube are respectively connected with two ends of the fourth resistor, the source electrode of the second MOS tube is grounded, the grid electrode of the second MOS tube is connected with the first end of the reverser, and the second end of the reverser is connected with the output end of the first comparator. In this way, the triggering threshold value of the over-current protection through the PFCTRIP is reduced along with the temperature rise of the IGBT of the PFC power element, and when the over-current protection of the PFC of the previous two times is triggered, the PFC drive is only turned off, the three-phase inversion drive is not affected, the over-current protection of the PFCTRIP is performed for the third time, and meanwhile, the PFC drive and the three-phase inversion drive are turned off, so that the whole system is protected, and the over-current protection device is suitable for 7-channel drive HVIC of an application scene. The flexibility of the driving IC is improved, so that the driving IC is suitable for more application occasions, has higher reliability and improves the market competitiveness of products.

Drawings

The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the accompanying drawings:

FIG. 1 is a block diagram of a high voltage integrated circuit of the present invention;

FIG. 2 is a circuit diagram of a high voltage integrated circuit according to the present invention;

FIG. 3 is a first partial enlarged view of FIG. 2;

FIG. 4 is a second enlarged partial view of FIG. 2;

FIG. 5 is a circuit diagram of an interlock and dead zone circuit of the present invention;

FIG. 6 is a circuit diagram of a bootstrap circuit of the present invention;

FIG. 7 is a circuit diagram of an over-current protection circuit of the present invention;

FIG. 8 is a circuit diagram of the temperature protection circuit of the present invention;

fig. 9 is a circuit diagram of the PFC current protection circuit of the present invention;

FIG. 10 is a circuit diagram of the counting circuit of FIG. 9;

FIG. 11 is a circuit diagram of a temperature sampling circuit according to the present invention;

fig. 12 is a schematic diagram of the dead time test criteria of the interlock and dead time circuit of the present invention.

Detailed Description

The following describes in detail the embodiments of the present invention with reference to the drawings.

The detailed description/examples set forth herein are specific embodiments of the invention and are intended to be illustrative and exemplary of the concepts of the invention and are not to be construed as limiting the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to adopt other obvious solutions based on the disclosure of the claims and specification of the present application, including those adopting any obvious substitutions and modifications to the embodiments described herein, all within the scope of the present invention.

Example 1

As shown in fig. 1-12, the present invention provides a high voltage integrated circuit 100 comprising: a power supply circuit 1, a high-side driving circuit 2 of 3 channels, a low-side driving circuit 3 of 3 channels and a PFC controller driving circuit 4 of 1 channel; the high-side driving circuit 2 is electrically connected with the low-side driving circuit 3 and the power supply circuit 1 respectively, and the PFC controller driving circuit 4 is electrically connected with the low-side driving circuit 3; the high-side driving circuit 2 comprises a high-side undervoltage protection circuit 201 and a bootstrap circuit 202; the PFC controller driving circuit 4 includes a PFC current protection circuit 41 and a temperature protection circuit 42.

The high-side driving circuit 2 internally comprises a high-side under-voltage protection circuit 201 and a bootstrap circuit 202, and is used for realizing a high-side driving under-voltage protection function and a bootstrap power supply function.

The power supply circuit 1 includes a 5V LDO circuit and a 1.2V BANDGAP circuit, supplies 5V voltage to all circuits inside the HVIC and to external circuits, and provides a stable 1.2V voltage reference to the HVIC and to external circuits.

Therefore, the trigger threshold value through over-temperature protection is improved along with the improvement of the working frequency of PFC, and the method is suitable for 7-channel driving HVIC of various different temperature protection application scenes. The switching device of the PFC circuit is a MOSFET made of SiC material, the working frequency of the switching device can be quite high, and the working temperature of the MOSFET made of SiC material is quite high compared with that of the switching device made of Si material due to the characteristic of the SiC material, so that the trigger threshold of over-temperature protection can be improved. The switching device of the PFC circuit is a switching device made of Si material, the working frequency of the switching device is lower, and the working temperature of the switching device made of Si material is lower due to the characteristic of Si material, so that the trigger threshold of over-temperature protection is lowered. The flexibility of the driving IC is improved, so that the driving IC is suitable for more application occasions, and the market competitiveness of products is improved.

In this embodiment, the PFC current protection circuit 41 includes a first comparator 0813, a first MOS tube 0807, a first resistor 0801, a second resistor 0802, a third resistor 0806, a fourth resistor 0803, a second MOS tube 0805, an inverter 0809 and a counting circuit 37, the first resistor 0801, the second resistor 0802, the third resistor 0806 and the fourth resistor 0803 are sequentially connected in series, a positive input end of the first comparator 0813 is connected with PFC signal input, a negative input end of the first comparator 0813 is connected between the first resistor 0801 and the second resistor 0802, an output end of the first comparator 0813 is connected with a first end of the counting circuit 37, and a second end of the counting circuit 37 is connected with signal output end; the source electrode of the first MOS tube 0807 and the drain electrode of the first MOS tube 0807 are respectively connected with two ends of the third resistor 0806, and the gate electrode of the first MOS tube 0807 is connected with the temperature protection circuit 42; the source electrode of the second MOS tube 0805 and the drain electrode of the second MOS tube 0805 are respectively connected with two ends of the fourth resistor 0803, the source electrode of the second MOS tube 0805 is grounded, the gate electrode of the second MOS tube 0805 is connected with the first end of the inverter 0809, and the second end of the inverter 0809 is connected with the output end of the first comparator 0813. The triggering threshold value of the PFC overcurrent protection is reduced along with the temperature rise of the IGBT of the PFC power element, when the PFC overcurrent protection of the former two times is triggered, only the PFC drive is turned off, the three-phase inversion drive is not affected, the third-time PFCTRIP overcurrent protection is performed, the PFC drive and the three-phase inversion drive are turned off, the whole system is protected, and the PFC overcurrent protection device is suitable for 7-channel drive HVIC of an application scene. The flexibility of the driving IC is improved, so that the driving IC is suitable for more application occasions, has higher reliability and improves the market competitiveness of products.

In this embodiment, the counting circuit 37 includes a first JK flip-flop 0810, a second JK flip-flop 0811, and an and gate 0812, wherein the first JK flip-flop 0810 is connected to the second JK flip-flop 0811, and the and gate 0812 is also connected to the first JK flip-flop 0810 and the second JK flip-flop 0811, respectively.

Specifically, the PFC current protection circuit 41 is composed of a first comparator 0813 (CMP), a first MOS tube 0807, a second MOS tube 0805, a voltage dividing resistor, a reference voltage, a counting circuit 37, and a unit time control interface CP, a PFCTRIP signal is input to a positive input terminal of the first comparator 0813, and a VREF is divided by the first resistor 0801, the second resistor 0802, the fourth resistor 0803, and the third resistor 0806, and then a reference voltage signal of a voltage dividing point 0804 is obtained and input to a negative input terminal of the first comparator 0813; the D end of the first MOS tube 0807 is connected to the connection end of the second resistor 0802 and the third resistor 0806, and the S end of the first MOS tube 0807 is connected to the connection end of the third resistor 0806 and the fourth resistor 0803, so as to form the parallel connection of the first MOS tube 0807 and the third resistor 0806. The G pole of the first MOS transistor 0807 is connected to the PFC power element temperature detection circuit and the temperature protection circuit 42 to output signals.

The output end of the first comparator 0813 is connected to the input end of the inverter 0809, the output end of the inverter 0809 is connected with the G pole of the second MOS tube 0805, the S pole of the second MOS tube 0805 is connected with one end of the fourth resistor 0803 to be grounded, the D pole of the second MOS tube 0805, the other end of the fourth resistor 0803, the S pole of the first MOS tube 0807 and one end of the third resistor 0806 are connected together. Meanwhile, the output end of the first comparator 0813 is connected to the counting circuit 37, the counting circuit 37 mainly comprises a first JK trigger 0810 and a second JK trigger 0811, and J1, K1, J2 and K2 of the first JK trigger 0810 and the second JK trigger 0811 are connected together to be connected to VREF.

The first and second JK flip-

flops

0810 and 0811/R1/R2 are connected together and led out as an external unit time control input port/CR. The output end of the first comparator 0813 is connected to the design number pulse input port CP1 of the first JK flip-flop 0810, the output end Q1 of the first JK flip-flop 0810 is connected to the design number pulse input port CP2 of the second JK flip-flop 0811, meanwhile, the output end Q1 of the first JK flip-flop 0810 is led OUT to the PFC driving circuit control port OUTPFCIN, the output end Q1 of the first JK flip-flop 0810 and the output end Q2 of the second JK flip-flop 0811 are respectively connected to two input ports of the and gate 0812, and the output end OUT of the and gate 0812 is connected to the input port of the fault logic circuit of the HVIC.

The PFC current protection circuit 41 operates on a principle that is divided into two parts:

the over-current protection threshold value of the PFCTRIP is controlled by the temperature of a PFC circuit power device, when the temperature sampled by a temperature sampling circuit of the PFC circuit power device is compared by a temperature protection circuit 42, if the sampled temperature is higher than a set temperature, a third comparator output signal of the temperature protection circuit 42 is given to a first MOS tube 0807, the controlled MOS tube is turned off, a third resistor 0806 is connected into a voltage division loop, and the voltage of a voltage division point 0804 is reduced, so that the over-current protection threshold value of the PFCTRIP is reduced to LA; if the sampled temperature is lower than the set temperature, the third comparator 0706 of the temperature protection circuit 42 outputs a signal to the first MOS tube 0807, and the controlled MOS tube is turned on, so that the third resistor 0806 is not connected to the voltage division loop, the voltage of the voltage division point 0804 is increased, and the PFCTRIP overcurrent protection threshold is HA. Wherein, relation of the overcurrent capacity of the IGBT and the temperature thereof: the higher the temperature, the less the overcurrent capability of the IGBT, and when the temperature is high to some extent, the IGBT will fail.

In the PFCTRIP overcurrent protection function, no matter in the PFC overcurrent protection high threshold or the PFC overcurrent protection low threshold, when the PFCTRIP signal sampled by PFC current is higher than the current protection threshold, for example, the voltage value of the voltage division point 0804, the third comparator 0706 controls the output signal PFCIN to turn off the PFC driving control PWM to protect the PFC circuit, meanwhile, the counting circuit 37 starts to calculate the frequency of PFCTRIP overcurrent, the/R1 unit time control signal is the length of unit time set by the external MCU according to the system requirement or the own control scheme, when the frequency of occurrence of the PFCTRIP overcurrent protection in the unit time is less than or equal to 2, the PWM signal of the OUTPFCIN is turned off when the overcurrent protection occurs, but the OUT of the counting circuit is PWM which does not control the three-phase driving. If three overcurrent protection occurs in a unit time, when the overcurrent protection occurs, the PWM signal of the OUTPFCIN is turned off, and the OUT of the same counter circuit 37 outputs a control signal to turn off the PWM of the three-phase drive, thereby protecting the whole drive HVIC circuit. Counting circuit theory of operation: the counting circuit 37 is composed of two JK flip-flops, and a counting pulse is input from the CP terminal of the first JK flip-flop 0810 (lower flip-flop) when counting is started, and the state of Q1 is changed once every time a counting pulse is input. The Q terminal of the first JK flip-flop 0810 is connected to the CP terminal of the high-level flip-flop. The high flip-flop toggles whenever the state of the first JK flip-flop 0810 changes from 1 to 0, i.e., a negative transition pulse is output. The first JK flip-flop 0810 and the second JK flip-flop 0811 are connected in parallel with the 0 end (timing end)/R as the clear 0 end (timing end), and after the clear 0, the flip-flop is made to be at the initial state of 00.

When the first counting pulse is input, the pulse trailing edge enables Q1 to be changed from 0 to 1, Q2 are kept in 0 state, and the state of the counter is 01. When the second counting pulse is input, the pulse trailing edge changes Q1 from 1 to 0, Q2 from 0 to 1, and the state of the counter is 10. When the third count pulse is input, the pulse trailing edge changes Q1. from 0 to 1, Q2 remains in the 1 state, and the counter is in the 11 state. Three times of overcurrent protection are carried OUT in unit time, Q1 and Q2 are both 1, and the output 1 of the AND gate 0812 OUT controls the turn-off protection HVCI of the three-phase driving PWM.

In the present embodiment, the high-voltage integrated circuit 100 further includes an interlock and dead zone circuit 5, the interlock and dead zone circuit 5 being connected between the high-side driving circuit 2 and the low-side driving circuit 3. An interlock and dead zone circuit 5 is used to implement an interlock and dead zone function for the high side drive circuit 2 and the low side drive circuit 3.

In this embodiment, the high-voltage integrated circuit 100 further includes an enable circuit 6, an over-current protection circuit 7, and an under-voltage power protection circuit 8, where the enable circuit 6 and the over-current protection circuit 7 are respectively connected to the high-side driving circuit 2, and the under-voltage power protection circuit 8 is connected to the power circuit 1. The power supply circuit 1 is connected with a power supply under-voltage protection circuit 8 to realize a power supply under-voltage protection function. An enabling circuit 6 contained inside the HVIC for realizing an enabling function; the overcurrent protection circuit 7 realizes an overcurrent protection function, and the overvoltage protection circuit realizes an overvoltage protection function; the fault reporting circuit outputs fault reporting signals to the outside when conditions such as under-voltage, over-current, PFC faults, over-voltage, over-temperature and the like occur in the fault reporting circuit.

In this embodiment, the interlock and dead zone circuit 5 includes a third MOS transistor 51, a source of the third MOS transistor 51 is connected to a bias voltage, a drain of the third MOS transistor 51 is connected to a supply voltage, and a gate of the third MOS transistor 51 is connected to the input/output circuit 36. The dead zone circuit is mainly used for generating dead zone time and avoiding false triggering when the power switch control signal is overturned. The HVIC controls the three-phase inverter power device, and the feedback current or voltage signal is often affected by noise generated when the power device is switched, so that the signal input into the chip is superimposed with peak noise caused by the parasitic inductance of the conductive wire and the parasitic capacitance of the chip, and the peak noise can cause false triggering in the chip and output a wrong control signal. In order to avoid the influence of peak noise, the operation circuit of the feedback signal is shielded in a period from the time when the control signal is turned over to the time when the feedback signal is stable, and the period is dead time. Jian Shandian the turn-on and turn-off of the upper and lower switching devices (such as IGBTs and MOS transistors) of the same bridge arm are staggered for a certain time, namely dead time, so as to ensure that the upper and lower IGBTs of the same bridge arm are always turned off and then turned on.

By using resistors, capacitors and diodes to form the RC charge delay circuit 15, the charge speed is slow and the discharge speed is fast. The rising edge of the pulse is slowed down and the falling edge is unchanged. This is the principle of dead zone generation, which can be modified by adjusting the values of R, C. Dead time DT test criteria. Where Ton is the output rising edge propagation delay, toff is the output falling propagation delay, tr is the output rising time, and Tf is the output falling time.

To avoid that the output signals HO1, LO1, HO2, LO2, HO3, LO3 of the HVIC are simultaneously high, an interlock circuit has to be introduced, which is set to a level when HIN and LIN are simultaneously high. If HO and LO are at high level at the same time, the subsequent IGBT and other elements are turned on at the same time, and a large current flows, which causes damage to the IGBT and other subsequent elements. When the two input ends are logic 1, the two output ends are logic 0, and the input and output are the same logic in the rest cases.

In this embodiment, the high voltage integrated circuit 100 further includes a VREG generating circuit 9, an RC filter circuit 10, a schmitt trigger circuit 11, a low-pass filter 12, a level shifter circuit 13, a three and gate 38, a pulse driver circuit 14, a delay circuit 15, a fault logic control circuit 16, a fault output circuit 17, and a high voltage region detection circuit 39; the VREG generation circuit 9 is connected with the under-voltage power supply protection circuit 8, the under-voltage power supply protection circuit 8 is connected with the fault logic control circuit 16, the RC filter circuit 10 is sequentially connected with the level conversion circuit 13 and the fault logic control circuit 16, the fault logic control circuit 16 is respectively connected with the PFC current protection circuit 41, the temperature protection circuit 42 and the input ends connected with the three AND gates, the output end of the three AND gates 38 is connected with the first end of the pulse driving circuit 14, and the second end of the pulse driving circuit 14 is connected with the fault output circuit 17.

Specifically, the VREG generating circuit (VREG/VCC) is required to generate a VREG of 7V to 8V in order to receive a logic 1 signal of 5V such as MCU, and the supply voltage TYPE for the driver IC is generally 15V. A VREG signal of 7.2V with good temperature characteristics is generated, and meanwhile, a 5V power supply is also needed to supply power to an MCU processor integrating a sine wave algorithm.

RC filter circuit 10, known as Resistor-capacitor circuit (Resistor-Capacitance circuit), is a passive interference-free filter circuit comprising a Resistor and a capacitor. For removing unnecessary high frequency components from the input signal and removing high frequency interference.

SCHMITT trigger 11 (SCHMITT) filters the level noise of the input circuit by passing both PWM IN, ITRIP, TVC, EN through the SCHMITT trigger first, with a logic 0 maximum of 0.8V and a logic 1 minimum of 2.9V.

The low-pass filter 12 (TWIN FILTER) is used for filtering high-frequency noise of the input circuit, and for providing sufficient charging time for VB, so as to avoid that the driven back-end circuit works in a state of insufficient VB voltage (which reduces the efficiency of the back-end circuit), and the frequency range of the input signal needs to be limited, and the signal with the excessive frequency needs to be filtered. Signals generally above 600 KHz-700 KHz should be filtered out.

The VREG-VCC LEVEL conversion circuit 13 (VREG 2 VCC LEVEL SHIFT) has a small current due to the HVIC being a MOS circuit, but has a limited current capability of VREG, and cannot drive too many circuits, and after schmitt trigger and low-pass filtering, voltage conversion is generally performed first, and the driving voltage is converted from VREG to VCC.

The pulse driving circuit 14 is used for respectively generating pulses at the rising edge and the falling edge of the HIN signal, so that the high-voltage DMOS transistor of the high-voltage region detection circuit is instantaneously turned on, and the signal of the instantaneous conduction is recorded by the RS trigger to control HO to be synchronous with the HIN. The continuous high-low signal of HIN cannot be used to control the turn-on of DMOS because when VS is 600V-650V, VB is 615V-675V, VB is a voltage formed by a voltage pump, has limited energy, and generally does not have the capability of continuously flowing through the turned-on DMOS to ground; if a continuous current loop is generated between VB and ground, VB will be quickly reduced and enter a low-voltage protection area, so that the driving IC cannot work normally. Thus, the introduction of PLUSEGEN circuits is necessary, and more PLUSEGEN signals are used in the driver IC, including ONESHOT circuits (generating one pulse) and DOUBLELPLUSE circuits (generating two pulses). In the general use occasion, an ONESHOT circuit is enough; for circuits where VS will be pulled lower (typically with a large inductance in the subsequent circuit), a doubleple circuit will be used.

Delay circuit 15 is used to delay the LO signal output so that the HO output signal and the LO output signal remain identical.

The undervoltage protection circuit 8 is used for stopping the driving IC (keeping the output in logic 0 state) when the voltage is too low so as to protect the subsequent circuits. Therefore, in the low voltage region, there should be a low voltage protection circuit for detecting the VCC level. VCC starts to fall from high potential, after being lower than 13V, the output keeps logic 0; when VCC rises from the low point, above 13.7V, a hold logic 1 is output. I.e. there is a difference of 0.7V between them. To better protect the subsequent circuitry, the output is not high until the supply voltage is indeed high enough. In consideration of power supply noise, the delay circuit 15 should be added at the end of the circuit, so that no malfunction occurs in the output when the power supply voltage due to the power supply noise is instantaneously lowered.

In which the driver IC should be deactivated (keep the output in a logic 0 state) when the voltage is too low to protect the subsequent circuits. Therefore, in the low voltage region, there should be a low voltage protection circuit for detecting the VCC level.

When VCC starts to fall from high potential and is lower than 13V, the output keeps logic 0; when VCC rises from the low point, above 13.7V, a hold logic 1 is output. I.e. there is a difference of 0.7V between them.

This is mainly to better protect the subsequent circuits, and the output will not go high until the supply voltage is indeed high enough. In consideration of power supply noise, a delay circuit is added at the end of the circuit, so that when the power supply voltage caused by the power supply noise is instantaneously lowered, misoperation does not occur in output.

The fault logic control circuit 16 receives fault signals of each functional circuit, makes fault processing according to each fault signal, and turns off the corresponding function or turns off all the functions of the HVIC according to the importance of the fault, thereby protecting the HVIC and the whole application circuit. When the undervoltage protection function signal UVLO is 0, the fault logic control circuit 16 outputs a fault signal to the fault output circuit 17, meanwhile, the HVIC enters an undervoltage protection function, six paths of PWM waves of the HVIC are turned off, the undervoltage protection function, the ITRIP, PFCTRIP current protection function and the temperature protection function are respectively in normal fault-free function, when the undervoltage protection function signal UVLO is 0, the fault logic control circuit 16 outputs a fault signal to the fault output circuit 17, meanwhile, the HVIC also enters corresponding function protection, and the HVIC stops six paths of PWM wave output and stops working.

The fault output circuit 17 is a MOS tube, the base electrode of the MOS tube is connected to the output end of the fault logic control circuit 16, the fault logic control circuit 16 controls the on-off of the fault output MOS, the D of the MOS tube is suspended, a pull-up resistor is required to be externally added to the HVIC, and when the fault logic control circuit 16 outputs 1, the MOS tube is turned on to output FO signals to external equipment. When the fault logic control circuit 16 outputs 0 (HVIC has no fault), the MOS is turned off and the FO signal is high.

In this embodiment, the bootstrap circuit 202 includes a first capacitor C1, a high-side power transistor Q1, a low-side power transistor Q2, a MOS transistor Q3, a high-side driving switch 18 for connecting a high-side driving signal, and a low-side driving switch 19 for connecting a low-side driving signal; a first end of the high-side driving switch 18 is respectively connected with the source electrode of the MOS tube Q3 and the first end of the first capacitor, and a second end of the high-side driving switch 18 is connected with the base electrode of the high-side power tube Q1; a third end of the high-side driving switch 18 is respectively connected with a second end of the first capacitor C1 and an emitter of the high-side power tube Q1, and a collector of the high-side power tube Q1 is connected with a power supply voltage (310 VDC); the drain electrode of the MOS tube Q3 is connected with the power supply Voltage (VCC), the grid electrode of the MOS tube Q3 is connected with the input end of the low-side driving switch 19, the output end of the low-side driving switch 19 is connected with the base electrode of the low-side power tube Q2, the emitter electrode of the low-side power tube Q2 is connected with a resistor and grounded, and the collector electrode of the low-side power tube Q2 is connected with the emitter electrode of the high-side power tube Q1.

Specifically, a capacitor is required to be added between VB and VS by the bootstrap circuit 202 formed by using MOS transistors, as shown in fig. 5, the MOS transistor Q3 and the first capacitor C1 form a complete bootstrap circuit 202, and the voltage VBs at two ends of the first capacitor C1 is the voltage between VB1, 2 and 3 and VS1, 2 and 3 shown in fig. 6, so as to provide a driving power supply for the outputs of the high sides HO1, 2 and 3, and be used for switching the power transistor Q1. When LIN1,2,3 is high level, low side LO1,2,3 output is high level, low side power tube Q2 switches on, simultaneously MOS tube Q3 switches on, and low side power VCC charges to first electric capacity C1 through MOS tube Q3 this moment, and VCC, Q3, Q2 constitute the charging loop, and the charging loop is as shown by the broken line arrow in fig. 11. When the outputs of the low sides LO1,2 and 3 are low level, the low side power transistor Q2 is turned off, the MOS transistor Q3 is turned off, the charging loop is turned off, and VCC stops charging the first capacitor C1.

In this embodiment, the over-current protection circuit 7 includes a second comparator 0606, a fifth resistor 0601, a sixth resistor 0602, a seventh resistor 0603 and a fourth MOS transistor 0605; the positive input end of the second comparator 0606 is used for connecting a current detection signal, the negative input end of the second comparator 0606 is connected between the first end of the fifth resistor 0601 and the first end of the sixth resistor 0602, and the output end of the second comparator 0606 is connected with the fault logic control circuit 16; a second end of the fifth resistor 0601 is connected with a reference voltage, a second end of the sixth resistor 0602 is connected with a first end of the seventh resistor 0603, and a second end of the seventh resistor 0603 is grounded; the source electrode of the fourth MOS transistor 0605 is connected to the second end of the seventh resistor 0603, the drain electrode of the fourth MOS transistor 0605 is connected to the first end of the seventh resistor 0603, and the gate electrode of the fourth MOS transistor 0605 is connected to the fault logic control circuit 16.

Specifically, the overcurrent protection circuit is composed of a second comparator 0606 (CMP), a fourth MOS tube, a voltage dividing resistor, a reference voltage and a logic circuit, the current detection signal itip is input to the positive input end of the second comparator 0606, VREF is divided by the voltage dividing resistor (a fifth resistor 0601, a sixth resistor 0602 and a seventh resistor 0603), and then the reference voltage signal of the voltage dividing point a is obtained and input to the negative input end of the comparator; the end D of the MOS tube is connected with the connection ends of the divider resistor sixth resistor 0602 and the seventh resistor 0603, and the end S is connected with one end of the divider resistor seventh resistor 0603 to be grounded. The output end of the second comparator 0606 is connected to the logic circuit, and is fed back to the upper bridge and lower bridge driving circuits, and when the current detection signal ITRIP is higher than the reference voltage, the logic circuit can turn off the upper bridge and the lower bridge at the same time. The feedback end of the logic circuit is connected with the grid electrode G of the MOS tube to control the switch of the MOS tube. When the voltage higher than the reference voltage is not available, the MOS tube is turned off, and when the voltage higher than the reference voltage is available, the fourth MOS tube is turned on. Forming a hysteresis effect. The overcurrent protection circuit realizes an overcurrent protection function.

In this embodiment, the temperature protection circuit 42 includes a third comparator 0706, an eighth resistor 0701, a ninth resistor 0702, a tenth resistor 0703, and a fifth MOS transistor 0705; the positive input end of the third comparator 0706 is used for being connected with a current detection signal, the negative input end of the third comparator 0706 is connected between the first end of the eighth resistor 0701 and the first end of the ninth resistor 0702, and the output end of the third comparator 0706 is connected with the fault logic control circuit 16; the second end of the eighth resistor 0701 is connected with a reference voltage, the second end of the ninth resistor 0702 is connected with the first end of the tenth resistor 0703, and the second end of the tenth resistor 0703 is grounded; the source electrode of the fifth MOS 0705 is connected to the second end of the tenth resistor 0703, the drain electrode of the fifth MOS 0705 is connected to the first end of the tenth resistor 0703, and the gate electrode of the fifth MOS 0705 is connected to the fault logic control circuit 16.

In this embodiment, the high voltage integrated circuit 100 further includes a temperature sampling circuit 33, where the temperature sampling circuit 33 includes an eleventh resistor 0901 and an adjustable resistor 35, a first end of the eleventh resistor 0901 is connected to the power supply voltage VCC, a second end of the eleventh resistor 0901 is connected to the first end of the adjustable resistor 35, and a second end of the adjustable resistor 35 is grounded.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any such modifications, equivalents, and improvements that fall within the spirit and principles of the present invention are intended to be covered by the following claims.

Claims

1. A high voltage integrated circuit, comprising: the power supply circuit, the high-side driving circuit of the 3 channels, the low-side driving circuit of the 3 channels and the PFC controller driving circuit of the 1 channels; the high-side driving circuit is electrically connected with the low-side driving circuit and the power supply circuit respectively, and the PFC controller driving circuit is electrically connected with the low-side driving circuit;

2. The high voltage integrated circuit of claim 1, further comprising an interlock and dead zone circuit connected between the high side drive circuit and the low side drive circuit.

3. The high voltage integrated circuit of claim 2, further comprising an enable circuit, an over-current protection circuit, and an under-voltage power supply protection circuit, wherein the enable circuit and the over-current protection circuit are respectively connected with the high-side driving circuit, and wherein the under-voltage power supply protection circuit is connected with the power supply circuit.

4. The high voltage integrated circuit of claim 3, wherein the interlock and dead zone circuit comprises a third MOS transistor, a source of the third MOS transistor is connected to a bias voltage, a drain of the third MOS transistor is connected to a supply voltage, and a gate of the third MOS transistor is connected to an input-output circuit.

5. The high voltage integrated circuit of claim 4, further comprising a VREG generation circuit, an RC filter circuit, a schmitt trigger circuit, a low pass filter, a level shifter circuit, a three and gate, a pulse driver circuit, a delay circuit, a fault logic control circuit, a fault output circuit, and a high voltage region detection circuit; the VREG generation circuit is connected with the undervoltage power protection circuit, the undervoltage power protection circuit is connected with the fault logic control circuit, the RC filter circuit is sequentially connected with the level conversion circuit and the fault logic control circuit, the fault logic control circuit is respectively connected with the PFC current protection circuit, the temperature protection circuit and the input ends connected with the three AND gates, the output ends of the three AND gates are connected with the first end of the pulse driving circuit, and the second end of the pulse driving circuit is connected with the fault output circuit.

6. The high voltage integrated circuit of claim 5, wherein the bootstrap circuit comprises a first capacitor, a high side power transistor Q1, a low side power transistor Q2, a MOS transistor Q3, a high side drive switch for connecting a high side drive signal, and a low side drive switch for connecting a low side drive signal; the first end of the high-side driving switch is respectively connected with the source electrode of the MOS tube Q3 and the first end of the first capacitor, and the second end of the high-side driving switch is connected with the base electrode of the high-side power tube Q1; the third end of the high-side driving switch is respectively connected with the second end of the first capacitor and the emitter of the high-side power tube Q1, and the collector of the high-side power tube Q1 is connected with a power supply voltage; the drain electrode of the MOS tube Q3 is connected with the power supply voltage, the grid electrode of the MOS tube Q3 is connected with the input end of the low-side driving switch, the output end of the low-side driving switch is connected with the base electrode of the low-side power tube Q2, the emitter electrode of the low-side power tube Q2 is connected with the first resistor and grounded, and the collector electrode of the low-side power tube Q2 is connected with the emitter electrode of the high-side power tube Q1.

7. The high voltage integrated circuit of claim 5, wherein the over-current protection circuit comprises a second comparator, a fifth resistor, a sixth resistor, a seventh resistor, and a fourth MOS transistor; the positive input end of the second comparator is used for being connected with a current detection signal, the negative input end of the second comparator is connected between the first end of the fifth resistor and the first end of the sixth resistor, and the output end of the second comparator is connected with the fault logic control circuit; the second end of the fifth resistor is connected with a reference voltage, the second end of the sixth resistor is connected with the first end of the seventh resistor, and the second end of the seventh resistor is grounded;

8. The high voltage integrated circuit of claim 5, wherein the temperature protection circuit comprises a third comparator, an eighth resistor, a ninth resistor, a tenth resistor, and a fifth MOS transistor; the positive input end of the third comparator is used for being connected with a current detection signal, the negative input end of the third comparator is connected between the first end of the eighth resistor and the first end of the ninth resistor, and the output end of the third comparator is connected with the fault logic control circuit; the second end of the eighth resistor is connected with a reference voltage, the second end of the ninth resistor is connected with the first end of the tenth resistor, and the second end of the tenth resistor is grounded;

9. The high voltage integrated circuit of claim 1, wherein the counting circuit comprises a first JK flip-flop, a second JK flip-flop, and an and gate, the first JK flip-flop being connected to the second JK flip-flop, the and gate further connecting the first JK flip-flop and the second JK flip-flop, respectively.

10. The high voltage integrated circuit of claim 5, further comprising a temperature sampling circuit, the temperature sampling circuit comprising an eleventh resistor and an adjustable resistor, a first terminal of the eleventh resistor connected to the supply voltage, a second terminal of the eleventh resistor connected to the first terminal of the adjustable resistor, a second terminal of the adjustable resistor connected to ground.