CN116404854A

CN116404854A - High-voltage integrated circuit

Info

Publication number: CN116404854A
Application number: CN202310521267.4A
Authority: CN
Inventors: 冯宇翔; 谢荣才; 华庆
Original assignee: Guangdong Huixin Semiconductor Co Ltd
Current assignee: Guangdong Huixin Semiconductor Co Ltd
Priority date: 2023-05-09
Filing date: 2023-05-09
Publication date: 2023-07-07

Abstract

The invention relates to the technical field of intelligent power modules, and provides a high-voltage integrated circuit, which comprises: a power supply circuit, a 6-channel high-side driving circuit, a 6-channel low-side driving circuit, a 1-channel PFC driving circuit, a dead zone circuit and a frequency division circuit; the high-side driving circuit is respectively and electrically connected with the low-side driving circuit and the power supply circuit, the first end of the dead zone circuit is respectively connected with the high-side driving circuit and the low-side driving circuit, the second end of the dead zone circuit is connected with the first end of the frequency dividing circuit, and the second end of the frequency dividing circuit is used for respectively dividing 6 paths of PWM waves into complementary high-side and low-side driving PWM waves; the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit; the PFC driving circuit comprises a driving current protection circuit, an overcurrent protection circuit, an overtemperature protection circuit, an error reporting circuit, an undervoltage protection circuit and an enabling circuit which are respectively connected with the high-side driving circuit. The high-voltage integrated circuit is convenient for reducing the electric control cost and has strong market competitiveness.

Description

High-voltage integrated circuit

Technical Field

The invention relates to the technical field of intelligent power modules, in particular to a high-voltage integrated circuit.

Background

The high voltage integrated circuit, HVIC (High Voltage Integrated Circuit), is an integrated circuit product that converts MCU signals to drive IGBT signals. The HVIC integrates the PMOS tube, the NMOS tube, the triode, the diode, the voltage stabilizing tube, the resistor and the capacitor to form circuits such as a Schmitt, a low voltage LEVELSHIFT, a high voltage LEVELSHIFT, a pulse driving circuit, a dead zone circuit, an interlocking circuit, a delay circuit, a filter circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage protection circuit and the like. On one hand, the HVIC receives the control signal of the MCU to drive the subsequent IGBT or MOS to work, and on the other hand, the HVIC sends the state detection signal of the system back to the MCU. Is a critical chip inside the IPM.

Along with the rapid development of industry, the IPM intelligent power module is widely applied to various fields, particularly in the field of white household appliances, along with the miniaturization, high reliability, safety and miniaturization trend of the volume design of a variable-frequency electric control main board of household products, the driving IC inside the traditional IPM intelligent power module has basic functions and is difficult to adapt to development requirements.

Brushless direct current (BLDC) motors (or "motors") having characteristics of significant energy saving, low noise, and excellent speed change performance in white goods designs are increasingly used today. It has been counted that 5 or more motors may be used in a high-grade refrigerator, 2 for each of an outdoor unit and an indoor unit of an air conditioner, and 2 for a washing machine/dryer, a dish washer, etc., which requires an energy-efficient motor driving/controlling scheme. The current market lacks a multi-channel drive HVIC capable of simultaneously driving two or more motors, and the current six-channel and seven-channel HVICs are difficult to meet the high-speed development demands of the market.

Therefore, the existing high-voltage integrated circuit simultaneously needs more PFC and electric control board drive ICs of a double-motor functional system, the circuit layout and wiring are intricate and complex, the area of the electric control board is too large, the manufacturing cost of the electric control system is high, and the reliability is poor.

Disclosure of Invention

Aiming at the defects of the related technology, the invention provides a high-voltage integrated circuit which has the advantages of high integration HVIC, simplified application electric control design and electric control miniaturization, reduced electric control cost and strong product market competitiveness.

In order to solve the above technical problems, an embodiment of the present invention provides a high voltage integrated circuit, including: a power supply circuit connected with the power supply voltage, a high-side driving circuit of 6 channels, a low-side driving circuit of 6 channels, a PFC driving circuit of 1 channel, a dead zone circuit and a frequency division circuit; the high-side driving circuit is respectively and electrically connected with the low-side driving circuit and the power supply circuit, a first end of the dead zone circuit is respectively connected with the high-side driving circuit and the low-side driving circuit, a second end of the dead zone circuit is connected with a first end of the frequency dividing circuit, and a second end of the frequency dividing circuit is used for respectively dividing 6 paths of PWM waves into complementary high-side and low-side driving PWM waves;

the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit;

the PFC driving circuit comprises a driving current protection circuit, an overcurrent protection circuit, an over-temperature protection circuit, an error reporting circuit, an under-voltage protection circuit and an enabling circuit which are respectively connected with the high-side driving circuit, wherein the error reporting circuit is also connected to the low-side driving circuit, and the under-voltage protection circuit is connected with the power supply circuit.

Preferably, the frequency dividing circuit includes an inverter, an input end of the inverter is connected to a PWMIN1 port, a first output end of the inverter is connected to a PWMOUT1 port, and a second output end of the inverter is connected to a PWMOUT2 port; the PWM wave input by the PWMIN1 port is consistent with the timing chart of the PWM wave output by the PWMOUT1 port, and the PWM wave input by the PWMIN1 port is opposite to the timing chart of the PWM wave output by the PWMOUT2 port.

Preferably, the dead zone circuit comprises a first resistor, a first capacitor and a first diode, wherein the first resistor is connected with the first diode in parallel, a first end of the first capacitor is respectively connected with an anode of the first diode and a first output end of the NOT gate, a second end of the first capacitor is grounded, and a cathode of the first diode is connected with an input end of the NOT gate.

Preferably, the high-voltage integrated circuit further comprises a VREG generation circuit, an RC filter circuit, a Schmidt trigger circuit, a low-pass filter, a level conversion circuit, a pulse driving circuit, a delay circuit, a fault logic control circuit, a three-AND gate, a fault output circuit and a high-voltage region detection circuit; the VREG generation circuit is connected with the first end of the under-voltage protection circuit, the second end of the under-voltage protection circuit is connected with the fault logic control circuit, the Schmidt trigger circuit is sequentially connected with the RC filter circuit, the level conversion circuit and the fault logic control circuit, the fault logic control circuit is respectively connected with the driving current protection circuit, the over-temperature protection circuit and the dead zone circuit, the output ends of the three AND gates are connected with the first end of the pulse driving circuit, the input ends of the three AND gates are respectively connected with the over-current protection circuit and the fault logic control circuit, and the second end of the pulse driving circuit is connected with the fault output circuit.

Preferably, the bootstrap circuit includes a first MOS transistor, a source electrode of the first MOS transistor is connected to the VB port of the high-side driving circuit, a drain electrode of the first MOS transistor is connected to the supply voltage, and a gate electrode of the first MOS transistor is connected to the LO port of the low-side driving circuit.

Preferably, the bootstrap circuit further includes a second capacitor, a high-side power tube Q1, a low-side power tube Q2, a MOS tube Q3, a high-side driving switch for connecting a high-side driving signal, and a low-side driving switch for connecting a low-side driving signal; the first end of the high-side driving switch is respectively connected with the source electrode of the MOS tube Q3 and the first end of the second capacitor, and the second end of the high-side driving switch is connected with the base electrode of the high-side power tube Q1; the third end of the high-side driving switch is respectively connected with the second end of the second capacitor and the emitter of the high-side power tube Q1, and the collector of the high-side power tube Q1 is connected with a power supply voltage; the drain electrode of the MOS tube Q3 is connected with the power supply voltage, the grid electrode of the MOS tube Q3 is connected with the input end of the low-side driving switch, the output end of the low-side driving switch is connected with the base electrode of the low-side power tube Q2, the emitter electrode of the low-side power tube Q2 is connected with the second resistor and grounded, and the collector electrode of the low-side power tube Q2 is connected with the emitter electrode of the high-side power tube Q1.

Preferably, the overcurrent protection circuit comprises a first comparator, a third resistor, a fourth resistor, a fifth resistor and a second MOS tube; the positive input end of the first comparator is used for being connected with a current detection signal, the negative input end of the first comparator is connected between the first end of the third resistor and the first end of the fourth resistor, and the output end of the first comparator is connected with the fault logic control circuit; the second end of the third resistor is connected with a reference voltage, the second end of the fourth resistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is grounded;

the source electrode of the second MOS tube is connected with the second end of the fifth resistor, the drain electrode of the second MOS tube is connected with the first end of the fifth resistor, and the grid electrode of the second MOS tube is connected with the fault logic control circuit.

Preferably, the over-temperature protection circuit comprises a second comparator, a sixth resistor, a seventh resistor, an eighth resistor and a third MOS tube; the positive input end of the second comparator is used for being connected with a current detection signal, the negative input end of the second comparator is connected between the first end of the sixth resistor and the first end of the seventh resistor, and the output end of the second comparator is connected with the fault logic control circuit; the second end of the sixth resistor is connected with a reference voltage, the second end of the seventh resistor is connected with the first end of the eighth resistor, and the second end of the eighth resistor is grounded;

the source electrode of the third MOS tube is connected with the second end of the eighth resistor, the drain electrode of the third MOS tube is connected with the first end of the eighth resistor, and the grid electrode of the third MOS tube is connected with the fault logic control circuit.

Compared with the related art, the invention has the advantages that the power supply circuit is connected with the power supply voltage, and is respectively connected with the 6-channel high-side driving circuit, the 6-channel low-side driving circuit and the 1-channel PFC driving circuit; the high-side driving circuit is respectively and electrically connected with the low-side driving circuit and the power supply circuit, a first end of the dead zone circuit is respectively connected with the high-side driving circuit and the low-side driving circuit, a second end of the dead zone circuit is connected with a first end of the frequency dividing circuit, and a second end of the frequency dividing circuit is used for respectively dividing 6 paths of PWM waves into complementary high-side and low-side driving PWM waves; the high-side driving circuit comprises a high-side undervoltage protection circuit and a bootstrap circuit; the PFC driving circuit comprises a driving current protection circuit, an overcurrent protection circuit, an over-temperature protection circuit, an error reporting circuit, an under-voltage protection circuit and an enabling circuit which are respectively connected with the high-side driving circuit, wherein the error reporting circuit is also connected to the low-side driving circuit, and the under-voltage protection circuit is connected with the power supply circuit. Therefore, the 7-in 13-out multi-channel HVIC can drive one totem pole PFC and drive two paths of direct current variable frequency motors simultaneously, and the problems that PFC and an electric control board drive IC of a dual-motor functional system are needed simultaneously, circuit layout and wiring are complicated, the area of the electric control board is too large, and the cost of a fast general electric control system is high are solved. The high integration HVIC simplifies the application of the electric control design, leads the electric control to be more miniaturized, reduces the electric control cost and the production cost and leads the product to have more market competitiveness.

Drawings

The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the accompanying drawings:

FIG. 1 is a block diagram of a high voltage integrated circuit of the present invention;

FIG. 2 is a circuit diagram of a high voltage integrated circuit according to the present invention;

FIG. 3 is a first partial enlarged view of FIG. 2;

FIG. 4 is a second enlarged partial view of FIG. 2;

FIG. 5 is a third partial enlarged view of FIG. 2;

FIG. 6 is a circuit diagram of a divider circuit according to the present invention;

FIG. 7 is a timing diagram of the input PWM wave and the output PWM wave of the frequency divider circuit according to the present invention;

fig. 8 is a circuit diagram of a dead zone circuit of the present invention;

FIG. 9 is a circuit diagram of a bootstrap circuit of the present invention;

FIG. 10 is a schematic circuit diagram of a bootstrap circuit of the present invention;

FIG. 11 is a circuit diagram of an over-current protection circuit of the present invention;

FIG. 12 is a circuit diagram of an over-temperature protection circuit according to the present invention;

fig. 13 is a schematic diagram of a dead time test standard of the dead time circuit of the present invention.

In the figure, 100, a high-voltage integrated circuit, 1, a power supply circuit, 2, a high-side driving circuit, 201, a high-side undervoltage protection circuit, 202, a bootstrap circuit, 3, a low-side driving circuit, 4, a PFC driving circuit, 5, a dead zone circuit, 6, a frequency dividing circuit, 7, a driving current protection circuit, 8, an overcurrent protection circuit, 9, an overtemperature protection circuit, 10, a fault reporting circuit, 11, an undervoltage protection circuit, 12, an enabling circuit, 13, a VREG generating circuit, 14, an RC filter circuit, 15, a schmitt trigger circuit, 16, a low-pass filter, 17, a level conversion circuit, 18, a pulse driving circuit, 19, a delay circuit, 20, a fault logic control circuit, 21, a fault output circuit, 22, a high-voltage region detection circuit, 23, a first MOS transistor, 24, a high-side driving switch, 25, a low-side driving switch, 26, a second resistor, 27, a first comparator, 28, a third resistor, 29, a fourth resistor, 30, a fifth resistor, 31, a second comparator, 32, a sixth resistor, 33, a seventh resistor, and an eighth resistor.

Detailed Description

The following describes in detail the embodiments of the present invention with reference to the drawings.

The detailed description/examples set forth herein are specific embodiments of the invention and are intended to be illustrative and exemplary of the concepts of the invention and are not to be construed as limiting the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to adopt other obvious solutions based on the disclosure of the claims and specification of the present application, including those adopting any obvious substitutions and modifications to the embodiments described herein, all within the scope of the present invention.

Example 1

As shown in fig. 1-13, the present invention provides a high voltage integrated circuit 100 comprising: a high-side drive circuit 2 of a power supply circuit 1 and a power supply circuit 6 of a power supply voltage VCC, a low-side drive circuit 3 of a power supply circuit 6, a PFC drive circuit 4 of a power supply circuit 1, a dead zone circuit 5 and a frequency dividing circuit 6; the high-side driving circuit 2 is electrically connected with the low-side driving circuit 3 and the power supply circuit 1 respectively, a first end of the dead zone circuit 5 is connected with the high-side driving circuit 2 and the low-side driving circuit 3 respectively, a second end of the dead zone circuit 5 is connected with a first end of the frequency dividing circuit 6, and a second end of the frequency dividing circuit 6 is used for dividing 6 paths of PWM waves into complementary high-side and low-side driving PWM waves respectively. The power supply circuit 1 is configured to control a voltage to which a power supply voltage is input so that a stable power supply is output to the high-side drive circuit 2 and the low-side drive circuit 3, and safety is high. The dead zone circuit 5 connected between the high-side driving circuit 2 and the corresponding low-side driving circuit 3 is used to realize the dead zone function.

The high-side driving circuit 2 includes a high-side under-voltage protection circuit 201 and a bootstrap circuit 202.

The PFC driving circuit 4 comprises a driving current protection circuit 7, an overcurrent protection circuit 8, an overtemperature protection circuit 9, an error reporting circuit 10, an undervoltage protection circuit 11 and an enabling circuit 12 which are respectively connected with the high-side driving circuit 2, wherein the error reporting circuit 10 is also connected to the low-side driving circuit 3, and the undervoltage protection circuit 11 is connected with the power supply circuit 1.

Specifically, the power supply circuit 1 includes a 5V LDO circuit and a 1.2V BANDGAP circuit, supplies 5V voltage to all circuits inside the HVIC and to external circuits, and supplies a stable 1.2V voltage reference to the HVIC and to external circuits; the power supply circuit 1 is connected with the undervoltage protection circuit 11 to realize the undervoltage protection function.

The drive current protection circuit 7 includes an ITRIP1 protection circuit and an ITRIP2 protection circuit. The ITRIP1 protection circuit and the ITRIP2 protection circuit realize the circuit protection function of a current protection circuit driven by a two-path three-phase direct-current variable-frequency motor. PFCTRIP is a PFC driving current protection circuit 7 for realizing the current protection function of PFC; the HVIC also comprises an enabling circuit 12 inside to realize the enabling function; the overvoltage protection circuit realizes an overvoltage protection function; the fault reporting circuit 10 outputs a fault reporting signal to the outside when conditions such as under-voltage, over-current, PFC fault, overvoltage and the like occur in the circuit.

Specifically, by connecting the power supply circuit 1 to the power supply voltage, the power supply circuit 1 is connected to the 6-channel high-side driving circuit 2, the 6-channel low-side driving circuit 3, and the 1-channel PFC driving circuit 4, respectively; the high-side driving circuit 2 is electrically connected with the low-side driving circuit 3 and the power supply circuit 1 respectively, a first end of the dead zone circuit 5 is connected with the high-side driving circuit 2 and the low-side driving circuit 3 respectively, a second end of the dead zone circuit 5 is connected with a first end of the frequency dividing circuit 6, and a second end of the frequency dividing circuit 6 is used for dividing 6 paths of PWM waves into complementary high-side driving PWM waves and low-side driving PWM waves respectively; the high-side driving circuit 2 comprises a high-side undervoltage protection circuit 201 and a bootstrap circuit 202; the PFC driving circuit 4 comprises a driving current protection circuit 7, an overcurrent protection circuit 8, an overtemperature protection circuit 9, an error reporting circuit 10, an undervoltage protection circuit 11 and an enabling circuit 12 which are respectively connected with the high-side driving circuit 2, wherein the error reporting circuit 10 is also connected to the low-side driving circuit 3, and the undervoltage protection circuit 11 is connected with the power supply circuit 1. Therefore, the 7-in 13-out multi-channel HVIC can drive one totem pole PFC and drive two paths of direct current variable frequency motors simultaneously, and the problems that PFC and an electric control board drive IC of a dual-motor functional system are needed simultaneously, circuit layout and wiring are complicated, the area of the electric control board is too large, and the cost of a fast general electric control system is high are solved. The high integration HVIC simplifies the application of the electric control design, leads the electric control to be more miniaturized, reduces the electric control cost and the production cost and leads the product to have more market competitiveness.

In this embodiment, the frequency dividing circuit 6 includes an inverter, an input end of the inverter is connected to the PWMIN1 port, a first output end of the inverter is connected to the PWMOUT1 port, and a second output end of the inverter is connected to the PWMOUT2 port; the PWM wave input by the PWMIN1 port is consistent with the timing chart of the PWM wave output by the PWMOUT1 port, and the PWM wave input by the PWMIN1 port is opposite to the timing chart of the PWM wave output by the PWMOUT2 port. The frequency dividing circuit 6 is generally composed of NOT gates, one path of PWM wave is decomposed into two paths of complementary PWM waves, an upper switching tube (IGBT) and a lower switching tube (IGBT) of a group of H bridges are driven, one path of totem pole PFC and two paths of direct current variable frequency motors can be driven simultaneously, and 7-in and 13-out multi-channel HVIC are driven.

In this embodiment, the dead zone circuit 5 includes a first resistor R1, a first capacitor C1, and a first diode D1, where the first resistor R1 is connected in parallel with the first diode D1, a first end of the first capacitor C1 is connected to an anode of the first diode D1 and a first output end of the not gate, a second end of the first capacitor C1 is grounded, and a cathode of the first diode D1 is connected to an input end of the not gate.

Specifically, the dead zone circuit 5 is mainly used for generating dead zone time, and is used for avoiding false triggering when the power switch control signal is turned over. The HVIC controls the three-phase inverter power device, and the feedback current or voltage signal is often affected by noise generated when the power device is switched, so that the signal input into the chip is superimposed with peak noise caused by the parasitic inductance of the conductive wire and the parasitic capacitance of the chip, and the peak noise can cause false triggering in the chip and output a wrong control signal. In order to avoid the influence of peak noise, the operation circuit of the feedback signal is shielded in a period from the time when the control signal is turned over to the time when the feedback signal is stable, and the period is dead time. Jian Shandian the turn-on and turn-off of the upper and lower switching devices (such as IGBTs and MOS transistors) of the same bridge arm are staggered for a certain time, namely dead time, so as to ensure that the upper and lower IGBTs of the same bridge arm are always turned off and then turned on.

By using resistors, capacitors and diodes to form the RC charge delay circuit 19, the charge speed is slow and the discharge speed is fast. The rising edge of the pulse is slowed down and the falling edge is unchanged. This is the principle of dead zone generation, which can be modified by adjusting the values of R, C. Dead time DT test criteria. Where ton is the output rising edge propagation delay, toff is the output falling propagation delay, tr is the output rising time, and tf is the output falling time.

In this embodiment, the high voltage integrated circuit 100 further includes a VREG generating circuit 13, an RC filter circuit 14, a schmitt trigger circuit 15, a low-pass filter 16, a level shifter circuit 17, a pulse driver circuit 18, a delay circuit 19, a fault logic control circuit 20, a three-and gate, a fault output circuit 21, and a high voltage region detection circuit 22; the VREG generation circuit 13 is connected with a first end of the under-voltage protection circuit 11, a second end of the under-voltage protection circuit 11 is connected with the fault logic control circuit 20, the Schmitt trigger circuit 15 is sequentially connected with the RC filter circuit 14, the level conversion circuit 17 and the fault logic control circuit 20, the fault logic control circuit 20 is respectively connected with the driving current protection circuit 7, the over-temperature protection circuit 9 and the dead zone circuit 5, an output end of the three AND gates is connected with a first end of the pulse driving circuit 18, an input end of the three AND gates is respectively connected with the over-current protection circuit 8 and the fault logic control circuit 20, and a second end of the pulse driving circuit 18 is connected with the fault output circuit 21.

Specifically, the VREG generating circuit 13 is configured to generate a VREG of 7V to 8V in order to receive a logic 1 signal of 5V such as MCU, for example, with a supply voltage TYPE of 15V. A VREG signal of 7.2V with good temperature characteristic is generated, and meanwhile, a 5V power supply is also needed to supply power to an MCU processor integrating a sine wave algorithm.

RC filter circuit 14, known as Resistor-capacitor circuit (Resistor-Capacitance circuit), is a passive interference-free filter circuit consisting of a Resistor and a capacitor. For removing unnecessary high frequency components from the input signal and removing high frequency interference.

SCHMITT trigger (SCHMITT), the level noise of the input circuit is filtered by passing both PWM IN, ITRIP, TVC, EN through the SCHMITT trigger first, with a logic 0 maximum of 0.8V and a logic 1 minimum of 2.9V.

The low-pass filter 16 (TWIN FILTER) is used for filtering high-frequency noise of the input circuit, and for providing sufficient charging time for VB, so that the driven back-end circuit is prevented from operating in a state of insufficient VB voltage (which reduces the efficiency of the back-end circuit), and the frequency range of the input signal needs to be limited, and the signal with the excessive frequency needs to be filtered. Signals generally above 600 KHz-700 KHz should be filtered out.

The VREG-VCC level conversion circuit 17 is a MOS circuit, and has a small current, but the VREG has a limited current capability, and cannot drive an excessive circuit, and after schmitt trigger and low-pass filtering, voltage conversion is generally performed first, and the driving voltage is converted from VREG to VCC.

The pulse driving circuit 18 is configured to generate pulses at the rising edge and the falling edge of the HIN signal respectively, so that the high voltage DMOS transistor of the high voltage region detecting circuit 22 is instantaneously turned on, and the RS flip-flop is used to record the instantaneously turned-on signal, so as to control HO to synchronize with HIN. The continuous high-low signal of HIN cannot be used to control the turn-on of DMOS because when VS is 600V-650V, VB is 615V-675V, VB is a voltage formed by a voltage pump, has limited energy, and generally does not have the capability of continuously flowing through the turned-on DMOS to ground; if a continuous current loop is generated between VB and ground, VB will be quickly reduced and enter a low-voltage protection area, so that the driving IC cannot work normally. Thus, the introduction of PLUSEGEN circuits is necessary, and more PLUSEGEN signals are used in the driver IC, including ONESHOT circuits (generating one pulse) and DOUBLELPLUSE circuits (generating two pulses). In the general use occasion, an ONESHOT circuit is enough; for circuits where VS will be pulled lower (typically with a large inductance in the subsequent circuit), a doubleple circuit will be used.

Delay circuit 19 is used to delay the LO signal output so that the HO output signal is consistent with the LO output signal.

The undervoltage protection circuit 11 is used to stop the driving IC (keep the output in logic 0 state) when the voltage is too low, so as to protect the subsequent circuit. Therefore, in the low voltage region, there should be a low voltage protection circuit for detecting the VCC level. VCC starts to fall from high potential, after being lower than 13V, the output keeps logic 0; when VCC rises from the low point, above 13.7V, a hold logic 1 is output. I.e. there is a difference of 0.7V between them. To better protect the subsequent circuitry, the output is not high until the supply voltage is indeed high enough. In view of the power supply noise, a delay circuit 19 should be added at the end of the circuit so that the output does not malfunction when the power supply voltage due to the power supply noise is instantaneously lowered.

In which the driver IC should be deactivated (keep the output in a logic 0 state) when the voltage is too low to protect the subsequent circuits. Therefore, in the low voltage region, there should be a low voltage protection circuit for detecting the VCC level.

When VCC starts to fall from high potential and is lower than 13V, the output keeps logic 0; when VCC rises from the low point, above 13.7V, a hold logic 1 is output. I.e. there is a difference of 0.7V between them.

This is mainly to better protect the subsequent circuits, and the output will not go high until the supply voltage is indeed high enough. In consideration of power supply noise, a delay circuit is added at the end of the circuit, so that when the power supply voltage caused by the power supply noise is instantaneously lowered, misoperation does not occur in output.

The fault logic control circuit 20 receives fault signals of each functional circuit, makes fault processing according to each fault signal, and turns off corresponding functions or turns off all functions of the HVIC according to importance of the fault, thereby protecting the HVIC and the whole application circuit. When the undervoltage protection function signal UVLO is 0, the fault logic control circuit 20 outputs a fault signal to the fault output circuit 21, meanwhile, the HVIC enters the undervoltage protection function, six paths of PWM waves of the HVIC are turned off, each function fault signal 1 of the undervoltage protection function, the ITRIP, PFCTRIP current protection function and the temperature protection function is normal and has no fault, when the undervoltage protection function signal UVLO is 0, the fault logic control circuit 20 outputs a fault signal to the fault output circuit 21, meanwhile, the HVIC also enters the corresponding function protection, and the HVIC stops 12 paths of PWM wave output and stops working.

The fault output circuit 21 is a MOS tube, the base electrode of the MOS tube is connected to the output end of the fault logic control circuit 20, the fault logic control circuit 20 controls the on-off of the fault output MOS, the D of the MOS tube is suspended, a pull-up resistor is required to be externally added to the HVIC, and when the fault logic control circuit 20 outputs 1, the MOS tube is turned on to output an FO signal to external equipment. When the fault logic control circuit 20 outputs 0 (HVIC has no fault), the MOS is turned off and the FO signal is high.

Optionally, the high-voltage region detection circuit 22 is a plurality of MOS transistors, and the MOS transistors are 605V series MOS transistors, which include UQ1, UQ2, VQ1, VQ2, WQ1, and WQ2. The circuit is used for realizing the transition between a low voltage area and a high voltage area, and has the PULSE of a CMOS conduction PULSE generation circuit (PULSE GEN) to control the on of a high-voltage DMOS, and when the DMOS is turned off, the voltage between the drain electrode and the source electrode of the DMOS can bear more than 650V. In order to realize the separation between a high voltage area and a low voltage area, a high voltage island structure is needed to realize the isolation between the high voltage area and the low voltage area.

In this embodiment, the bootstrap circuit 202 includes a first MOS transistor 23, a source electrode of the first MOS transistor 23 is connected to the VB port of the high-side driving circuit 2, a drain electrode of the first MOS transistor 23 is connected to the supply voltage, and a gate electrode of the first MOS transistor 23 is connected to the LO port of the low-side driving circuit 3.

Specifically, the D pole of the first MOS transistor 23 is connected to VCC, the S pole of the first MOS transistor 23 is connected to the VB port, and the g pole of the first MOS transistor 23 is connected to the lower bridge driving signal LO port.

In this embodiment, the bootstrap circuit 202 further includes a second capacitor C2, a high-side power transistor Q1, a low-side power transistor Q2, a MOS transistor Q3, a high-side driving switch 24 for connecting a high-side driving signal, and a low-side driving switch 25 for connecting a low-side driving signal; a first end of the high-side driving switch 24 is connected to the source of the MOS transistor Q3 and the first end of the second capacitor C2, and a second end of the high-side driving switch 24 is connected to the base of the high-side power transistor Q1; a third end of the high-side driving switch 24 is respectively connected with a second end of the second capacitor C2 and an emitter of the high-side power tube Q1, and a collector of the high-side power tube Q1 is connected with a power supply voltage; the drain electrode of the MOS tube Q3 is connected with the power supply voltage, the grid electrode of the MOS tube Q3 is connected with the input end of the low-side driving switch 25, the output end of the low-side driving switch 25 is connected with the base electrode of the low-side power tube Q2, the emitter electrode of the low-side power tube Q2 is connected with the second resistor 26 and grounded, and the collector electrode of the low-side power tube Q2 is connected with the emitter electrode of the high-side power tube Q1.

Specifically, a capacitor needs to be added between VB and VS by using the bootstrap circuit 202 formed by the MOS transistors, so that the MOS transistor Q3 and the second capacitor C2 form the complete bootstrap circuit 202, and the voltage VBs at two ends of the second capacitor C2 is the voltage between VB1, 2 and 3 and VS1, 2 and 3 shown in fig. 10, so as to provide a driving power supply for the output of the high side HO1, 2 and 3, and be used for switching the power transistor Q1. When LIN1,2,3 is high level, low side LO1,2,3 output is high level, low side power tube Q2 switches on, simultaneously, MOS tube Q3 switches on, and low side power VCC charges to second electric capacity C2 through MOS tube Q3 this moment, VCC, Q3, Q2 constitute the charge loop, when low side LO1,2,3 output is low level, low side power tube Q2 switches off, MOS tube Q3 opens, the charge loop opens, VCC stops charging for second electric capacity C2.

In this embodiment, the over-current protection circuit 8 includes a first comparator 27, a third resistor 28, a fourth resistor 29, a fifth resistor 30, and a second MOS transistor 31; the positive input end of the first comparator 27 is used for being connected with a current detection signal, the negative input end of the first comparator 27 is connected between the first end of the third resistor 28 and the first end of the fourth resistor 29, and the output end of the first comparator 27 is connected with the fault logic control circuit 20; a second end of the third resistor 28 is connected to a reference voltage, a second end of the fourth resistor 29 is connected to a first end of the fifth resistor 30, and a second end of the fifth resistor 30 is grounded; the source electrode of the second MOS transistor 31 is connected to the second end of the fifth resistor 30, the drain electrode of the second MOS transistor 31 is connected to the first end of the fifth resistor 30, and the gate electrode of the second MOS transistor 31 is connected to the fault logic control circuit 20.

Specifically, the overcurrent protection circuit 8 is composed of a first comparator 27 (CMP), a second MOS tube 31, a voltage dividing resistor, a reference voltage, and a fault logic control circuit 20, a current detection signal ITRIP is input to a positive input end of the first comparator 27, VREF is divided by the voltage dividing resistor (a third resistor 28, a fourth resistor 29, and a fifth resistor 30), and a reference voltage VREF signal of a voltage dividing point a is obtained and is input to a negative input end of the first comparator 27; the end D of the second MOS tube 31 is connected with the connecting ends of the fourth resistor 29 and the fifth resistor 30, and the end S is connected with one end of the fifth resistor 30 of the voltage dividing resistor to be grounded. The output terminal of the first comparator 27 is connected to the fault logic control circuit 20, and is fed back to the upper bridge and lower bridge driving circuits, and when the current detection signal ITRIP is higher than the reference voltage, the fault logic control circuit 20 turns off the upper bridge and the lower bridge at the same time. The feedback end of the fault logic control circuit 20 is connected with the gate G of the second MOS tube 31 to control the switch of the second MOS tube 31. When the voltage higher than the reference voltage is not applied, the second MOS transistor 31 is turned off, and when the voltage higher than the reference voltage is applied, the second MOS transistor 31 is turned on. A hysteresis effect is formed and the overcurrent protection circuit 8 realizes an overcurrent protection function.

In this embodiment, the over-temperature protection circuit 9 includes a second comparator 32, a sixth resistor 33, a seventh resistor 34, an eighth resistor 35, and a third MOS transistor 36; the positive input end of the second comparator 32 is connected to a current detection signal, the negative input end of the second comparator 32 is connected between the first end of the sixth resistor 33 and the first end of the seventh resistor 34, and the output end of the second comparator 32 is connected to the fault logic control circuit 20; a second end of the sixth resistor 33 is connected to a reference voltage, a second end of the seventh resistor 34 is connected to a first end of the eighth resistor 35, and a second end of the eighth resistor 35 is grounded; the source electrode of the third MOS transistor 36 is connected to the second end of the eighth resistor 35, the drain electrode of the third MOS transistor 36 is connected to the first end of the eighth resistor 35, and the gate electrode of the third MOS transistor 36 is connected to the fault logic control circuit 20.

Specifically, the temperature detection TVC signal is input to the positive input end of the second comparator 32, VREF is divided by the sixth resistor 33, the seventh resistor 34, and the eighth resistor 35, and then a reference voltage signal of the voltage division point B is obtained and input to the negative input end of the comparator; the end D of the third MOS tube 36 is connected with the connection ends of the seventh resistor 34 and the eighth resistor 35, the end S of the third MOS tube 36 is grounded, the output end of the second comparator 32 is connected to the fault logic control circuit 20 and is fed back to the overcurrent protection circuit 8, when the temperature detection signal TVC is higher than the reference voltage, the fault logic control circuit outputs a signal to the overcurrent protection circuit 8 for adjustment, the overcurrent threshold of the overcurrent protection circuit 8 enables the PFC driving circuit 4 to work in a reliable and controllable safe working environment, and the feedback end of the fault logic control circuit 20 is connected with the grid G of the third MOS tube 36 to control the switching of the third MOS tube 36. When the voltage higher than the reference voltage is not applied, the third MOS transistor 36 is turned off, and when the voltage higher than the reference voltage is applied, the third MOS transistor 36 is turned on. A hysteresis effect is formed, and the overcurrent protection circuit 8 realizes the adjustment of the overcurrent protection threshold.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any such modifications, equivalents, and improvements that fall within the spirit and principles of the present invention are intended to be covered by the following claims.

Claims

1. A high voltage integrated circuit, comprising: a power supply circuit connected with the power supply voltage, a high-side driving circuit of 6 channels, a low-side driving circuit of 6 channels, a PFC driving circuit of 1 channel, a dead zone circuit and a frequency division circuit; the high-side driving circuit is respectively and electrically connected with the low-side driving circuit and the power supply circuit, a first end of the dead zone circuit is respectively connected with the high-side driving circuit and the low-side driving circuit, a second end of the dead zone circuit is connected with a first end of the frequency dividing circuit, and a second end of the frequency dividing circuit is used for respectively dividing 6 paths of PWM waves into complementary high-side and low-side driving PWM waves;

2. The high voltage integrated circuit of claim 1, wherein the frequency divider circuit comprises a not gate, an input of the not gate is connected to a PWMIN1 port, a first output of the not gate is connected to a PWMOUT1 port, and a second output of the not gate is connected to a PWMOUT2 port; the PWM wave input by the PWMIN1 port is consistent with the timing chart of the PWM wave output by the PWMOUT1 port, and the PWM wave input by the PWMIN1 port is opposite to the timing chart of the PWM wave output by the PWMOUT2 port.

3. The high voltage integrated circuit of claim 2, wherein the dead zone circuit comprises a first resistor, a first capacitor and a first diode, the first resistor is connected in parallel with the first diode, a first end of the first capacitor is connected with a positive pole of the first diode and a first output end of the not gate respectively, a second end of the first capacitor is grounded, and a negative pole of the first diode is connected with an input end of the not gate.

4. The high voltage integrated circuit of claim 1, further comprising a VREG generation circuit, an RC filter circuit, a schmitt trigger circuit, a low pass filter, a level shifter circuit, a pulse driver circuit, a delay circuit, a fault logic control circuit, a tri-and gate, a fault output circuit, and a high voltage region detection circuit; the VREG generation circuit is connected with the first end of the under-voltage protection circuit, the second end of the under-voltage protection circuit is connected with the fault logic control circuit, the Schmidt trigger circuit is sequentially connected with the RC filter circuit, the level conversion circuit and the fault logic control circuit, the fault logic control circuit is respectively connected with the driving current protection circuit, the over-temperature protection circuit and the dead zone circuit, the output ends of the three AND gates are connected with the first end of the pulse driving circuit, the input ends of the three AND gates are respectively connected with the over-current protection circuit and the fault logic control circuit, and the second end of the pulse driving circuit is connected with the fault output circuit.

5. The high voltage integrated circuit of claim 4, wherein the bootstrap circuit comprises a first MOS transistor, a source of the first MOS transistor is connected to a VB port of the high side drive circuit, a drain of the first MOS transistor is connected to the supply voltage, and a gate of the first MOS transistor is connected to an LO port of the low side drive circuit.

6. The high voltage integrated circuit of claim 5, wherein the bootstrap circuit further comprises a second capacitor, a high side power transistor Q1, a low side power transistor Q2, a MOS transistor Q3, a high side drive switch for connecting a high side drive signal, and a low side drive switch for connecting a low side drive signal; the first end of the high-side driving switch is respectively connected with the source electrode of the MOS tube Q3 and the first end of the second capacitor, and the second end of the high-side driving switch is connected with the base electrode of the high-side power tube Q1; the third end of the high-side driving switch is respectively connected with the second end of the second capacitor and the emitter of the high-side power tube Q1, and the collector of the high-side power tube Q1 is connected with a power supply voltage; the drain electrode of the MOS tube Q3 is connected with the power supply voltage, the grid electrode of the MOS tube Q3 is connected with the input end of the low-side driving switch, the output end of the low-side driving switch is connected with the base electrode of the low-side power tube Q2, the emitter electrode of the low-side power tube Q2 is connected with the second resistor and grounded, and the collector electrode of the low-side power tube Q2 is connected with the emitter electrode of the high-side power tube Q1.

7. The high voltage integrated circuit of claim 4, wherein the over-current protection circuit comprises a first comparator, a third resistor, a fourth resistor, a fifth resistor, and a second MOS transistor; the positive input end of the first comparator is used for being connected with a current detection signal, the negative input end of the first comparator is connected between the first end of the third resistor and the first end of the fourth resistor, and the output end of the first comparator is connected with the fault logic control circuit; the second end of the third resistor is connected with a reference voltage, the second end of the fourth resistor is connected with the first end of the fifth resistor, and the second end of the fifth resistor is grounded;

8. The high voltage integrated circuit of claim 4, wherein the over-temperature protection circuit comprises a second comparator, a sixth resistor, a seventh resistor, an eighth resistor, and a third MOS transistor; the positive input end of the second comparator is used for being connected with a current detection signal, the negative input end of the second comparator is connected between the first end of the sixth resistor and the first end of the seventh resistor, and the output end of the second comparator is connected with the fault logic control circuit; the second end of the sixth resistor is connected with a reference voltage, the second end of the seventh resistor is connected with the first end of the eighth resistor, and the second end of the eighth resistor is grounded;