CN116190380A - Groove type MOS device and preparation method thereof - Google Patents
Groove type MOS device and preparation method thereof Download PDFInfo
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- CN116190380A CN116190380A CN202310041130.9A CN202310041130A CN116190380A CN 116190380 A CN116190380 A CN 116190380A CN 202310041130 A CN202310041130 A CN 202310041130A CN 116190380 A CN116190380 A CN 116190380A
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention discloses a trench type MOS device and a preparation method thereof, and relates to the technical field of transistor processing. The invention is used for solving the technical problems that the substrate is thinned for many times and lacks of fixed bonding in the polishing and grinding process, the warping probability of the substrate is increased, the front forming structure lacks of protection and is easy to be stained, and the voltage resistance and the peak voltage and peak current inhibiting performance are to be improved. According to the trench type MOS device, the enhanced electrode layer and the titanium bonding layer are formed below the metal electrode body, so that the electric field intensity at the bottom of the trench is reduced, and meanwhile, the peak voltage and the peak current are effectively suppressed; the groove type MOS device has high processing yield, low cost, small voltage and current fluctuation during use and excellent performance; the stain-resistant protective film is stuck before thinning, so that the formed MOS device main body structure can be isolated and protected, and the die wafer substrate and the thick carrier can be fixed by temporary bonding of bonding glue, so that warping in the polishing and grinding process is avoided.
Description
Technical Field
The invention belongs to the technical field of transistor processing, and particularly relates to a trench type MOS device and a preparation method thereof.
Background
The MOS transistor is called a metal-oxide-semiconductor field effect transistor or a metal-insulator-semiconductor field effect transistor, and belongs to an insulated gate type field effect transistor, and therefore, the MOS transistor is sometimes called an insulated gate type field effect transistor. The grid electrode and the source electrode of the MOS tube are insulated, and the voltage generates an electric field so as to generate source electrode-drain electrode current. The gate voltage determines the drain current at this time, and the drain current can be controlled by controlling the gate voltage. Therefore, the MOS transistor is a device for controlling current by changing voltage, and is therefore a voltage device, and the input characteristic of the MOS transistor is a capacitive characteristic, so that the input impedance is extremely high.
At present, a plurality of reports about a trench type MOS device and a manufacturing method thereof are provided, and the patent of the grant publication No. CN109004030B sequentially comprises a polysilicon layer, a silicon nitride layer, a substrate structure of a first epitaxial layer and a second epitaxial layer, a gate dielectric layer, a first dielectric layer and a metal electrode leading-out end from bottom to top; the problem that the prior groove type MOS device is invalid due to outward diffusion of phosphorus in high-concentration doped polysilicon on the back surface of a wafer in a gate oxide growth process is solved. The patent of the publication number CN111276542B discloses that after the structure required on the front surface of the wafer of the trench MOS device is fabricated by a conventional process, the back surface of the wafer of the trench MOS device is first thinned to a conventional thickness, then a barrier layer with a flat upper surface is formed on the front surface of the wafer of the trench MOS device to protect the device structure on the front surface of the wafer of the trench MOS device, and a flat bonding surface is provided, and then a carrier wafer is used to bond to the barrier layer, which can carry the wafer of the trench MOS device after the first thinning, and offset the stress therein in the process of further thinning the back surface of the wafer of the trench MOS device again, so that the back surface of the wafer of the trench MOS device can be thinned to a limited required thickness without damaging the front surface structure of the wafer of the trench MOS device. However, the following technical problems are found: the operation of thinning the substrate for many times and the lack of fixed bonding in the polishing and grinding process increase the probability of warping of the substrate, and the lack of protection of the front molding structure is easy to be stained, and the voltage-resisting performance and the performance of inhibiting spike voltage and spike current are required to be improved.
Disclosure of Invention
The invention aims to provide a trench type MOS device and a preparation method thereof, which are used for solving the technical problems that in the prior art, the substrate is thinned for many times, fixed bonding is absent in the polishing and grinding process, the probability of substrate warpage is increased, the front forming structure is easy to be stained due to lack of protection, and the voltage-resisting performance and the performance of inhibiting spike voltage and spike current are to be improved.
The aim of the invention can be achieved by the following technical scheme:
the invention provides a trench type MOS device, which comprises a thinned substrate layer, a silicon nitride layer, a middle substrate layer, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top, wherein a plurality of gate trenches are downwards extended in the second epitaxial layer, a gate oxide layer and a polysilicon oxide layer are sequentially formed at the lower part of the inner surface of each gate trench from outside to inside, a gate dielectric layer and a polysilicon layer are sequentially formed at the upper part of the inner surface of each gate trench from outside to inside, a metal electrode body penetrating through the second epitaxial layer is arranged in each gate trench, a reinforced electrode layer and a titanium bonding layer are sequentially arranged between each metal electrode body and the bottom of each gate trench, an N+ source region layer is arranged outside each gate oxide layer and each gate dielectric layer and above the second epitaxial layer, an insulating dielectric layer is arranged above each N+ source region layer, a plurality of contact holes filled with metal penetrate through the insulating dielectric layer and extend to the second epitaxial layer, and a metal region layer is arranged above each insulating dielectric layer.
As a further preferable scheme of the invention, the thinning substrate layer is obtained by thinning a die wafer substrate, and the thickness is 10-20 mu m.
The invention also provides a preparation method of the groove type MOS device, which comprises the following steps:
selecting a bare chip wafer substrate with a first conductivity type, and sequentially forming a silicon nitride layer, an intermediate substrate layer with the first conductivity type, a first epitaxial layer and a second epitaxial layer on the upper surface of the bare chip wafer substrate through an epitaxial growth process;
photoetching and etching the surface of the second epitaxial layer to form a plurality of mutually parallel grid grooves;
depositing a layer of silicon dioxide on the surfaces of the gate groove and the second epitaxial layer to form a first dielectric layer;
depositing N-type or P-type doped conductive polysilicon on the first dielectric layer, forming a gate oxide layer and a polysilicon oxide layer on the lower part of the inner surface of the gate trench by dry etching, and forming a gate dielectric layer and a polysilicon layer on the upper part of the inner surface of the gate trench;
implanting P-type impurity ions into the first dielectric layer outside the gate dielectric layer, and performing rapid annealing treatment to form an N+ source electrode region layer;
depositing a metal titanium binder in the inner area of the grid electrode groove to obtain a titanium binding layer, depositing titanium nitride on the surface of the titanium binding layer to obtain a reinforced electrode layer, and depositing metal tungsten on the surface of the reinforced electrode layer to form a metal electrode body;
step seven, if a layer of silicon dioxide is deposited above the N+ source electrode region layer to form a second dielectric layer, grooves of a plurality of contact holes are formed through dry etching, and metal tungsten or copper is deposited into the grooves of the contact holes;
depositing a layer of silicon dioxide which is flush with the second dielectric layer above the contact hole, and forming an insulating dielectric layer with the rest second dielectric layer;
step nine, depositing copper alloy above the insulating dielectric layer to obtain a metal area layer;
step ten, spin-coating bonding glue on the back surface of the die wafer substrate to adhere to a thick carrier after adhering the stain-resistant protective film, and polishing and removing the area needing thinning on the back surface of the die wafer substrate through a wafer thinning polishing machine after vacuum adsorption to form a thinning substrate layer;
and step eleven, heating to remove bonding glue on the back surface of the thinned substrate layer, and packaging to obtain the trench type MOS device.
As a further preferable scheme of the invention, the doping concentration of the first conductivity type in the intermediate substrate layer, the first epitaxial layer and the second epitaxial layer is sequentially reduced; the doping ions of the first conductivity type are B, BF 2 One or more of In; the die wafer substrate has a thickness of 725 μm.
In a further preferred embodiment of the present invention, a contamination-resistant protective film is attached to the upper surface of the metal region layer, and the silicon nitride layer, the intermediate substrate layer, the first epitaxial layer, the second epitaxial layer, and the outer periphery of the insulating dielectric layer, and the area of the die wafer substrate that does not need to be thinned.
As a further preferable scheme of the invention, the stain-resistant protective film comprises a substrate layer, an antistatic pressure-sensitive adhesive layer, a hydrophobic protective film layer and a fluorine release film layer which are sequentially arranged from one side to the other side, wherein the substrate layer is a biaxially oriented polyester film, and the thickness range of the substrate layer is 5-15 mu m; the antistatic pressure-sensitive adhesive layer is formed by coating and drying the following components in parts by weight: 10-25 parts of polyether-ether-ketone resin, 0.5-3 parts of hydrogen-containing silicone oil, 5-10 parts of polymethyl methacrylate, 0.2-0.6 part of gamma-glycidyl ether oxypropyl trimethoxy silane and 50-80 parts of ethyl acetate; the hydrophobic protective film layer is formed by coating and drying the following components in parts by weight: 35-50 parts of aqueous polyurethane emulsion, 2-6 parts of SEBS block copolymer, 0.3-0.8 part of 1-hydroxycyclohexyl phenyl ketone and 0.2-0.6 part of hydrogen-containing silicone oil.
As a further preferable mode of the invention, the polyether-ether-ketone resin has a glass transition temperature of 143 ℃, a melting point of 334 ℃, a bending strength of 145MPa and a volume resistance of 10 16 Omega cm; the solid content of the aqueous polyurethane emulsion is 31-33%, the viscosity is 20-200 mPa.s, and the pH value is 7-9.
As a further preferable scheme of the invention, the preparation method of the bonding adhesive comprises the following steps:
adding hexafluorobisphenol a and bisphenol fluorene into a three-neck flask equipped with a mechanical stirrer, a condenser pipe and a dropping funnel, dropwise adding sodium hydroxide solution into the dropping funnel, stirring at normal temperature, dropwise adding triphosgene dichloromethane solution after dropwise adding, adding triethylamine after dropwise adding triphosgene dichloromethane solution, heating and refluxing for 2-4 hours, washing with deionized water to neutrality, concentrating under reduced pressure to remove dichloromethane, recrystallizing acetone, and drying to constant weight to obtain white powdery polycarbonate resin; wherein, the mole ratio of hexafluorobisphenol a to bisphenol fluorene, triethylamine, sodium hydroxide and triphosgene is 3:2:0.6:11:2, the concentration of the sodium hydroxide solution is 10-15 wt%, and the dosage of the methylene dichloride is 3-5 times of the mass of the triphosgene;
the synthetic reaction formula of the polycarbonate resin is as follows:
adding 30-42 parts by weight of polycarbonate resin, 6-10 parts by weight of hydrogenated rosin glyceride, 0.5-2 parts by weight of 2, 6-di-tert-butyl-p-cresol and 0.2-0.6 part by weight of polyether modified siloxane into a reaction kettle, and uniformly stirring at normal temperature to obtain bonding glue.
The invention has the following beneficial effects:
1. according to the trench type MOS device, the thickness of the multilayer epitaxial structure is increased, meanwhile, the toughness is improved, and the warping phenomenon caused by stress during the thinning treatment of the substrate is avoided; the plurality of oxide layers and the dielectric layers formed on the inner surfaces of the grid electrode grooves promote the high integration of the metal electrode body; the enhanced electrode layer and the titanium bonding layer formed below the metal electrode body reduce the electric field intensity at the bottom of the groove, improve the voltage withstand performance and effectively inhibit peak voltage and peak current; the effect of reducing resistance and improving device performance is realized by thinning the substrate layer; the groove type MOS device has high processing yield, low cost, small voltage and current fluctuation during use and excellent performance.
2. According to the preparation method of the trench type MOS device, the silicon nitride layer is epitaxially grown on the upper surface of the wafer substrate of the bare chip, so that the downward diffusion of doping ions in the middle substrate layer, the first epitaxial layer and the second epitaxial layer can be effectively restrained, and the pollution to the substrate during subsequent deposition, etching and thinning treatment is avoided; by forming a plurality of oxide layers and dielectric layers on the inner surface of the grid electrode groove, the effective side length in the unit groove is increased, and the performance of the MOS device is improved; the pollution-resistant protective film is stuck before the thinning treatment, the formed main structure of the MOS device can be isolated and protected, the pollution of substrate waste materials, electrostatic conduction and infiltration corrosion of cleaning liquid in the polishing and grinding process are avoided, the reject ratio of the MOS device is increased, the temporary bonding of bonding glue can fix the bare chip wafer substrate with a thick carrier, the warping generated in the polishing and grinding process is avoided, the bonding glue is corrosion-resistant and strong in stability, the bonding glue can be removed after the thinning is finished, and the final performance of the thinning substrate layer is not influenced.
3. According to the stain-resistant protective film, the antistatic pressure-sensitive adhesive layer in the hierarchical structure takes high-temperature-resistant, high-strength and antistatic polyether-ether-ketone resin as a main component, and is compounded with low-temperature film-forming and hydrophobic hydrogen-containing silicone oil, insulating, easy-to-process and heat-resistant polymethyl methacrylate, and a silane coupling agent gamma-glycidol ether oxypropyl trimethoxy silane is coated and dried to form a high-temperature-resistant, hydrophobic and antistatic film layer, so that the main structure of an MOS device is isolated from heat, static electricity and cleaning water; the hydrophobic protective film layer is formed by compounding weather-resistant waterborne polyurethane, a thermally stable and ageing-resistant SEBS block copolymer, an antioxidant 1-hydroxycyclohexyl phenyl ketone and film-forming hydrophobic hydrogen-containing silicone oil, and has good heat resistance and ageing resistance, so that the main structure of the MOS device is protected to further isolate heat and cleaning water.
4. According to the bonding adhesive, the polycarbonate resin is generated by polymerizing the hexafluorobisphenol a and bisphenol fluorene under the polycondensation catalysis of triphosgene, bisphenol fluorene with a benzene ring heterocyclic structure is introduced, and on the basis of increasing relative molecular mass and improving heat resistance, strong electronegativity brought by the bisphenol fluorene with a plurality of fluorocarbon bonds shows good weather resistance and heat resistance, and the temporary bonding with a bare chip wafer substrate can fix the bare chip wafer substrate and a thick carrier, so that warping generated in the polishing and grinding process is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a trench MOS device according to the present invention;
fig. 2 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after the completion of step one;
fig. 3 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after the completion of the second step;
fig. 4 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after the third step is completed;
fig. 5 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after the fifth step is completed;
fig. 6 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after the completion of step six;
fig. 7 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after completion of step seven;
fig. 8 is a schematic structural diagram of the trench MOS device manufacturing method according to the present invention after the completion of step eight;
fig. 9 is a schematic structural diagram of the trench MOS device manufacturing method of the present invention before the step ten is completed to form the thinned substrate layer.
Reference numerals: 10. thinning the substrate layer; 20. a silicon nitride layer; 30. an intermediate substrate layer; 40. a first epitaxial layer; 50. a second epitaxial layer; 51. a gate oxide layer; 52. a polysilicon oxide layer; 53. a gate dielectric layer; 54. a polysilicon layer; 55. a metal electrode body; 56. reinforcing the electrode layer; 57. a titanium bonding layer; 60. an n+ source region layer; 70. an insulating dielectric layer; 80. a contact hole; 90. a metal region layer; 100. a die wafer substrate; 110. a gate trench; 120. a first dielectric layer; 130. a second dielectric layer; 140. a stain-resistant protective film; 150. and (5) bonding glue.
Description of the embodiments
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 1, a trench MOS device of this embodiment includes a thinned substrate layer 10, a silicon nitride layer 20, a middle substrate layer 30, a first epitaxial layer 40 and a second epitaxial layer 50 sequentially disposed from bottom to top, a plurality of gate trenches 110 extending downward in the second epitaxial layer 50, a gate oxide layer 51 and a polysilicon oxide layer 52 sequentially formed from outside to inside at the lower part of the inner surface of the gate trench 110, a gate dielectric layer 53 and a polysilicon layer 54 sequentially formed from outside to inside at the upper part of the inner surface of the gate trench 110, a metal electrode body 55 penetrating through the second epitaxial layer 50 is disposed in the interior of the gate trench 110, a reinforcing electrode layer 56 and a titanium bonding layer 57 sequentially disposed between the metal electrode body 55 and the bottom of the gate trench 110, an n+ source region layer 60 disposed above the second epitaxial layer 50 and the gate oxide layer 51, an insulating dielectric layer 70 disposed above the n+ source region layer 60, a plurality of metal-filled contact holes 80 extending through the insulating dielectric layer 70 and into the second epitaxial layer 50, and a metal region 90 disposed above the insulating layer 70. The thinned substrate layer 10 is obtained by thinning a bare chip wafer substrate, and has a thickness of 10-20 mu m.
Compared with the prior art, the trench type MOS device of the embodiment has the advantages that the silicon nitride layer 20, the middle substrate layer 30, the first epitaxial layer 40 and the second epitaxial layer 50 are arranged above the substrate, so that the thickness of the multilayer epitaxial structure is increased, the toughness is improved, and the warping phenomenon caused by stress during the thinning treatment of the substrate is avoided; the plurality of oxide layers and dielectric layers formed on the inner surface of the gate trench 110 promote high integration of the metal electrode body 55; forming the reinforcing electrode layer 56 and the titanium bonding layer 57 under the metal electrode body 55, the electric field intensity at the bottom of the trench is reduced, and simultaneously, the spike voltage and spike current can be effectively suppressed due to the withstand voltage effect of the reinforcing electrode layer 56; thinning the substrate layer 10 achieves the effects of reducing resistance and improving device performance; the groove type MOS device has high processing yield, low cost, small voltage and current fluctuation during use and excellent performance.
The preparation method of the trench type MOS device of the embodiment comprises the following steps:
step one, as shown in fig. 2, selecting a die wafer substrate 100 with a first conductivity type, and sequentially forming a silicon nitride layer 20, an intermediate substrate layer 30 with the first conductivity type, a first epitaxial layer 40 and a second epitaxial layer 50 on the upper surface of the die wafer substrate 100 through an epitaxial growth process; the doping concentration of the first conductivity type within the intermediate substrate layer 30, the first epitaxial layer 40 and the second epitaxial layer 50 decreases in sequence; the doping ions of the first conductivity type are B, BF 2 One or more of In; the thickness of the die wafer substrate 100 is 725 μm; by epitaxially growing the silicon nitride layer 20 on the upper surface of the die wafer substrate 100, the downward diffusion of doping ions in the intermediate substrate layer 30, the first epitaxial layer 40 and the second epitaxial layer 50 can be effectively inhibited, and the contamination of the substrate during subsequent deposition, etching and thinning processes is avoided;
step two, as shown in fig. 3, performing photolithography and etching on the surface of the second epitaxial layer 50 to form a plurality of gate trenches 110 parallel to each other;
step three, as shown in fig. 4, a layer of silicon dioxide is deposited on the surfaces of the gate trench 110 and the second epitaxial layer 50 to form a first dielectric layer 120;
step four, as shown in fig. 5, depositing N-type or P-type doped conductive polysilicon on the first dielectric layer 120, forming a gate oxide layer 51 and a polysilicon oxide layer 52 on the lower part of the inner surface of the gate trench 110 by dry etching, and forming a gate dielectric layer 53 and a polysilicon layer 54 on the upper part of the inner surface of the gate trench 110; by forming a plurality of oxide layers and dielectric layers on the inner surface of the gate trench 110, the effective side length in the unit trench is increased, and the performance of the MOS device is improved; by forming a plurality of oxide layers and dielectric layers on the inner surface of the gate trench 110, the effective side length in the unit trench is increased, and the performance of the MOS device is improved;
step five, implanting P-type impurity ions into the first dielectric layer 120 outside the gate dielectric layer 53, and performing rapid annealing treatment to form an n+ source region layer 60;
step six, as shown in fig. 6, depositing a metal titanium binder in the inner area of the gate trench 110 to obtain a titanium binding layer 57, depositing titanium nitride on the surface of the titanium binding layer 57 to obtain a reinforced electrode layer 56, and depositing metal tungsten on the surface of the reinforced electrode layer 56 to form a metal electrode body 55;
step seven, as shown in fig. 7, a layer of silicon dioxide is deposited above the n+ source region layer 60 to form a second dielectric layer 130, grooves of a plurality of contact holes 80 are formed by dry etching, and metal tungsten or copper is deposited into the grooves of the contact holes 80;
step eight, as shown in fig. 8, a layer of silicon dioxide which is flush with the second dielectric layer 130 is deposited over the contact hole 80, and an insulating dielectric layer 70 is formed with the remaining second dielectric layer 130;
step nine, as shown in fig. 9, depositing copper alloy on the insulating dielectric layer 70 to obtain a metal region layer 90;
step ten, adhering a stain-resistant protective film 140 to the upper surface of the metal region layer 90, the silicon nitride layer 20, the middle substrate layer 30, the first epitaxial layer 40, the second epitaxial layer 50 and the periphery of the insulating medium layer 70 and the area of the die wafer substrate 100 which is not required to be thinned, adhering the spin-on bonding adhesive 150 on the back surface of the die wafer substrate 100 to a thick carrier, and polishing and removing the area of the back surface of the die wafer substrate 100 by a wafer thinning and polishing machine after vacuum adsorption to form a thinned substrate layer 10; the stain-resistant protective film 140 is stuck before the thinning treatment, so that the formed main structure of the MOS device can be isolated and protected, the pollution of substrate waste materials, electrostatic conduction and infiltration corrosion of cleaning liquid in the polishing and grinding process are avoided, the reject ratio of the MOS device is increased, the die wafer substrate 100 and a thick carrier can be fixed by the temporary bonding of the bonding adhesive 150, the warping in the polishing and grinding process is avoided, the bonding adhesive 150 is corrosion-resistant, strong in stability and low in thermal expansion coefficient, and can be removed by heating after the thinning is finished, and the final performance of the thinned substrate layer 10 is not influenced;
and step eleven, heating to remove the bonding adhesive 150 on the back surface of the thinned substrate layer 10, and packaging to obtain the trench type MOS device.
Example 2
The embodiment provides a stain-resistant protective film, which is suitable for preparing a groove type MOS device in the embodiment 1, and comprises a substrate layer, an antistatic pressure-sensitive adhesive layer, a hydrophobic protective film layer and a fluorine release film layer which are sequentially arranged from one side to the other side, wherein the substrate layer is a biaxially oriented polyester film, and the thickness range of the substrate layer is 5-15 mu m; the antistatic pressure-sensitive adhesive layer is formed by coating and drying the following components in parts by weight: 16g of polyether-ether-ketone resin, 1.2g of hydrogen-containing silicone oil, 7g of polymethyl methacrylate, 0.4g of gamma-glycidyl ether oxypropyl trimethoxysilane and 65g of ethyl acetate; the hydrophobic protective film layer is formed by coating and drying the following components in weight: 42g of aqueous polyurethane emulsion, 4g of SEBS block copolymer, 0.5g of 1-hydroxycyclohexyl phenyl ketone and 0.4g of hydrogen-containing silicone oil.
Wherein the glass transition temperature of the polyether-ether-ketone resin is 143 ℃, the melting point is 334 ℃, the bending strength is 145MPa, and the volume resistance is 10 16 Omega cm; the solid content of the aqueous polyurethane emulsion is 31-33%, the viscosity is 20-200 mPa.s, and the pH value is 7-9. When the stain-resistant protective film is used, the fluorine release film layer is torn off, and the hydrophobic protective film layer is adhered to the outer surface of the area which is not required to be thinned as shown in fig. 9.
Example 3
The embodiment provides a stain-resistant protective film, which is suitable for preparing a groove type MOS device in the embodiment 1, and comprises a substrate layer, an antistatic pressure-sensitive adhesive layer, a hydrophobic protective film layer and a fluorine release film layer which are sequentially arranged from one side to the other side, wherein the substrate layer is a biaxially oriented polyester film, and the thickness range of the substrate layer is 5-15 mu m; the antistatic pressure-sensitive adhesive layer is formed by coating and drying the following components in parts by weight: 24g of polyether-ether-ketone resin, 2.6g of hydrogen-containing silicone oil, 9g of polymethyl methacrylate, 0.6g of gamma-glycidyl ether oxypropyl trimethoxysilane and 76g of ethyl acetate; the hydrophobic protective film layer is formed by coating and drying the following components in weight: 48g of aqueous polyurethane emulsion, 6g of SEBS block copolymer, 0.7g of 1-hydroxycyclohexyl phenyl ketone and 0.6g of hydrogen-containing silicone oil.
Wherein the glass transition temperature of the polyether-ether-ketone resin is 143 ℃, the melting point is 334 ℃, the bending strength is 145MPa, and the volume resistance is 10 16 Omega cm; the solid content of the aqueous polyurethane emulsion is 31-33%, the viscosity is 20-200 mPa.s, and the pH value is 7-9. When the stain-resistant protective film is used, the fluorine release film layer is torn off, and the hydrophobic protective film layer is adhered to the outer surface of the area which is not required to be thinned as shown in fig. 9.
Example 4
The embodiment provides a preparation method of bonding glue, which is suitable for preparing a trench type MOS device in embodiment 1, and comprises the following steps:
adding 10.1g of hexafluorobisphenol a and 7g of bisphenol fluorene into a three-neck flask provided with a mechanical stirrer, a condenser pipe and a dropping funnel, dropwise adding 29.3g of 15wt% sodium hydroxide solution into the dropping funnel, stirring at normal temperature, dropwise adding a methylene dichloride solution containing 5.9g of triphosgene after the dropwise adding is finished, adding 0.6g of triethylamine after the dropwise adding of the methylene dichloride solution of triphosgene is finished, heating, refluxing for 3 hours, washing with deionized water to neutrality, concentrating under reduced pressure to remove methylene dichloride, recrystallizing acetone, and drying to constant weight to obtain white powdery polycarbonate resin; wherein, the dosage of the methylene dichloride is 23.6g;
step two, adding 35g of polycarbonate resin, 7g of hydrogenated rosin glyceride, 0.6g of 2, 6-di-tert-butyl-p-cresol and 0.4g of polyether modified siloxane into a reaction kettle, and stirring uniformly at normal temperature to obtain bonding adhesive, wherein the bonding adhesive is spin-coated on the back surface of a die wafer substrate 100 when in use as shown in figure 9.
Example 5
The embodiment provides a preparation method of bonding glue, which is suitable for preparing a trench type MOS device in embodiment 1, and comprises the following steps:
adding 10.1g of hexafluorobisphenol a and 7g of bisphenol fluorene into a three-neck flask provided with a mechanical stirrer, a condenser pipe and a dropping funnel, dropwise adding 29.3g of 15wt% sodium hydroxide solution into the dropping funnel, stirring at normal temperature, dropwise adding a methylene dichloride solution containing 5.9g of triphosgene after the dropwise adding is finished, adding 0.6g of triethylamine after the dropwise adding of the methylene dichloride solution of triphosgene is finished, heating, refluxing for 4 hours, washing with deionized water to neutrality, concentrating under reduced pressure to remove methylene dichloride, recrystallizing acetone, and drying to constant weight to obtain white powdery polycarbonate resin; wherein, the dosage of the methylene dichloride is 29.5g;
step two, 42g of polycarbonate resin, 10g of hydrogenated rosin glyceride, 1.8g of 2, 6-di-tert-butyl-p-cresol and 0.6g of polyether-modified siloxane are added into a reaction kettle, and the mixture is spin-coated on the back surface of a bare chip wafer substrate 100 as shown in FIG. 9 when in use.
The foregoing is merely illustrative and explanatory of the invention, as it is well within the scope of the invention as claimed, as it relates to various modifications, additions and substitutions for those skilled in the art, without departing from the inventive concept and without departing from the scope of the invention as defined in the accompanying claims.
In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the invention disclosed above are intended only to assist in the explanation of the invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (8)
1. The utility model provides a trench MOS device, a serial communication port, including attenuate substrate layer (10) that sets gradually from the bottom up, silicon nitride layer (20), middle substrate layer (30), first epitaxial layer (40) and second epitaxial layer (50), downwardly extending is equipped with a plurality of gate trenches (110) in second epitaxial layer (50), gate oxide layer (51) and polycrystalline silicon oxide layer (52) have been formed in proper order from outside to inside in the internal surface lower part of gate trench (110), gate dielectric layer (53) and polycrystalline silicon layer (54) have been formed in proper order from outside to inside in the internal surface upper part of gate trench (110), the inside of gate trench (110) is equipped with metal electrode body (55) that runs through out second epitaxial layer (50), be equipped with reinforcing electrode layer (56) and titanium tie coat (57) in proper order between the bottom of metal electrode body (55) and gate trench (110), the outside of gate oxide layer (51) and gate dielectric layer (53) are located the top of second epitaxial layer (50) and are equipped with N+ source region (60), the top of N+ source region (60) is equipped with gate dielectric layer (70) and is equipped with metal layer (70) and extends to dielectric layer (70) in proper order, it has dielectric layer (70) to be equipped with insulating layer (70) to extend to top dielectric layer (70).
2. The trench MOS device of claim 1, wherein the thinned substrate layer (10) is obtained by thinning a die wafer substrate to a thickness of 10-20 μm.
3. The preparation method of the trench type MOS device is characterized by comprising the following steps of:
selecting a bare chip wafer substrate (100) with a first conductivity type, and sequentially forming a silicon nitride layer (20), an intermediate substrate layer (30) with the first conductivity type, a first epitaxial layer (40) and a second epitaxial layer (50) on the upper surface of the bare chip wafer substrate (100) through an epitaxial growth process;
step two, photoetching and etching the surface of the second epitaxial layer (50) to form a plurality of mutually parallel grid grooves (110);
depositing a silicon dioxide layer on the surfaces of the gate trench (110) and the second epitaxial layer (50) to form a first dielectric layer (120);
depositing N-type or P-type doped conductive polysilicon on the first dielectric layer (120), forming a gate oxide layer (51) and a polysilicon oxide layer (52) on the lower part of the inner surface of the gate trench (110) by dry etching, and forming a gate dielectric layer (53) and a polysilicon layer (54) on the upper part of the inner surface of the gate trench (110);
implanting P-type impurity ions into the first dielectric layer (120) outside the gate dielectric layer (53), and performing rapid annealing treatment to form an N+ source electrode region layer (60);
depositing a metal titanium binder in the inner area of the gate trench (110) to obtain a titanium binding layer (57), depositing titanium nitride on the surface of the titanium binding layer (57) to obtain a reinforced electrode layer (56), and depositing metal tungsten on the surface of the reinforced electrode layer (56) to form a metal electrode body (55);
step seven, a layer of silicon dioxide is deposited above the N+ source electrode region layer (60) to form a second dielectric layer (130), grooves of a plurality of contact holes (80) are formed through dry etching, and metal tungsten or copper is deposited into the grooves of the contact holes (80);
depositing a layer of silicon dioxide which is flush with the second dielectric layer (130) above the contact hole (80), and forming an insulating dielectric layer (70) with the rest of the second dielectric layer (130);
step nine, depositing copper alloy above the insulating dielectric layer (70) to obtain a metal area layer (90);
step ten, spin-coating bonding glue (150) on the back surface of the die wafer substrate (100) to adhere to a thick carrier after adhering the stain-resistant protective film (140), and polishing and removing the area, needing thinning, of the back surface of the die wafer substrate (100) through a wafer thinning polishing machine after vacuum adsorption to form a thinning substrate layer (10);
and step eleven, heating to remove bonding glue (150) on the back surface of the thinned substrate layer (10), and packaging to obtain the trench type MOS device.
4. A method of fabricating a trench MOS device according to claim 3, characterized in that the doping concentration of the first conductivity type in the intermediate substrate layer (30), the first epitaxial layer (40) and the second epitaxial layer (50) is sequentially reduced; the doping ions of the first conductivity type are B, BF 2 One or more of In; the die wafer substrate (100) has a thickness of 725 μm.
5. The method for fabricating a trench MOS device according to claim 3, wherein in step ten, a contamination-resistant protective film (140) is attached to the upper surface of the metal region layer (90), and to the periphery of the silicon nitride layer (20), the intermediate substrate layer (30), the first epitaxial layer (40), the second epitaxial layer (50), and the insulating dielectric layer (70), and to the area of the die wafer substrate (100) that does not need to be thinned.
6. The method for manufacturing a trench type MOS device according to claim 3, wherein the stain-resistant protective film comprises a substrate layer, an antistatic pressure-sensitive adhesive layer, a hydrophobic protective film layer and a fluorine release film layer sequentially arranged from one side to the other side, the substrate layer is a biaxially oriented polyester film, and the thickness range of the substrate layer is 5-15 μm; the antistatic pressure-sensitive adhesive layer is formed by coating and drying the following components in parts by weight: 10-25 parts of polyether-ether-ketone resin, 0.5-3 parts of hydrogen-containing silicone oil, 5-10 parts of polymethyl methacrylate, 0.2-0.6 part of gamma-glycidyl ether oxypropyl trimethoxy silane and 50-80 parts of ethyl acetate; the hydrophobic protective film layer is formed by coating and drying the following components in parts by weight: 35-50 parts of aqueous polyurethane emulsion, 2-6 parts of SEBS block copolymer, 0.3-0.8 part of 1-hydroxycyclohexyl phenyl ketone and 0.2-0.6 part of hydrogen-containing silicone oil.
7. The method for manufacturing a trench MOS device of claim 6, wherein the polyetheretherketone resin has a glass transition temperature of 143 ℃, a melting point of 334 ℃, a bending strength of 145MPa, and a volume resistance of 10 16 Omega cm; the solid content of the aqueous polyurethane emulsion is 31-33%, the viscosity is 20-200 mPa.s, and the pH value is 7-9.
8. The method for manufacturing a trench MOS device of claim 3, wherein the method for manufacturing the bonding glue comprises the steps of:
adding hexafluorobisphenol a and bisphenol fluorene into a three-neck flask equipped with a mechanical stirrer, a condenser pipe and a dropping funnel, dropwise adding sodium hydroxide solution into the dropping funnel, stirring at normal temperature, dropwise adding triphosgene dichloromethane solution after dropwise adding, adding triethylamine after dropwise adding triphosgene dichloromethane solution, heating and refluxing for 2-4 hours, washing with deionized water to neutrality, concentrating under reduced pressure to remove dichloromethane, recrystallizing acetone, and drying to constant weight to obtain white powdery polycarbonate resin; wherein, the mole ratio of hexafluorobisphenol a to bisphenol fluorene, triethylamine, sodium hydroxide and triphosgene is 3:2:0.6:11:2, the concentration of the sodium hydroxide solution is 10-15 wt%, and the dosage of the methylene dichloride is 3-5 times of the mass of the triphosgene;
adding 30-42 parts by weight of polycarbonate resin, 6-10 parts by weight of hydrogenated rosin glyceride, 0.5-2 parts by weight of 2, 6-di-tert-butyl-p-cresol and 0.2-0.6 part by weight of polyether modified siloxane into a reaction kettle, and uniformly stirring at normal temperature to obtain bonding glue.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101308778A (en) * | 2008-06-06 | 2008-11-19 | 无锡中微高科电子有限公司 | Thinning method of semiconductor chip |
| CN106328647A (en) * | 2016-11-01 | 2017-01-11 | 西安后羿半导体科技有限公司 | High-speed groove MOS device and preparing method thereof |
| CN109004030A (en) * | 2017-06-06 | 2018-12-14 | 中航（重庆）微电子有限公司 | A kind of groove type MOS device architecture and its manufacturing method |
| CN111276542A (en) * | 2020-02-17 | 2020-06-12 | 中芯集成电路制造(绍兴)有限公司 | Groove type MOS device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308778A (en) * | 2008-06-06 | 2008-11-19 | 无锡中微高科电子有限公司 | Thinning method of semiconductor chip |
| CN106328647A (en) * | 2016-11-01 | 2017-01-11 | 西安后羿半导体科技有限公司 | High-speed groove MOS device and preparing method thereof |
| CN109004030A (en) * | 2017-06-06 | 2018-12-14 | 中航（重庆）微电子有限公司 | A kind of groove type MOS device architecture and its manufacturing method |
| CN111276542A (en) * | 2020-02-17 | 2020-06-12 | 中芯集成电路制造(绍兴)有限公司 | Groove type MOS device and manufacturing method thereof |
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