CN116190353A - Substrate-reinforced source region edge P-type heavily-doped radiation-resistant NMOS transistor structure - Google Patents
Substrate-reinforced source region edge P-type heavily-doped radiation-resistant NMOS transistor structure Download PDFInfo
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- 230000005855 radiation Effects 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 26
- 230000002787 reinforcement Effects 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 15
- 239000002245 particle Substances 0.000 abstract description 4
- 230000003471 anti-radiation Effects 0.000 abstract description 3
- 230000005865 ionizing radiation Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 230000003014 reinforcing effect Effects 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005524 hole trap Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention discloses a substrate-reinforced source region edge P-type heavily-doped anti-radiation NMOS transistor structure, and relates to the fields of microelectronic technology, integrated circuit manufacturing, semiconductor device ionizing radiation effect and the like. Aiming at the defect of the prior patent 'a total dose resistant CMOS circuit basic transistor structure', the invention provides a transistor structure adopting a new reinforcing measure, which can effectively inhibit negative effects such as NMOS (N-channel metal oxide semiconductor) tube turn-off current increase caused by ionizing radiation and the like, and improve the total dose resistance and single particle resistance of the device.
Description
Technical Field
The present invention relates to the field of semiconductor technology and integrated circuits, and more particularly to a transistor structure resistant to total dose and single event latch-up.
Background
The ionizing radiation effect on CMOS integrated circuits in the radiation environment is mainly the total dose effect and the single event effect.
The total dose effect means that various high-energy charged particles can enter the device for a long time in a radiation environment to generate a large number of electron-hole pairs, so that the working performance of the device is affected, and the reliability and the service life of the device can be greatly damaged. The total dose effect mainly affects the gate oxide and the shallow trench isolation oxide STI. After the device is irradiated, electron-hole pairs can appear in the oxide, electrons can quickly move out of the oxide due to the fact that the mobility of electrons is higher than that of holes, and only a small part of holes move out of the oxide, so that most of the remaining holes are trapped by hole traps in the oxide and on the surface to form fixed positive charges, the threshold voltage of the device can be reduced, and off-state leakage current is greatly increased. In large-scale MOS devices, the overall dose effect is more pronounced because of the thicker gate oxide and STI, which traps more holes in the oxide.
The single event effect refers to a radiation effect that causes abnormal changes in the state of the device when a single energetic particle passes through the sensitive region of the microelectronic device, including single event upset, single event locking, single event burnout, single event gate breakdown, etc.
At present, the anti-irradiation reinforcement measures for the transistor mainly comprise structures such as a ring grid, a half-ring grid, a protection ring and the like, but the structures have the problems of large occupied area, low flexibility in width-to-length ratio adjustment, inapplicability to large-scale integration and the like.
Patent 'a kind of anti-total dose CMOS circuit basic transistor structure' [1] The P-type heavily doped NMOS at the edge of the active region is proposed to improve the total dose effect of the transistor, but tunnel breakdown is easy to occur due to the fact that the N+ doping of the drain region of the structure is connected with the P-type heavily doped at the edge of the drain region, so that the working voltage of the transistor cannot be too high. In addition, the structure can only prevent the formation of a leakage channel on the side wall of a transistor channel, and can not block the leakage channel formed by inversion of a substrate due to positive charges accumulated at the bottom of an STI region of an integrated circuit when the total irradiation dose is high. Meanwhile, if a silicon metallization process exists in the transistor manufacturing process, the transistor with the structure can cause the problem of source-drain short circuit.
Reference is made to:
[1] liping, chen Kongbin A basic transistor structure of an anti-total dose CMOS circuit is CN106783853A [ P ].2017-05-31.
Disclosure of Invention
In view of the influence of radiation environment on electronic components and the shortcomings of the prior art, a substrate-reinforced source region edge P-type heavily doped NMOS transistor is provided.
The technical scheme of the invention is that the substrate-reinforced source region edge P-type heavily-doped anti-radiation NMOS transistor structure (Substrate reinforcement P +edge source NMOS, SRPES-NMOS) is supported on a P-type substrate (108), a channel of the NMOS structure is positioned at the top end of the substrate, a drain region (103) and a source region (106) are arranged at two sides of the length direction of the channel, a gate oxide layer (101) is arranged at the upper part of the channel, and a gate electrode (104) is arranged at the upper part of the gate oxide layer. The drain region (103), the source region (106) and the channel region of the NMOS structure are surrounded by a shallow trench isolation region (102). The semiconductor device is characterized in that the surface of a P-type substrate at the bottom of a shallow trench isolation region of the NMOS is provided with a P-type heavily doped region (107), and the two sides of the width direction of a source region (106) of the NMOS are provided with P-type heavily doped regions (105), as shown in figures 1,2 and 3.
Further, the NMOS substrate reinforcement region (107) may be located in the entire transistor substrate, as shown in fig. 4.
Further, the width of the P-type heavily doped region (105) disposed at two sides of the source region (106) of the NMOS is the minimum line width of the manufacturing process, as shown in fig. 5.
Fig. 6 is a schematic diagram of positive charge accumulated in STI after total dose simulation of transistors using Sentaurus TCAD simulation software. It can be seen that the trapped positive charge not only accumulates at the channel sidewalls, but also at the interface of the STI and the substrate region, which can cause the substrate to invert as well, forming a leakage path.
Compared with the invention of the 'total dose resistant CMOS circuit basic transistor structure', the invention has the advantage of better total dose resistant performance, because the invention not only can block the leakage channel of the side wall of the channel shown in figure 7, but also can solve the problem of inversion of the substrate. Therefore, the invention can enhance the total dose resistance and single particle resistance of the electronic components working in the radiation environment such as aerospace, nuclear field, medical equipment and the like for a long time, and improve the stability and service life of the electronic components working normally in the radiation environment. Fig. 8, 9 and 10 are respectively the change of transfer characteristic curves after total dose simulation of a common NMOS transistor, a source region edge P-type heavily doped transistor and an SRPES-NMOS transistor of the present invention by using sentaurrus TCAD simulation software, and it can be obviously seen that the structure of the present invention has better total dose resistance.
The invention has the advantages that:
first, this region makes the substrate unfavorable for inversion, thereby reducing the leakage current increase caused by the total dose effect;
secondly, the substrate reinforcement region does not affect the concentration of the channel, so that the influence on the normal characteristics of the transistor is very small;
thirdly, as the material of the substrate reinforced region is still Silicon, the difference between the material of the substrate reinforced region and the Silicon material of the adjacent region is only doping concentration difference, the floating potential is not introduced like a Silicon-On-Insulator (SOI) structure formed On an Insulator by adding the region, and the operation of the transistor is more stable;
fourth, the substrate reinforcement structure can reduce the base resistance of the silicon controlled rectifier structure in the PNPN of the four-layer structure in the CMOS circuit, so that the effect of resisting the single event effect can be achieved;
fifth, the structure is very flexible and simple in process implementation, a layer of P-type doped substrate with higher concentration can be grown at the end of growing the epitaxial substrate, and when the STI is formed by etching, higher P-type impurities are injected into the bottom of the trench in an ion injection mode after the inverted trapezoid trench is formed, and then the trench is filled with an insulating medium to form the STI. In any process, it is theoretically unnecessary to increase the number of platemaking, and thus the cost of realizing the structure is very low.
Sixth, compared with the reinforcement structure of the ring gate and semi-ring gate transistor, the structure has the advantages of small occupied area and flexible adjustment of the width-to-length ratio.
Drawings
FIG. 1 is a schematic diagram of a substrate-reinforced source-region-edge P-type heavily doped NMOS transistor according to the present invention
FIG. 2 is a top view of FIG. 1
FIG. 3 is a cross-sectional view taken along the dashed line of FIG. 3
FIG. 4 is another form of substrate reinforcing region
FIG. 5 is a diagram of the minimum line width of the (105) region
FIG. 6 is a schematic diagram of positive charges accumulated in STI after total dose simulation of transistors using Sentaurus TCAD simulation software
FIG. 7 shows the leakage path of the sidewall of the channel due to the total dose effect of the transistor
FIG. 8 shows the transfer characteristic change after total dose irradiation of a common NMOS transistor
FIG. 9 shows the transfer characteristic curve after total dose irradiation of the source region edge P-type heavily doped NMOS transistor
FIG. 10 shows the transfer characteristic change after total dose irradiation of the SRPES-NMOS transistor of the present invention
FIG. 11 example 2 inverter layout constructed with the present invention
Detailed Description
Example 1:
a transfer characteristic curve simulation and result of a substrate reinforced source region edge P type heavily doped NMOS transistor.
This example simulates a substrate-reinforced source-edge P-type heavily doped NMOS transistor as claimed in claim 1, as shown in fig. 1. The width is perpendicular to the transverse direction and the longitudinal direction. The specific structural parameters are as follows, the length of the (108) region is 11 μm, the thickness is 2.8 μm, and the doping concentration is 5×10 15 cm -3 The impurity is boron; (107) The length of the region is 11 μm, the thickness is 0.2 μm, and the doping concentration is 1×10 18 cm -3 The impurity is boron; (102) the thickness of the area is 0.6 mu m, and the material is silicon dioxide; (105) The regions had a length of 0.9 μm, a width of 0.2 μm and a doping concentration of 1X 10 20 cm -3 The impurity is boron; the (103, 106) regions were 0.9 μm in length, 30 μm in width, and 1X 10 in doping concentration 20 cm -3 The impurity is phosphorus; (101) The length of the region is 3 mu m, the width is 30 mu m, the thickness is 5nm, and the material is silicon dioxide; (104) The regions were 0.2 μm thick, 30 μm wide and 3 μm long, as shown in FIG. 1. The transfer characteristic of the total dose simulation is shown in fig. 10. Comparing the normal NMOS transistor of FIG. 8 with the P-type heavily doped NMOS transistor of FIG. 9 at the edge of the source regionThe transfer characteristic curve of the tube after total dose irradiation can be seen that the invention can effectively inhibit the increase of the turn-off current and improve the irradiation resistance of the NMOS device.
Example 2:
the embodiment applies the substrate-reinforced source region edge P-type heavily doped NMOS transistor as claimed in claim 1, wherein the upper tube of the CMOS inverter is a common PMOS, and the lower tube is the SRPES-NMOS. Fig. 11 shows an inverter layout constructed by the invention, and the embodiment can construct a radiation-resistant CMOS basic cell library.
Example 3:
the embodiment applies the substrate-reinforced source region edge P-type heavily doped NMOS transistor as claimed in claim 1, and as shown in FIG. 12, the NMOS cascade structure layout constructed by the invention is shown. In this embodiment, the NMOS near the ground end is the SRPES-NMOS of the present invention, and the source region of the upper tube is shared with the drain region of the lower tube. The upper tube also needs to perform P injection on the surface of the substrate under the STI, so that the anti-radiation effect is enhanced.
Claims (3)
1. A P-type heavily doped radiation-resistant NMOS transistor structure at the edge of a source region reinforced by a substrate is supported on a P-type substrate (108), a channel of the NMOS structure is positioned at the top end of the substrate, a drain region (103) and a source region (106) are arranged on two sides of the length direction of the channel, a gate oxide layer (101) is arranged at the upper part of the channel, and a gate electrode (104) is arranged at the upper part of the gate oxide layer. The drain, source, and channel regions of the NMOS structure are surrounded by shallow trench isolation (Shallow Trench Isolation, STI) regions (102). The semiconductor device is characterized in that the upper surface of a P-type substrate at the bottom of a shallow slot isolation region of the NMOS is provided with a P-type heavy doping region (107), and the two sides of a source region (106) are provided with P-type heavy doping regions (105).
2. A radiation resistant reinforcement structure for NMOS as recited in claim 1; which is characterized in that the (107) region may be present not only in the substrate below the STI region but also in the substrate of the entire transistor, depending on the integrated circuit manufacturing process.
3. A radiation resistant reinforcement structure for NMOS as recited in claim 1; the method is characterized in that the width of the P-type heavily doped region (105) arranged at two sides of the source region (106) of the NMOS can be the minimum line width of the manufacturing process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310298237.1A CN116190353A (en) | 2023-03-24 | 2023-03-24 | Substrate-reinforced source region edge P-type heavily-doped radiation-resistant NMOS transistor structure |
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| CN202310298237.1A CN116190353A (en) | 2023-03-24 | 2023-03-24 | Substrate-reinforced source region edge P-type heavily-doped radiation-resistant NMOS transistor structure |
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