CN116190224A

CN116190224A - Method for manufacturing an anchor element for an electronic device, anchor element and electronic device

Info

Publication number: CN116190224A
Application number: CN202211491542.4A
Authority: CN
Inventors: V·普利西; G·贝洛基; S·拉斯库纳
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2021-11-26
Filing date: 2022-11-25
Publication date: 2023-05-30
Also published as: CN219180514U

Abstract

Embodiments of the present disclosure relate to a method of manufacturing an anchor element of an electronic device, an anchor element, and an electronic device. An electronic device, comprising: a silicon carbide semiconductor body; an insulating layer on a surface of the semiconductor body; a layer of metal material extending partially on a surface of the semiconductor body and partially on the insulating layer; a first SiN interfacial layer on the metal material layer and the insulating layer; a passivation layer on the interface layer; and an anchor element protruding from the passivation layer toward the first insulating layer and extending in the first insulating layer below the interface layer.

Description

Method for manufacturing an anchor element for an electronic device, anchor element and electronic device

Technical Field

The present invention relates to a method of manufacturing an anchor element for an electronic device, an anchor element and an electronic device comprising said anchor element. In particular, the present disclosure relates to an anchoring element designed to improve the reliability of silicon carbide (SiC) electronic power devices, where the conditions of use envisage high voltages and present difficulties in forming trenches.

Background

The semiconductor industry has shown considerable interest in silicon carbide (SiC), particularly for the manufacture of electronic components such as diodes or transistors, especially for power applications.

Electronic devices of various polytypes (e.g., 3C-SiC,4H-SiC, 6H-SiC) formed in silicon carbide substrates have many advantages such as the presence of many advantages such as low on-state output resistance, low leakage current, high operating temperature tolerance and high operating frequency.

However, the development and manufacture of silicon carbide based electronic devices is limited by factors such as the electrical and mechanical properties of passivation layers (included in these electronic devices and extending, for example, over the semiconductor body of silicon carbide of the electronic device). In particular, it is known to manufacture passivation layers using polymeric materials (e.g. polyimide) that enable withstanding high operating temperatures of the electronic device and have high dielectric strength, for example, above 400 kV/mm. In detail, the high dielectric strength of the polymeric material ensures that the passivation layers are subjected to high electric fields and thus to high potential differences across them without undergoing electrical breakdown and thus becoming electrically conductive.

However, polymeric materials have a high Coefficient of Thermal Expansion (CTE) (e.g., cte=43e for the material poly (p-phenylene benzobisoxazole) or PIX ^－6 1/K), and this results in a passivation layer pair having a lower coefficient of thermal expansion (cte=3.8e) ^－6 1/K) adhesion of silicon carbide.

In particular, these problems of adhesion between the passivation layer and the silicon carbide may occur during thermal cycling testing (e.g., conducted between about-50 ℃ and about +150 ℃) or during use of the electronic device when the electronic device is subjected to high thermal swings (e.g., it is subjected to differences in operating temperatures equal to or greater than about 200 ℃). Due to the large difference in CTE between the passivation layer and the silicon carbide, these high thermal swings create mechanical stresses at the interface between the passivation layer and the silicon carbide, which can lead to delamination of the passivation layer (at least in part) with respect to the silicon carbide semiconductor body.

In the case where such delamination is sufficiently large (for example, such that a portion without a passivation layer is interposed between two metallization layers of an electronic device provided at different electric potentials, which are thus separated from each other only by air), a discharge may occur at the interface, resulting in damage to the electronic device itself. In particular, when the electronic device is used under reverse bias conditions, the risk of damage to the electronic device increases due to the high voltage difference to be sustained (for example, higher than 1000V).

Known solutions to this problem include the use of multiple dielectric layers of mutually different materials (e.g., silicon nitride, silicon oxide and polyimide, which are continuous with each other) to form passivation layers designed to limit mechanical stress at the interface with the silicon carbide semiconductor body.

Disclosure of Invention

According to the present disclosure, a method of manufacturing an anchor element of an electronic device, an anchor element, and an electronic device including the anchor element are provided.

For example, in at least one embodiment of the present disclosure, a method of manufacturing an anchor element of a passivation layer of an electronic device includes the steps of: forming a first insulating layer of a first material on a surface of a silicon carbide semiconductor body; forming a metal material layer partially on a surface of the semiconductor body and partially on the first insulating layer; forming an interface layer of a second material different from the first material on the metal material layer and the first insulating layer; removing selective portions of the interfacial layer at a distance from the metallic material layer to form openings through the interfacial layer, thereby exposing the first insulating layer; removing selective portions of the first insulating layer through the openings to form cavities in the first insulating layer at and below the openings, the cavities having at least one dimension in a direction parallel to the surface that is greater than a corresponding dimension of the openings; and simultaneously providing a passivation material on the first insulating layer, in the opening and in the cavity, thereby forming the passivation layer on the first insulating layer, in the opening and on the anchor element in the cavity.

Drawings

For a better understanding of the present disclosure, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

fig. 1 shows in a cross-sectional view an electronic device of a known type;

fig. 2 shows an electronic device in a cross-sectional view according to an embodiment of the present disclosure;

fig. 3A and 3B illustrate, in plan view, the electronic device of fig. 2 in accordance with various embodiments of the present disclosure;

fig. 4 illustrates a portion of an electronic device in a cross-sectional view according to another embodiment of the present disclosure;

5A-5C illustrate in cross-sectional view steps for manufacturing the electronic device of FIG. 2, limited to manufacturing an anchor element, in accordance with embodiments of the present disclosure;

fig. 6 shows an electronic device according to another embodiment of the present disclosure in a cross-sectional view; and

fig. 7A-7D illustrate, in cross-sectional views, steps for manufacturing the electronic device of fig. 6, in accordance with embodiments of the present disclosure and limited to manufacturing the anchor elements.

Detailed Description

Fig. 1 shows in a cross-sectional view of the (triaxial) cartesian reference system of axis X, Y, Z a part of an electronic device (here a JBS or junction barrier schottky diode as an example) 1 which may be of a known type.

The JBS device 1 includes an N-type SiC semiconductor body 3 having a surface 3a opposite to a surface 3 b. The semiconductor body 3 comprises, for example, a substrate and one or more regions of N-type epitaxially grown on the substrate and having corresponding doping concentration values. The JBS device 1 further comprises a plurality of Junction Barrier (JB) elements 9 in the semiconductor body 3 facing the top surface 3a, and each junction barrier element 9 comprises a respective implanted region of P-type in the semiconductor body 3, and an ohmic contact on the implanted region at the level of the top surface 3a of the semiconductor body 3. The JBS device 1 further comprises a first metallization layer 8 extending over the top surface 3a in electrical contact with the junction barrier element 9 through corresponding ohmic contacts. The JBS device 1 further comprises an edge termination area 10 (or guard ring), in particular a P-type implant area, which completely encloses the JB elements 9.

A schottky diode 12 is formed at the interface between the anode metallization 8 and the semiconductor body 3, at which interface a semiconductor-metal schottky junction is formed. The region of MPS device 1 including JB element 9 and schottky diode 12 (i.e., the region contained within guard ring 10) is the active region 4 of JBs device 1.

The JBS device 1 further comprises a second metallization layer 6 extending over the bottom surface 3 b. The first and second metallizations 8,6 form an electrical anode terminal and an electrical cathode terminal, respectively, which may be biased during use of the JBS device 1.

Extending beyond the edge termination region 10 is an electrically inactive region 16.

Extending partially over the edge termination region 10 is an insulating layer 18, which is made of an insulating or dielectric material, in particular silicon oxide (SiO 2).

The first metallization layer 8 is in electrical contact with a portion of the edge termination region 10, wherein the edge termination region 10 is not covered by the insulating layer 18 and also extends partially over the insulating layer 18. An interfacial layer 20, here silicon nitride (SiN), extends over the first metallization layer 8 and the insulating layer 18. Furthermore, the JBS device 1 comprises a passivation layer 22, in particular polyimide, extending over the interface layer 20. In other words, the interfacial layer 20 serves as an interface between the passivation layer 22 and the underlying layers (here the first metallization layer 8 and the insulating layer 18). The interfacial layer 20 may be omitted; however, applicants have found that interfacial layer 20 improves the adhesion of passivation layer 22 to the underlying layers.

A resin protection layer 24 such as bakelite extends over the passivation layer 22, protecting the JBS device 1 when inserted into a package (not shown).

However, although as described above, the interfacial layer 20 improves the adhesion of the passivation layer 22 to the underlying layers, some special conditions of use of the JBS device 1 or thermal or thermo-mechanical testing may cause delamination or partial separation of the passivation layer 22 from the interfacial layer 20 (due to stress generated by the testing). This occurs in particular under stress conditions caused by the high temperatures used (for example, higher than 150 ℃). In addition to making the JBS device 1 structurally fragile, this effect may be the cause of unwanted or unintentional discharge occurrence that affects the electrical operation of the JBS device 1. Indeed, the applicant has found that in some process conditions of thermal mechanical or mechanical stress after the assembly process, the interface layer 20 has one or more localized cracks throughout its thickness, which lead to the generation of these unwanted or unintentional discharges at the first metal layer 8. These problems are all more pronounced when the electronic device 1 is subjected to high thermal swings and high voltage differences under reverse bias conditions.

Therefore, it is necessary to overcome the above-described problems concerning the JBS device 1. These foregoing problems may be addressed by the embodiments of the present disclosure discussed in detail herein.

Fig. 2 illustrates an electronic device 50 according to one aspect of the present disclosure in a cross-sectional side view in the same (triaxial) cartesian reference system of the axis X, Y, Z of fig. 1. In particular, device 50 is a JBS diode, similar to that described with reference to fig. 1. However, the present disclosure is not limited to this device, and may also be applied to other types of electronic devices, particularly power devices, such as MOSFET, IGBT, MPS, schottky diodes, PN diodes, piN diodes, and the like.

The electronic device 50 includes elements described below with reference to fig. 2.

An N-type or P-type silicon carbide semiconductor body 53 (e.g., comprising a substrate 53' and optionally one or more epitaxial layers 53 "grown thereon) (hereinafter, reference will be made to N-type only without limitation) is provided with a front surface 53a opposite a rear surface 53b in the direction of axis Z. In the example shown in fig. 2, the semiconductor body 53 comprises a substrate 53', on which substrate 53' an epitaxial layer 53 "is grown, which epitaxial layer 53" has the function of a drift layer of the electronic device 50, which substrate 53' is of N-type SiC (in particular 4H-SiC, however, other polytypes may be used, such as but not limited to 2H-SiC,3C-SiC and 6H-SiC). For example, the substrate 53' has a thickness of 1 to 10 ¹⁹ at/cm ³ And 1 to 10 ²² at/cm ³ An N-type dopant concentration in between, and having a thickness measured along an axis Z between

surfaces

53a and 53b of between 300 μm and 450 μm, and in particular equal toAbout 360 μm. The drift layer 53 "has a corresponding dopant concentration lower than that of the substrate and a thickness comprised, for example, between 5 μm and 15 μm.

An ohmic contact layer 56, such as nickel silicide, extends on the rear surface 53b and a metallization layer 57, in this example a cathode metallization layer, such as Ti/NiV/Ag or Ti/NiV/Au, extends on the ohmic contact region 56.

One or more P-type doped regions 59' extend in the semiconductor body 53 (in particular in the drift layer), facing the top surface 53a; each doped region 59 'accommodates a respective ohmic contact (not shown and of a known type) such that each doped region 59' forms a respective Junction Barrier (JB) element 59. An edge termination region or guard ring 60, particularly another doped region of the P-type, extends in the drift layer, faces the top surface 53a, and completely encloses (in plan view, in the plane XY defined by axes X and Y) the JB element 59. The edge termination region 60 may be omitted.

An insulating layer 61 (made of insulating or dielectric material, such as silicon oxide or TEOS) extends over the top surface 53a so as to completely surround (as viewed in the XY plane) the JB elements 59 and partially overlap the guard ring 60 (when present).

Metallization 58 (in this example anodic metallization, such as Ti/AlSiCu or Ni/AlSiCu) extends over a portion of the top surface 53a defined externally by insulating layer 61 (i.e., at JB element 59/active region 54) and extends partially over insulating layer 61.

A passivation layer 69 of a polymeric material such as polyamide (e.g., PIX) extends over the anode metallization 58 and over the insulating layer 61.

An interfacial layer 63, here silicon nitride (SiN), extends over the anode metallization 58 and over the insulating layer 61 and under the passivation layer 69. In other words, interface layer 63 serves as an interface between passivation layer 69 and the underlying layers (here, metallization layer 58 and insulating layer 61) and facilitates adhesion of the overlying passivation layer 69.

One or more schottky diodes 62 are formed at the interface between the semiconductor body 53 and the anode metallization 58, and the schottky diodes 62 are transverse to the doped region 59'. In particular, the (semiconductor-metal) schottky junction is formed by a portion of the semiconductor layer 53 that is in direct electrical contact with a corresponding portion of the anode metallization 58.

Furthermore, each ohmic contact extending in a respective doped region 59 'provides an electrical connection having a resistivity value lower than that of the doped region 59' in which it is accommodated. Thus, JB element 59 is a P-i-N diode.

The region of the electronic device 50 that includes the JB element 59 and the schottky diode 62 (i.e., the region bounded by the guard ring 60) is the active region 54 of the electronic device 50.

Present outside the active region 54, i.e. outside the edge termination region 60, is a side surface 53c of the semiconductor body 53, for example extending substantially perpendicular to the top surface 53 a. The side surface 53c is formed after the dicing or dividing step of the silicon carbide wafer in which the plurality of electronic devices 50 are obtained. The dicing step has the function of separating one electronic device 50 from another device 50 of the same wafer. Dicing is performed at scribe lines (not shown) of the silicon carbide wafer from which the electronic device 50 is obtained. The scribe line surrounds the active region 54, guard ring 60 and insulating layer 61 at a distance in plane XY.

A resin protective layer 74, such as bakelite (bakelite), extends over passivation layer 69 to protect electronic device 50 when inserted into a package (not shown).

According to one aspect of the present disclosure, the passivation layer 69 has an anchoring element 82, which anchoring element 82 protrudes from the passivation layer 69 (in particular in the direction of the axis Z) and extends in the insulating layer 61 until it reaches the top surface 53a of the semiconductor body 53. The anchor elements 82 anchor and fix the passivation layer 69 to the insulating layer 61. The anchoring elements 82 are integral with the passivation layer 69 and in particular an extension of the passivation layer itself. Thus, the anchor element 82 extends from the passivation layer without interruption and without an interface, and is of the same material as the passivation layer. In other words, the anchor element 82 and the passivation layer 69 form a single or unitary body.

The anchor elements 82 extend through openings 84 formed through the interface layer 63. The opening 84 has a shape selected freely at the design stage, such as a circle, ellipse or polygon, a diameter d ₁ Several micrometers, for example between 2 and 5 μm.

The anchoring elements 82 are formed outside the active region 54, in particular outside the edge termination region 60; in other words, the anchor element 82 is interposed between the edge termination area 60 and the side surface 53 c. In the absence of the edge termination region 60, the anchor element 82 is formed outside the active region 54, i.e., between the active region 54 and the side surface 53c in the electrically inactive region of the device.

The anchor elements 82 are patterned to secure the passivation layer 69 to the insulating layer 61 and are designed to prevent and/or inhibit delamination and/or separation of the passivation layer 69.

In particular, the anchor elements 82 are received and arranged to be slotted into a housing or cavity extending in the insulating layer 61 so as to couple the passivation layer 69 and the insulating layer 61 together and to integrate them with each other. The cavity that receives the anchor element 82 has a shape that is complementary to the shape of the anchor element 82. In other words, the anchoring element 82 completely fills the cavity in which it is housed.

In one embodiment, in the cross-sectional view of fig. 2 and measured along axis X, the anchor element 82 has a dimension that increases with increasing distance (along axis Z) from the passivation layer 69.

In various embodiments, in the cross-sectional view of fig. 2 and measured along axis X, the anchor element 82 has a first dimension at the opening 84; a first dimension and the diameter d of the opening 84 ₁ And consistent. Furthermore, the anchoring element 82 has a second dimension measured along the axis X within the insulating layer 61 in the cross-sectional view of fig. 2. The second dimension is greater than the first dimension (e.g., without limitation, twice as large, i.e., 2d ₁ ). Within the insulating layer 61, the anchoring elements 82 may have any geometry chosen at the stage of design, the dimensions of which (again considered in the section of fig. 2 and measured along the axis X) are variable, but in any case are greater than the aforesaid first dimension d at the openings 84 ₁ 。

Obviously, within insulating layer 61, anchoring element 82 may have, in addition to or as an alternative to the dimensions described above with respect to the dimensions along X, another dimension measured along axis Y that is greater than the corresponding dimension of opening 84 (again measured along axis Y).

In this way, since the anchoring element 82 extends below the opening 84 and has at least one dimension in the plane XY that is greater than the corresponding dimension of the opening 84 in the plane XY, the anchoring element 82 has the purpose of fixing the passivation layer 69, the passivation layer 69 being therefore constrained in its movement along the axis Z, preventing any delamination or separation.

In another embodiment, within the insulating layer 61, the anchoring elements 82 may have locally a size equal to or smaller than the first size described above, but in any case have at least one portion with a size greater than the first size described above.

In the example of fig. 2, the portion of the anchoring element 82 extending within the insulating layer 61 (in a cross-sectional view and along the axis X) has a trapezoidal shape, with the primary side directly facing the interface layer 63 and the secondary side in contact with the top surface 53a of the semiconductor body. In a further embodiment, not shown, the portion of the anchoring element 82 extending within the insulating layer 61 has (in a cross-section and along the axis X) a rectangular or substantially polygonal shape, or an elliptical shape, or a substantially curved or curvilinear shape.

According to another embodiment, the anchoring elements 82 do not extend through the insulating layer 61 over the entire thickness of the insulating layer 61, but end within the insulating layer 61 at a distance from the top surface 53a of the semiconductor body. Also in this case, the shape and size may be selected similarly to those described previously.

Fig. 3A and 3B schematically illustrate a top view (in plane XY) of an electronic device 50 according to various embodiments.

Referring to fig. 3A, the anchor elements 82 extend in the plane XY so as to completely surround the anodic metallization 58. In the view in plane XY of fig. 3A, the anchoring elements 82 are annular and define a closed polygonal shape, and in more detail define a square shape with rounded corners (even different shapes are possible, such as a circular shape, a rectangular shape or a general polygonal or irregular shape). As shown in fig. 3A, the anchor element 82 is a continuous, unitary layer of material that extends continuously around the anode metallization 58 and, as described above, has a closed polygonal shape.

Referring to fig. 3B, the electronic device 50 includes a plurality of anchor elements (all of which are similar to the anchor elements 82 described previously and therefore are designated by the same reference numerals). The anchors 82 extend at a distance from each other at the top surface 53a and at a distance from each other at respective portions of the top surface 53 a. For example, the view in plane XY of fig. 3B shows four anchor elements 82 that are separate, distinct and discrete from each other, arranged around anode metallization 58 so as to be separated by equal angular distances with respect to anode metallization 58, and arranged in more detail at corners of an ideal square geometry. However, other arrangements of different numbers of anchor elements are also possible (e.g., four discrete anchor elements along the sides of the ideal square geometry, three discrete anchor elements along the corners and sides of the ideal square geometry, or one or more anchor elements may be arranged in different configurations or arrangements).

Although not shown in fig. 3A and 3B, in some embodiments, the plurality of anchor elements 82 may be separate, distinct, and discrete anchor elements that are circular in shape disposed about the anode metallization 58. These separate, distinct and discrete anchor elements 82 may be similar or analogous points depicted along a geometric shape (e.g., square, circular, etc.), which may be an ideal square geometric shape as described above.

It will be apparent that in an alternative embodiment to the embodiment shown in fig. 2, two or more anchors 82 may be provided alongside one another. For example, as shown in fig. 4 (in which only a portion of an electronic device similar to electronic device 50 is shown), two anchoring elements 82 extend in insulating layer 61 along axis X at a mutual distance from each other equal to a few micrometers or tens of micrometers, for example between 5 μm and 20 μm. One, some or all of the plurality of anchor elements 82 extend through the thickness of insulating layer 61 (along Z) within insulating layer 61, or extend only partially within insulating layer 61, terminating at insulating layer 61 without reaching top surface 53a.

The steps for manufacturing the electronic device 50 of fig. 2 (similarly applicable to the embodiment of fig. 4) are described below with reference to fig. 5A-5C, and are limited to the steps for forming the anchor elements 82. Fig. 5A-5C illustrate the same triaxial system as fig. 2.

Referring to fig. 5A, a wafer comprising a silicon carbide semiconductor body 53 is provided, with subsequent fabrication steps designed to form the elements of the electronic device 50 previously described (and not further discussed herein) and identified by the same reference numerals.

Interfacial layer 63 is selectively etched to form openings 84. For this purpose, for example, a photoresist or an etching mask is provided and the openings 84 having the aforementioned shape, size and position are formed by means of photolithography and etching steps known per se. Openings 84 extend through interface layer 63 throughout the entire thickness of interface layer 63 exposing corresponding surface portions of insulating layer 61.

Next, in fig. 5B, etching of the insulating layer 61 is performed through the opening 84 formed previously. The etching is, for example, wet and can be performed without the presence of a further etching mask if an etching chemistry is used which is selective with respect to the material of the insulating layer 61 (e.g. hydrofluoric acid in the case of silicon oxide), which thus does not remove the interface layer 63. In this case, the interface layer 63 forms an etching mask. Otherwise, a mask similar to the step for forming the opening 84 may be used.

The etching of the insulating layer 61 is of the isotropic type and the material of the insulating layer is removed vertically (along Z) and horizontally (in plane XY) below the interface layer 63. The etching is, for example, a timing etching, and is interrupted according to the type of shape desired to be imparted to the anchor member 82. In the embodiment of fig. 5B, etching is performed until the top surface 53a of the semiconductor body 53 is exposed. As described above, etching also proceeds laterally (along axis X). Thus forming a cavity 86 in the insulating layer 61.

Then, in fig. 5C, a passivation layer 69 is formed. A liquid or semi-liquid polymeric material is applied to the wafer and is distributed by rotation over interface layer 63. During this process, the polymeric material passes through the opening 84 and completely fills the cavity 86 and the opening 84. A heat treatment is then performed until the polymer material hardens to form the passivation layer 69 (curing treatment) and simultaneously the anchor elements 82 are formed. The polymeric material is, for example, polyimide (polyimide).

The fabrication process then continues with subsequent steps to form other elements of the electronic device 50, which are not described in detail herein (e.g., the ohmic contact layer 56 and the cathode metallization 57).

Fig. 6 shows an electronic device 100 according to another embodiment of the present disclosure. The electronic device 100 is represented in the same (triaxial) cartesian reference system of the axis X, Y, Z of fig. 1 and 2. In particular, the electronic device 100 is a JBS diode similar to that described with reference to fig. 1 and 2. However, also in this case, the present disclosure is not limited to JBS devices, and may also be applied to other types of electronic devices, particularly power devices, such as MOSFET, IGBT, MPS, schottky diodes, PN diodes, piN diodes, and the like.

Elements of the electronic device 100 that are identical to the electronic device 50 of fig. 2 are denoted by the same reference numerals and will not be further described.

In particular, in addition to the electronic device 50 already described, the electronic device 100 comprises a further insulating layer 102, in particular a dielectric or insulating material, such as silicon oxide. In particular, the material of the insulating layer 102 is the same as that used for the insulating layer 61. For example, the thickness of the insulating layer 102 along the axis Z is between 0.5 μm and 2 μm.

Insulating layer 102 extends laterally over anode metallization 58 and insulating layer 61 to anode metallization 58.

Interfacial layer 63 is optional and extends over insulating layer 102 if present; passivation layer 69 extends over and contacts interface layer 63 (if present); alternatively, passivation layer 69 extends over and contacts insulating layer 102.

According to the embodiment of fig. 6, the passivation layer 69 has an anchoring element 82 (in particular, in the direction of the axis Z) protruding from the passivation layer 69, similar to the embodiment of fig. 2. In this case, however, the anchor element 82 extends completely within the insulating layer 102 (i.e. over the entire thickness along the Z of the insulating layer 102) and only partially within the insulating layer 61 (ending in the insulating layer 61) without reaching the top surface 53a of the semiconductor body 53. The anchor elements 82 anchor and fix the passivation layer 69 to both the insulating layer 102 and the insulating layer 61. The anchoring elements 82 are integral with the passivation layer 69, in particular an extension of the passivation layer itself. Thus, the anchor element 82 extends from the passivation layer without interruption and without an interface, and is of the same material as the passivation layer. In other words, the anchor element 82 and the passivation layer 69 form a single or unitary body.

In the presence of interface layer 63, anchor element 82 extends through opening 84 formed through interface layer 63. The opening 84 has a shape selected freely at the design stage, such as a circle, ellipse or polygon, a diameter d ₁ Equal to a few micrometers, for example between 2 and 5 μm.

The anchor elements 82 are formed outside the active region 54, in particular outside the edge termination region 60, and at a distance from the anode metallization 58. In other words, the anchor element 82 is interposed between the edge termination area 60 and the side surface 53 c. In the absence of the edge termination region 60, the anchor element 82 is formed outside the active region 54, i.e., between the active region 54 and the side surface 53c in the electrically inactive region of the device, and at a distance from the anode metallization 58.

In particular, the anchor elements 82 are received and arranged to slot into a housing or cavity extending in the insulating

layers

102 and 61 so as to connect the passivation layer 69 and the insulating

layers

102 and 61 together and to integrate them with each other. The cavity that receives the anchor element 82 has a shape that is complementary to the shape of the anchor element 82. In other words, the anchoring element 82 completely fills the cavity in which it is housed.

The anchoring elements 82 have the dimensions already discussed with reference to fig. 2 and are not repeated here for the sake of brevity.

According to a further embodiment, not shown, the anchoring elements 82 extend only (partially or completely) in the insulating layer 102 (thus ending within the insulating layer 102 or at the interface between the insulating layer 102 and the underlying insulating layer 61).

According to another embodiment (not shown), the anchor elements 82 extend completely through the thickness of the insulating layer 102 and completely through the thickness of the insulating layer 61.

According to another embodiment, not shown, there may be a plurality of anchoring elements 82, similar to that described with reference to fig. 4. One, some or all of the plurality of anchor elements 82 extend only within insulating layer 102 (and not insulating layer 61), or extend throughout the thickness of insulating layer 102, or extend throughout the thickness of insulating layer 61, or extend throughout the thickness of insulating layer 102, and extend partially within insulating layer 61.

In the embodiment of fig. 6, insulating layer 102 has the function of forming another interface between interface layer 63 and anode metallization 58 to obtain electrical insulation at anode metallization 58 in the event of a rupture of interface layer 63.

Fig. 7A-7D illustrate steps for manufacturing the electronic device 100 of fig. 6, which are limited to steps for forming the anchor elements 82. Fig. 7A-7D illustrate the same triaxial system as fig. 6.

Referring to fig. 7A, a wafer comprising a silicon carbide semiconductor body 53 is provided, followed by fabrication steps (not further discussed herein) designed to form the elements of the aforementioned electronic device 100, and designated by the same reference numerals.

Referring to fig. 7A, after forming the insulating layer 61 and the anodic metallization, a step of depositing an insulating or dielectric material is performed to form the insulating layer 102. This step is performed, for example, by a CVD process. An insulating layer 102 is formed over the entire surface of the wafer, particularly completely covering the anode metallization 50 and the insulating layer 61.

Then, after the insulating layer 102 is formed, an interface layer 63 is formed, for example, by depositing CVD-type silicon nitride. The interfacial layer 63 is formed on the entire surface of the wafer, and in particular, entirely covers the insulating layer 102.

Then, in fig. 7B, interfacial layer 63 is selectively etched to form openings 84. For this purpose, for example, a photoresist mask is provided and the openings 84 having the aforementioned shape, size and position are formed by means of photolithography and etching steps known per se. Openings 84 extend through interface layer 63 through the entire thickness of interface layer 63, exposing corresponding surface portions of insulating layer 102.

Then, in fig. 7C, etching of the insulating layer 102 is performed through the opening 84 formed previously. The etching is, for example, wet and can be performed without a mask if an etching chemistry is used that is selective with respect to the material of the insulating layer 102 (e.g., hydrofluoric acid in the case of silicon oxide), which thus does not remove the interface layer 63. Otherwise, a mask similar to the step for forming the opening 84 may be used.

The etching of the insulating layer 102 is of an isotropic type and below the interface layer 63, the material of the insulating layer 102 is removed vertically (along Z) and horizontally (in plane XY). For example, the etching is a timed etching selected according to the type of shape desired to be imparted to the anchor element 82. In the embodiment of fig. 7C, etching is performed until insulating layer 102 is completely removed, and also partial removal of the material of underlying insulating layer 61 is performed. If the materials of insulating layer 102 and insulating layer 61 can be etched using the same etching chemistry, portions of insulating layer 102 and insulating layer 61 are removed during the same etching step; otherwise, after removing the desired portion of insulating layer 102, the etching chemistry is changed to remove the desired portion of insulating layer 61. As described above, etching is also performed laterally (along the axis X) in the insulating layer 102 and the insulating layer 61. Thus forming cavities 86 in insulating

layers

102 and 61.

Then, as shown in fig. 7D, a passivation layer 69 is formed. A liquid or semi-liquid polymeric material is applied to the wafer and is distributed by rotation over interface layer 63. During this process, the polymeric material passes through the opening 84 and completely fills the cavity 86 and the opening 84. A thermal process is then performed such that the polymer material is hardened to form the passivation layer 69 (curing process) and simultaneously the anchor elements 82 are formed. The polymeric material is, for example, polyimide.

The fabrication process then continues with subsequent steps to form other elements of the electronic device 100, which are not described in detail herein (e.g., the ohmic contact layer 56 and the cathode metallization 57).

The advantages that it allows to obtain are evident from a review of the features according to the present disclosure.

In particular, the anchor elements 82 ensure adhesion of the passivation layer 69, preventing delamination. Thus, the passivation layer 69 may be obtained using a polymer material, thereby ensuring high electrical performance of the electronic device 50, 100 (due to the high dielectric strength of the passivation layer 69) and at the same time eliminating structural problems associated with possible separation of the passivation layer 69 (e.g. after thermal cycling or use of the electronic device 50, 100).

Thus, the risk of damaging the

electronic device

50, 100 after discharge between metallizations provided at different potentials (e.g., between an equipotential ring or EQR metallization and the anode metallization 58) is prevented, and thus the reliability of the

electronic device

50, 100 increases, especially when it is subjected to high thermal swings and operates under reverse bias conditions.

The manufacturing steps described with reference to fig. 5A-5C and 7A-7D make it possible to obtain, starting from a silicon carbide wafer, respectively,

electronic devices

50 and 100 comprising corresponding anchor elements 82. The etching performed with reference to fig. 5B-5C and 7B-7D is of the isotropic type and this allows to pattern the cavities thus formed and thus the anchor elements 82 without limitations deriving from the anisotropic etching process or from the crystal orientation of the silicon carbide wafer from which the

electronic device

50, 100 is obtained.

Finally, it is clear that modifications and variations may be made to the present disclosure described and illustrated herein without departing from the scope of the present disclosure as defined in the appended claims.

A method of manufacturing an anchor element (82) of a passivation layer (69) of an electronic device (50); 100 Can be summarized as comprising the steps of: forming a first insulating layer (61) of a first material on a surface (53 a) of a silicon carbide semiconductor body (53); -forming a layer of metallic material (58) partly on the surface (53 a) of the semiconductor body (53) and partly on the first insulating layer (61); -forming an interface layer (63) of a second material different from the first material on the layer of metallic material (58) and the first insulating layer (61); -removing selective portions of the interfacial layer (63) at a distance from the layer of metal material (58) to form openings (84) through the interfacial layer (63) to expose the first insulating layer (61); removing selective portions of the first insulating layer (61) through the opening (84) to provide openings in the first insulating layer (61)84 At) a cavity (86), the cavity (86) having at least one dimension (d) in a direction parallel to the surface (53 a) that is larger than a corresponding dimension of the opening (84) ₁ ) The method comprises the steps of carrying out a first treatment on the surface of the And simultaneously providing a passivation material in the opening (84) and in the cavity (86) on the first insulating layer (61), thereby forming the passivation layer (69) on the first insulating layer (61), and providing the anchor element (82) in the opening (84) and in the cavity (86).

The step of providing the passivation material may include providing the passivation material in a liquid or semi-liquid form such that the passivation material fills the cavity (86).

The step of providing the passivation material may include performing a rotation step of the passivation material.

The method of manufacturing may further comprise the step of curing or hardening the passivation material such that the anchor element (82) and the passivation layer (69) form a single body or sheet.

Removing the selective portion of the first insulating layer (61) may include performing an isotropic etch of the first insulating layer (61).

The interfacial layer (63) may be configured to facilitate adhesion of the passivation layer (69) to the insulating layer (61).

Forming the anchor element (82) in the opening (84) and the cavity (86) may include confining the anchor element (82) under the interface layer (63) and within the first insulating layer (61).

Forming the opening (84) may include forming an etch mask for the first insulating layer (61); the step of removing selected portions of the first insulating layer (61) through the openings (84) comprises performing a wet etch of the first insulating layer (61).

The volume of the cavity (86) may be greater than the volume of the opening (84).

The passivation material (69) may include a polymeric material.

The material of the interfacial layer may be silicon nitride.

The step of forming the cavity (86) may include forming the cavity (86) over the entire thickness of the first insulating layer (61); or a cavity (86) is formed through a part of the thickness of the first insulating layer (61), ending inside the first insulating layer (61).

The method of manufacturing may further comprise the step of forming a second insulating layer (102) on the first insulating layer (61) and on the metal material layer (58) below the interface layer (63).

The step of forming the cavity (86) may further include forming the cavity (86) only in the second insulating layer (102); or forming a cavity (86) completely through the second insulating layer (102) and partially through the first insulating layer (61), ending in the first insulating layer (61); or forming a cavity (86) completely through the second insulating layer (102) and the first insulating layer (61).

The second insulating layer (102) may be the same material as the first insulating layer (61).

The anchor element (82) may be formed in an electrically inactive region of the electronic device at a distance from the layer of metallic material (58).

An anchor element (82) of a passivation layer (69) of the electronic device (50); 100 Can be summarized as comprising a layer extending completely through the interface layer (63) starting from the passivation layer (69) and at least partially through the insulating structure (61; the protrusions terminate within the insulating structure underneath the interfacial layer (63) on the surface (53 a) of the silicon carbide semiconductor body (53) and form a single body or monolithic body with the passivation layer (69).

The anchoring element may comprise a first portion extending in the interface layer (63) from the surface (53 a) at a first distance and parallel to said surface (53 a) in parallel to a first axis (X; Y), the maximum dimension having a first value (d ₁ ) The method comprises the steps of carrying out a first treatment on the surface of the And a second portion extending in a structural continuation of the first portion in the insulating structure and having, in a direction parallel to the first axis (X): y) has a value greater than the first value (d ₁ ) A corresponding maximum size of the second value of (a).

The second portion of the anchoring element may extend partially inside the insulating structure (61, 102) or completely through the insulating structure (61, 102).

The passivation material (69) may include a polymeric material.

The anchor element (82) may extend in an electrically inactive region of the electronic device (50; 100).

An electronic device (50; 100), possibly summarised as a semiconductor body (53) comprising silicon carbide; a first insulating layer (61), a first material on a surface (53 a) of the semiconductor body (53), a metal material layer (58) extending partly on the surface (53 a) of the semiconductor body (53) and partly on the first insulating layer (61), an interface layer (63) on the first insulating layer (61) and the metal material layer (58), the interface layer (63) being composed of a second material different from the first material, a passivation layer (69) on the interface layer (63), and an anchor element (82) protruding from the passivation layer (69) towards the first insulating layer (61) and extending completely through an opening (84) of the interface layer (63) and ending at the first insulating layer (61), the anchor element (82) having at least one dimension (d) in a direction parallel to the surface (53 a) which is larger than the corresponding dimension of the opening (84) ₁ )。

The anchor element (82) and the passivation layer (69) may form a single body or monolithic body.

The anchor element (82) may be configured to confine the passivation layer (69) under the interface layer (63) and within the first insulating layer (61).

The anchoring element (82) may comprise a first portion extending in the insulating structure from the surface (53 a) by a first distance and parallel to said surface (53 a) in parallel to a first axis (X; Y), the maximum dimension having a first value (d ₁ ) The method comprises the steps of carrying out a first treatment on the surface of the And a second portion extending in a structural continuation of the first portion in the insulating structure and having, in a direction parallel to the first axis (X): y) has a value greater than the first value (d ₁ ) A corresponding maximum size of the second value of (a).

The passivation material (69) may include a polymeric material.

The material of the interfacial layer (63) may be silicon nitride.

The anchor element (82) may extend throughout the thickness of the interface layer (63) and the first insulating layer (61); or through a portion of the thickness of the interface layer (63) and the thickness of the first insulating layer (61), terminates within the first insulating layer (61).

The electronic device may further include a second insulating layer (102) on the first insulating layer (61) and the metallic material layer (58).

The anchor element (82) may extend throughout the thickness of the interface layer (63) and: terminating within the second insulating layer (102) in the second insulating layer (102); or completely through the second insulating layer (102) and partially in the first insulating layer (61), ending within the first insulating layer (61); or completely through the second insulating layer (102) and the first insulating layer (61) at the surface (53 a) of the semiconductor body (53).

The anchoring element (82) may be on the electronic device (50; 100).

The electronic devices selected in the group may include schottky diodes, pin diodes, PN diodes, MPS devices, JBS diodes, MOSFETs, IGBTs or power devices.

The various embodiments described above may be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A method, comprising:

forming a first insulating layer of a first material on a surface of a silicon carbide semiconductor body;

forming a layer of conductive material partially on the surface of the semiconductor body and partially on the first insulating layer;

forming an interface layer of a second material different from the first material on the conductive material layer and the first insulating layer;

removing a selective portion of the interfacial layer at a distance from the metal material layer, forming an opening extending through the interfacial layer, and exposing the first insulating layer with the opening;

removing a selective portion of the first insulating layer through the opening to form a cavity in the first insulating layer at and below the opening, the cavity having at least one dimension in a direction parallel to the surface that is greater than a corresponding dimension of the opening in the direction; and

on the first insulating layer, a passivation material is formed in the opening and in the cavity, the passivation material forming a passivation layer on the first insulating layer and an anchor element in the opening and in the cavity.

2. The method of claim 1, further comprising curing the passivation material such that the anchor element and the passivation layer are integral.

3. The method of claim 1, wherein removing the selective portion of the first insulating layer comprises performing an isotropic etch on the first insulating layer.

4. The method of claim 1, wherein the interface layer couples the passivation layer to the insulating layer and the interface layer is configured to facilitate adhesion of the passivation layer to the insulating layer.

5. The method of manufacturing of claim 1, wherein forming the anchor element in the opening and in the cavity comprises confining the anchor element below the interface layer and within the first insulating layer.

6. The manufacturing method according to claim 1, wherein forming the opening includes forming an etching mask for the first insulating layer;

removing the selective portion of the first insulating layer through the opening includes performing a wet etch of the first insulating layer.

7. The method of claim 1, wherein forming the cavity comprises:

the cavity is formed over the entire thickness of the first insulating layer.

8. The method of claim 1, wherein forming the cavity comprises forming the cavity through a partial thickness of the first insulating layer, terminating inside the first insulating layer before reaching the surface of the semiconductor body.

9. The method of claim 1, further comprising forming a second insulating layer over the first insulating layer and over the metal material layer, and wherein forming the interface layer further comprises forming the interface layer over the second insulating layer and covering the second insulating layer.

10. The method of claim 9, wherein forming the cavity further comprises forming the cavity only in the second insulating layer.

11. The method of claim 9, wherein forming the cavity further comprises forming the cavity to pass entirely through the second insulating layer and to pass partially through the first insulating layer to terminate within the first insulating layer.

12. The method of claim 9, wherein forming the cavity further comprises forming the cavity completely through the second insulating layer and the first insulating layer.

13. The manufacturing method according to claim 9, wherein the second insulating layer has the same material as the first insulating layer.

14. A device, comprising:

a silicon carbide semiconductor body comprising a surface;

an insulating structure on the surface of the semiconductor body;

an interfacial layer on the insulating structure;

a passivation layer on the interfacial layer, the passivation layer having an anchor element, the anchor element comprising:

a protrusion extending completely through the interface layer from the passivation layer and at least partially through the insulating structure, the protrusion ending within the insulating structure before reaching the surface of the semiconductor body and having a monolithic body with the passivation layer.

15. The anchor element of claim 14, comprising:

a first portion extending in the interface layer at a first distance from the surface and having a maximum dimension in a direction parallel to a first axis, the first axis being parallel to the surface and the maximum dimension having a first value; and

a second portion extending in the insulation structure in a structural continuation of the first portion and having a respective maximum dimension in a direction parallel to the first axis, the respective maximum dimension having a second value greater than the first value.

16. The anchor element of claim 15, wherein the second portion of the anchor element extends partially into or completely through the insulating structure.

17. A device, comprising:

a silicon carbide semiconductor body comprising a surface;

a first insulating layer of a first material on the surface of the semiconductor body;

a layer of metal material extending partially on the surface of the semiconductor body and partially on the first insulating layer;

an interface layer on the first insulating layer and on the metal material layer, the interface layer being made of a second material different from the first material;

a passivation layer on the interface layer; and

an anchor element of the passivation layer protruding towards the first insulating layer and extending completely through the opening of the interface layer and ending in the first insulating layer, the anchor element having at least one dimension in a direction parallel to the surface, the at least one dimension being larger than a corresponding dimension of the opening.

18. The electronic device of claim 17, wherein the interface layer couples the passivation layer to the insulating layer and is configured to facilitate adhesion of the passivation layer to the insulating layer.

19. The electronic device of claim 17, wherein the anchor element extends entirely through a first thickness of the interface layer and a second thickness of the first insulating layer.

20. The device of claim 17, wherein the anchor element extends through a portion of the first thickness of the interfacial layer and the second thickness of the first insulating layer, and the anchor element terminates within the first insulating layer before reaching the surface of the semiconductor body.