CN116190203A

CN116190203A - Semiconductor substrate, semiconductor device and manufacturing method

Info

Publication number: CN116190203A
Application number: CN202211425086.3A
Authority: CN
Inventors: 黄�俊; 杨冰
Original assignee: Hubei Jiufengshan Laboratory
Current assignee: Hubei Jiufengshan Laboratory
Priority date: 2022-11-15
Filing date: 2022-11-15
Publication date: 2023-05-30

Abstract

The application discloses a semiconductor substrate, a semiconductor device and a manufacturing method, wherein the manufacturing method of the semiconductor substrate comprises the following steps: providing an SOI substrate comprising: a first insulating layer; at least one monocrystalline silicon block located on the first insulating layer; a second insulating layer covering the monocrystalline silicon block and the first insulating layer around the monocrystalline silicon block; the single crystal silicon block has opposite first and second ends in a direction parallel to the SOI substrate; forming a first window on the second insulating layer to expose a part of the monocrystalline silicon block corresponding to the first end; forming a nucleation block based on the monocrystalline silicon block exposed by the first window; forming a second window penetrating through the second insulating layer to expose a part of the monocrystalline silicon block corresponding to the second end; removing the monocrystalline silicon block based on the second window to form a gap structure between the first insulating layer and the second insulating layer; based on the nucleation blocks, a GaN layer is selectively laterally epitaxially grown within the gap structure.

Description

Semiconductor substrate, semiconductor device and manufacturing method

Technical Field

The present disclosure relates to the field of semiconductor devices, and more particularly, to a semiconductor substrate, a semiconductor device, and a method of manufacturing the semiconductor substrate.

Background

As integrated circuit transistor densities approach physical limits, it has become increasingly difficult to rely on improved processes to improve integrated circuit performance. Around the information industry of the "post-molar age", the semiconductor field is striving to find new solutions. Among them, silicon phototechnology is considered as one of the development directions capable of continuing moore's law.

Silicon photonics is a low cost, high speed photonic integrated circuit technology based on silicon (Si) photonics. The method combines the characteristics of ultra-large scale and ultra-high precision manufacturing of a silicon CMOS microelectronic process with the advantages of ultra-high speed and ultra-low power consumption of a photon technology, integrates numerous originally separated optical and electrical devices into a single microchip, and realizes various emerging applications including high-performance calculation, automobiles, quantum communication, optical sensing and the like.

However, because group IV materials (silicon, germanium, etc.) are indirect bandgap structures, silicon photonics generally requires an integrated III-V laser as a light source. Therefore, over the last few decades, the integration of III-V materials on silicon has been pursued with little cumin. While high quality of III-V materials can be maintained, heterogeneous integrated III-V lasers on silicon using bonding or transfer printing have reached the commercialization stage, but also suffer from the disadvantages of high cost and low yield.

Although the III-V material is monolithically integrated on the silicon wafer by direct heteroepitaxy, the method has more cost advantage when facing mass production, and is an ideal technical scheme for solving the silicon-based photoelectric integrated light source, the crystal quality problem of the direct heteroepitaxy III-V material is required to be solved. While great progress is currently made in directly epitaxially III-V lasers on Si substrates, epitaxial III-V materials on silicon still exhibit high defect densities, with defect densities greater than 10 ⁸ ～10 ⁹ cm ^-2 。

The fully integrated silicon chip requires a monolithic III-V/Si substrate that can achieve a tight layout of III-V materials and Si to ensure efficient integration; low defect III-V materials can be realized to ensure high performance of the device; larger size III-V materials can be implemented to ensure flexible device design.

Integration of III-V materials with Si various discrete III-V devices can be integrated onto Si wafers, thus on the one hand to be compatible with CMOS processes, reducing the processing costs of electronics and circuitry, and on the other hand to achieve higher density integration with selective epitaxy and CMOS processes.

Disclosure of Invention

In view of this, the present application provides a semiconductor substrate, a semiconductor device and a manufacturing method, and the scheme is as follows:

a method of fabricating a semiconductor substrate, the method comprising:

providing an SOI substrate, the SOI substrate comprising: a first insulating layer; at least one monocrystalline silicon block located on the first insulating layer; the second insulating layer covers the monocrystalline silicon block and the first insulating layer around the monocrystalline silicon block; the single crystal silicon block has opposite first and second ends in a direction parallel to the SOI substrate;

forming a first window on the second insulating layer to expose a part of the monocrystalline silicon block corresponding to the first end;

forming a nucleation block based on the monocrystalline silicon block exposed by the first window;

forming a second window penetrating through the second insulating layer, and exposing a part of the monocrystalline silicon block corresponding to the second end;

removing the monocrystalline silicon block based on the second window to form a gap structure between the first insulating layer and the second insulating layer;

based on the nucleation blocks, a GaN layer is selectively laterally epitaxially grown within the gap structure.

Preferably, in the above manufacturing method, the nucleation block is an AlN block, and a surface of the monocrystalline silicon block facing the second insulating layer is a (111) crystal plane of monocrystalline Si.

Preferably, in the above manufacturing method, the method for forming the nucleation block includes:

forming a nucleation layer, wherein the nucleation layer at least fills part of the first window and covers the surface of one side of the second insulating layer, which is away from the first insulating layer;

and removing the nucleation layer on the surface of the second insulating layer, and reserving the nucleation layer in the first window to form the nucleation block.

Preferably, in the above manufacturing method, the method for forming the second window includes:

etching the second insulating layer based on a photoetching process to form the second window;

and over-etching the second insulating layer to increase the surface roughness of the monocrystalline silicon block exposed by the second window.

Preferably, in the above manufacturing method, the single crystal silicon block is rectangular; the first window and the second window are correspondingly arranged on two opposite side edges of the rectangle respectively, and the second insulating layer outside the other two opposite side edges of the rectangle is in contact with the first insulating layer to serve as a supporting structure of the gap structure.

Preferably, in the above manufacturing method, there are a plurality of the single crystal silicon blocks, and the second insulating layer is in contact with the first insulating layer between two adjacent single crystal silicon blocks.

Preferably, in the above manufacturing method, the thickness of the single crystal silicon block is in the range of 100nm to 900nm.

The application also provides a manufacturing method of the semiconductor device, which comprises the following steps:

providing a semiconductor substrate prepared by any one of the above methods of fabrication;

forming a third window on the semiconductor substrate, and exposing at least part of the GaN layer;

and forming a functional structure of the semiconductor device on the surface of the GaN layer based on the third window.

Preferably, in the above manufacturing method, the method for forming the third window includes:

the third window is positioned on one side of the second insulating layer facing the semiconductor substrate, is positioned on one side of the nucleation block of the semiconductor substrate facing the second window of the semiconductor substrate, and is communicated with the second window.

filling an insulating medium in a second window of the semiconductor substrate, and carrying out planarization treatment on one side of the second insulating layer of the semiconductor substrate, which is away from the first insulating layer of the semiconductor substrate;

and forming the third window on the first insulating layer of the semiconductor substrate.

Preferably, in the above manufacturing method, forming the functional structure on the GaN layer surface includes:

and preparing a functional structure of the GaN-HEMT device, or a laser functional structure or an LED functional structure on the surface of the GaN layer based on an epitaxial process.

The application also provides a semiconductor substrate prepared by the manufacturing method according to any one of the above, wherein the semiconductor substrate comprises:

and the two opposite sides of the GaN layer are respectively covered with an insulating layer.

The present application also provides a semiconductor device including:

the semiconductor substrate prepared by any one of the above manufacturing methods, wherein the semiconductor substrate is provided with a GaN layer, and two opposite sides of the GaN layer are respectively covered with an insulating layer;

wherein one of the insulating layers has a window exposing the GaN layer;

and a functional structure positioned on the surface of the GaN layer based on the window.

As can be seen from the above description, in the semiconductor substrate, the semiconductor device and the manufacturing method provided in the technical solution of the present application, the manufacturing method of the semiconductor substrate includes: providing an SOI substrate, the SOI substrate comprising: a first insulating layer; at least one monocrystalline silicon block located on the first insulating layer; the second insulating layer covers the monocrystalline silicon block and the first insulating layer around the monocrystalline silicon block; the single crystal silicon block has opposite first and second ends in a direction parallel to the SOI substrate; forming a first window on the second insulating layer to expose a part of the monocrystalline silicon block corresponding to the first end; forming a nucleation block based on the monocrystalline silicon block exposed by the first window; forming a second window penetrating through the second insulating layer, and exposing a part of the monocrystalline silicon block corresponding to the second end; removing the monocrystalline silicon block based on the second window to form a gap structure between the first insulating layer and the second insulating layer; based on the nucleation blocks, a GaN layer is selectively laterally epitaxially grown within the gap structure. Therefore, the technical scheme is based on the SOI substrate, the semiconductor substrate comprising III-V material GaN is prepared, the lattice defect density of GaN can be reduced, and the performance of a semiconductor device prepared based on the semiconductor substrate can be improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the provided drawings without inventive effort to those skilled in the art.

The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and should not be construed as limiting the scope of the invention, since any modification, variation in proportions, or adjustment of the size, which would otherwise be used by those skilled in the art, would not have the essential significance of the present disclosure, would not affect the efficacy or otherwise be achieved, and would still fall within the scope of the present disclosure.

FIG. 1 is a schematic view of the crystal structure of three semiconductor materials;

FIG. 2 is a schematic diagram of lattice structures and crystal planes of three semiconductor materials;

fig. 3-24 are process flow diagrams of a method for fabricating a semiconductor substrate according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which it is shown, and in which it is evident that the embodiments described are exemplary only some, and not all embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In conventional techniques, inP is typically used for the substrate of typical III-V materials.

As shown in fig. 1, fig. 1 is a schematic diagram of crystal structures of three semiconductor materials, fig. 1 (a) is a lattice structure of Si, fig. 1 (b) is a lattice structure of InP, and it is known from fig. 1 (a) and (b) that InP is a cubic structure, which is the same as the lattice structure of Si, and that there is no significant obstacle for SOI (silicon on insulator) substrate template-assisted lateral heteroepitaxy. Fig. 1 (c) shows a lattice structure of GaN, which is not a cubic structure, and cannot be directly formed by lateral heteroepitaxy assisted by SOI substrate templates.

Due to the back-melting etching problem of GaN to Si, an epitaxial layer AlN is needed to be used as a buffer layer and a nucleation layer on Si, so that direct contact of GaN and Si and subsequent nucleation growth of GaN are prevented. But AlN cannot be directly prepared by template-assisted selective lateral heteroepitaxial growth.

As shown in fig. 2, fig. 2 is a schematic diagram of lattice structures and crystal planes of three semiconductor materials, in which fig. 2 (a) is a lattice structure of GaN and its (0001) crystal plane, fig. 2 (b) is a lattice structure of Si and its (111) crystal plane, fig. 2 (c) is an epitaxial relationship between the (0001) crystal plane in the GaN lattice structure and the (111) crystal plane in the Si lattice structure, and fig. 2 (d) is a crystal orientation relationship between the (0001) crystal plane in the GaN lattice structure and the (111) crystal plane in the Si lattice structure.

The inventors have found that, based on the relationship shown in fig. 2, a high-quality GaN epitaxial layer can be formed by two etching and epitaxy methods using an SOI substrate. In the semiconductor substrate prepared based on the preparation method and comprising III-V material GaN, the GaN layer has a certain area and higher crystal quality, can be used for epitaxy and processing various GaN discrete devices, such as micro electronic devices and micro photoelectric devices, and can be used in the fields of communication photoelectrons, automobile photoelectrons, optical sensing and the like.

In view of this, the technical scheme of the present application provides a semiconductor substrate, a semiconductor device and a manufacturing method, where the manufacturing method of the semiconductor substrate includes:

According to the manufacturing method, the semiconductor substrate comprising III-V material GaN is prepared based on the SOI substrate, so that the lattice defect density of GaN can be reduced, and the performance of a semiconductor device prepared based on the semiconductor substrate can be improved.

Optionally, the manufacturing method may form a nucleation layer by a selective epitaxy mode, and then form the nucleation block in the first window by combining with a Chemical Mechanical Polishing (CMP) process, so that a template is not required to assist selective lateral heteroepitaxy to prepare the AlN buffer layer.

In addition, after forming a nucleation block based on the SOI substrate, the manufacturing method removes the monocrystalline silicon block in the SOI substrate, and forms a GaN layer based on a gap structure formed by removing the monocrystalline silicon block, so that direct contact between GaN and Si is avoided.

In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.

Referring to fig. 3 to 24, fig. 3 to 24 are process flow diagrams of a method for manufacturing a semiconductor substrate according to an embodiment of the present application, where the method includes:

step S11: as shown in fig. 3 and 4, an SOI substrate 100 is provided.

The SOI substrate 100 includes: a first insulating layer 101; at least one single crystal silicon block 102 located on the first insulating layer 101; a second insulating layer 103, wherein the second insulating layer 103 covers the monocrystalline silicon block 102 and the first insulating layer 101 around the monocrystalline silicon block 102; the single crystal silicon block 102 has opposite first and second ends in a direction parallel to the SOI substrate 100. In fig. 4, the left side is taken as a first end, and the right side is taken as a second end as an example.

Fig. 3 is a plan view of the SOI substrate 100, and fig. 4 is a sectional view of fig. 3 in the A-A' direction. It should be noted that, in the SOI substrate 100, the number of the monocrystalline silicon blocks 102 may be one or more, and when there are a plurality of monocrystalline silicon blocks 102, the number and arrangement of the monocrystalline silicon blocks 102 are not limited to those shown in fig. 3, and as shown in fig. 5, the number and arrangement of the monocrystalline silicon blocks 102 may be set based on the requirement, which is not particularly limited in the embodiment of the present application.

Step S12: as shown in fig. 6 to 9, a first window 104 is formed on the second insulating layer 103 to expose a portion of the monocrystalline silicon block 102 corresponding to the first end.

In this step, the first window 104 is formed based on a photolithography process. First, as shown in fig. 6, a photoresist 105 is formed on the surface of the second insulating layer 103. Then, as shown in fig. 7, the photoresist 105 is patterned, and an opening C1 is formed at a position of the photoresist 105 corresponding to the first window 104. As shown in fig. 8, the second insulating layer 103 is etched based on the opening C1, and a first window 104 is formed in the second insulating layer 103. Finally, as shown in fig. 9, the photoresist 105 on the surface of the second insulating layer 103 is removed.

Step S13: as shown in fig. 10-12, a nucleation block 106 is formed based on the monocrystalline silicon block 102 exposed by the first window 104.

In this embodiment, the nucleation block 106 is an AlN block, and a surface of the monocrystalline silicon block 102 facing the second insulating layer 103 is a (111) crystal plane of monocrystalline Si. Wherein AlN and GaN are III-V materials, and can be used as nucleation substrates of GaN. And the (111) crystal face of the single crystal Si comprises a hexagon matched with the GaN (0001) crystal face, so that the subsequently formed GaN layer 111 has good lattice quality and defect density is reduced. Thus, the AlN layer can be directly formed by surface epitaxial growth based on the (111) crystal face of the single crystal Si, and is used for preparing the AlN block, the manufacturing process is simple, and the high-quality AlN layer can be formed based on the (111) crystal face of the single crystal Si, so that the high-quality GaN layer 111 is formed in the subsequent process.

In this step, the method of forming the nucleation block 106 includes:

first, as shown in fig. 10, a nucleation layer 107 is formed, and the nucleation layer 107 fills at least a portion of the first window 104 and covers a surface of the second insulating layer 103 facing away from the first insulating layer 101.

The nucleation layer 107 on the surface of the second insulating layer 103 is then removed, leaving the nucleation layer 107 within the first window 104, forming the nucleation block 106, as shown in fig. 11. The nucleation block 106 is flush with the surface of the second insulating layer 103. The nucleation layer 107 on the surface of the second insulating layer 103 may be removed by a CMP process and a portion of the second insulating layer 103 may be removed such that the nucleation block 106 is flush with the surface of the second insulating layer 103.

Finally, as shown in fig. 12, a layer of insulating material with the same material is formed on the surface of the second insulating layer 103, so as to form a new second insulating layer 103.

In the manufacturing method of the embodiment of the present application, each insulating layer may be a silicon oxide layer. The contact areas of both the first insulating layer 101 and the second insulating layer 103 of the corresponding materials may have no visible interface, the manner shown in fig. 12 showing the interface areas of the two for the sake of clarity in illustrating the relative hierarchy.

Step S14: as shown in fig. 13-16, a second window 109 is formed through the second insulating layer 103 to expose a portion of the monocrystalline silicon block 102 corresponding to the second end;

in which the second windows 109 are formed by a photolithographic process. As with the method of forming the first window 104, first, a photoresist layer is formed as shown in fig. 13, then, as shown in fig. 14, a photoresist is patterned, an opening is formed at a position of the photoresist corresponding to the second window 109, then, as shown in fig. 15, etching is performed based on the opening of the photoresist to form the second window 109, and finally, as shown in fig. 16, the photoresist is removed.

The etch depth of the first window 104 on the surface of the monocrystalline silicon block 102 may be zero or greater than zero. The etching depth of the second window 109 on the surface of the monocrystalline silicon block 102 is greater than zero, so that over-etching is formed on the monocrystalline silicon block 102 when the second window 109 is formed, the surface roughness of the monocrystalline silicon block 102 exposed by the second window 109 is improved, and the etching of the monocrystalline silicon block 102 when the monocrystalline silicon block 102 is removed in a subsequent process is facilitated.

Step S15: as shown in fig. 17, the monocrystalline silicon block 102 is removed based on the second window 109, forming a gap structure 110 between the first insulating layer 101 and the second insulating layer 103.

In this step, the monocrystalline silicon block 102 is removed based on wet etching, and the speed of removing the monocrystalline silicon block 102 in the etching process can be increased based on the over etching of the monocrystalline silicon block 102 by the second window 109 in the previous step.

In embodiments of the present application, single crystal silicon block 102 may be selectively etched using a 10% dilute KOH solution. At room temperature, the diluted KOH solution has low etching rate to AlN, and the AlN block can be prevented from being completely etched based on the control of etching time.

It should be noted that, the method is not limited to selectively etching the monocrystalline silicon block 102 by using diluted KOH solution, and other reagents with high selective etching ratio may be used to etch and remove the monocrystalline silicon block 102, and the type of etching reagent used in the embodiment of the present application is not limited.

After the monocrystalline silicon block 102 is removed, the substrate is cleaned to avoid etching residues affecting the lattice quality of the subsequently prepared GaN layer 111.

Step S16: as shown in fig. 18, a GaN layer 111 is selectively laterally epitaxially grown within the gap structure 110 based on the nucleation block 106.

The GaN layer 111 may be prepared using an MOCVD (metal organic chemical vapor deposition) process. In the MOCVD apparatus, template-assisted selective lateral heteroepitaxial growth of GaN is performed. In the technical scheme, an AlN nucleation block is formed based on a Si (111) crystal face of monocrystalline silicon, the monocrystalline silicon block 102 is removed subsequently, and template-assisted selective lateral heteroepitaxial growth of GaN is performed based on a template structure of the SOI substrate 100 and the AlN nucleation block, so that a high-quality GaN layer 111 with a defect density smaller than 10 can be formed ³ cm ^-2 。

As described above, in the manufacturing method according to the embodiment of the present application, the method for forming the second window 109 includes: etching the second insulating layer 103 based on a photolithography process to form the second window 109; the second insulating layer 103 is over-etched, so that the surface roughness of the monocrystalline silicon block 102 exposed by the second window 109 is increased, so that the etching speed of the monocrystalline silicon block 102 is increased in the subsequent process.

After the gap structure 110 is formed, a top view of the substrate before the GaN layer 111 is formed is shown in fig. 19, a cross-sectional view of fig. 19 in A-A 'direction is shown in fig. 17, and a cross-sectional view of fig. 19 in B-B' direction is shown in fig. 20. As shown in the drawings and fig. 19 and 20 in combination with the above embodiments, the single crystal silicon block 102 has a rectangular shape; the two opposite sides of the rectangle are respectively provided with the first window 104 and the second window 109, and the second insulating layer 103 outside the other two opposite sides of the rectangle is in contact with the first insulating layer 101, so as to serve as a supporting structure of the gap structure 110. Specifically, as shown in fig. 20, the second insulating layer 103 contacts the first insulating layer 101 on the outer sides of the left and right sides of the gap structure 110, so that the second insulating layer 103 can be prevented from cracking or collapsing due to gravity after the gap structure 110 is formed as a supporting structure of the gap structure 110.

A plurality of device structures can be formed based on the plurality of monocrystalline silicon blocks 102, and the plurality of device structures can be arranged based on a layout array of the monocrystalline silicon blocks 102. Based on the shape of the monocrystalline silicon block 102, a correspondingly shaped device structure may be formed, and the shape of the monocrystalline silicon block 102 and the device structure formed based thereon are not particularly limited in the embodiments of the present application. In the manner shown in fig. 19, one single crystal silicon block 102 corresponds to one device structure, and the device structure may have a size of several micrometers to several tens micrometers in the lateral direction as well as the longitudinal direction, which may be adjusted based on the requirements.

As described above, in this embodiment of the present application, there may be a plurality of monocrystalline silicon blocks 102, and between two adjacent monocrystalline silicon blocks 102, the second insulating layer 103 is in contact with the first insulating layer 101, so that after removing the monocrystalline silicon blocks 102, a supporting structure is formed.

In the embodiment of the present application, the thickness of the monocrystalline silicon block 102 ranges from 100nm to 900nm. Within this thickness range, the formation of the high-quality GaN layer 111 can be ensured. Meanwhile, while meeting the thickness requirements of the GaN layer 111 required by various current semiconductor devices, the increase in device volume caused by the excessive thickness of the GaN layer 111 can be avoided.

The semiconductor substrate having the GaN layer 111 prepared based on the above-described fabrication method can be used as a platform for preparing GaN electronic devices, not limited to photovoltaic devices for preparing GaN.

Based on that a single crystal Si (111) crystal face can not be directly subjected to template auxiliary transverse epitaxial AlN layer, the first window 104 and the second window 109 are respectively formed by adopting a twice etching process, a nucleation block 106 of AlN can be formed on the single crystal Si (111) crystal face through a simple surface epitaxial mode (first epitaxy) based on the first window, the single crystal Si block 102 is removed based on the second window 109, and then the GaN layer 111 can be formed through epitaxy based on a gap structure 110 formed after the single crystal Si block 102 is removed and the nucleation block 106 of AlN (second epitaxy). Therefore, in the technical scheme, the difficulty of lateral epitaxy of AlN assisted by the template on the Si (111) surface is considered, and a nucleation block 106 and a GaN layer 111 of high-quality AlN material can be formed by adopting a process of etching twice and epitaxy twice.

Based on the above embodiments, another embodiment of the present application further provides a method for manufacturing a semiconductor device, where the method includes:

first, a semiconductor substrate prepared by the manufacturing method described in the above embodiment is provided.

Then, a functional structure of the semiconductor device is formed based on the GaN layer 111 in the semiconductor substrate.

In one mode, forming a functional structure of a semiconductor device based on a GaN layer 111 in a semiconductor substrate includes: as shown in fig. 21, a third window 112 is formed on the semiconductor substrate to expose at least a portion of the GaN layer 111; as further shown in fig. 22, a functional structure 113 of the semiconductor device is formed on the surface of the GaN layer 111 based on the third window 112.

In the manner shown in fig. 21 and 22, the method for forming the third window 112 includes: the third window 112 is formed on a side of the second insulating layer 103 facing the semiconductor substrate, the third window 112 is located on a side of the nucleation block 106 of the semiconductor substrate facing the second window 109 of the semiconductor substrate and is in communication with the second window 109. In this way, the insulating layer on the surface of the GaN layer 111 may be removed by dry etching to form the third window 112.

In other manners, the method for forming the third window 112 includes: as shown in fig. 23, an insulating medium is filled in the second window 109 of the semiconductor substrate, and a planarization treatment is performed on a side of the second insulating layer 103 of the semiconductor substrate away from the first insulating layer of the semiconductor substrate, and the planarization treatment may be performed through a CMP process; as further shown in fig. 24, the third window 112 is formed in the first insulating layer 101 so as to form a functional structure 113. In this manner, the third window 113 may also be formed by dry etching.

In this embodiment, forming the functional structure 113 of the semiconductor substrate on the surface of the GaN layer 111 includes: based on the epitaxial process, a functional structure of the GaN-HEMT device, or a laser functional structure, or an LED functional structure is prepared on the surface of the GaN layer 111. The GaN layer 111 may be a layer structure of the N-polar plane of the semiconductor substrate. The GaN layers 111 of the respective regions may correspond to separate devices, respectively.

Based on the above embodiment, another embodiment of the present application further provides a semiconductor substrate prepared by the above manufacturing method, where the structure of the semiconductor substrate may be shown with reference to the drawings in the above embodiment, and the method includes: and a GaN layer 111, wherein two opposite sides of the GaN layer 111 are respectively covered with an insulating layer (i.e., a first insulating layer 101 and a second insulating layer 102).

The semiconductor substrate according to this embodiment is prepared based on the manufacturing method according to the above embodiment, which can greatly reduce the defect density in the GaN layer 111 and improve the performance of the semiconductor device.

Based on the above embodiments, another embodiment of the present application further provides a semiconductor device, where the structure of the semiconductor device is as shown in fig. 22 or fig. 24, and the semiconductor device includes:

the structure of the semiconductor substrate prepared by the above manufacturing method can be shown by referring to the drawings of the above embodiments, the semiconductor substrate has a GaN layer 111, and two opposite sides of the GaN layer 111 are respectively covered with an insulating layer;

one of the insulating layers has a window (the third window 112) exposing the GaN layer 111;

based on the window, a functional structure 113 is located on the surface of the GaN layer 111.

The semiconductor device can be a GaN-HEMT device, a laser or an LED.

The semiconductor device according to the embodiment of the application adopts the semiconductor substrate prepared based on the manufacturing method of the embodiment, the GaN layer 111 has a good lattice structure, the defect density is small, and the semiconductor device has good reliability.

In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. The semiconductor device and the manufacturing method thereof, and the semiconductor substrate disclosed in the embodiments correspond to the manufacturing method of the semiconductor substrate disclosed in the embodiments, so that the description is relatively simple, and the relevant points are described in the relevant parts of the manufacturing method of the semiconductor substrate.

It should be noted that in the description of the present application, it is to be understood that the description of the drawings and embodiments are illustrative and not restrictive. Like diagramming marks throughout the embodiments of the specification identify like structures. In addition, the drawings may exaggerate the thicknesses of some layers, films, panels, regions, etc. for understanding and ease of description. It will also be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In addition, "on …" refers to positioning an element on or under another element, but not essentially on the upper side of the other element according to the direction of gravity.

The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like are used for convenience in describing and simplifying the present application based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of fabricating a semiconductor substrate, the method comprising:

2. The method of claim 1, wherein the nucleation block is an AlN block and the surface of the single crystal silicon block facing the second insulating layer is a (111) crystal plane of single crystal Si.

3. The method of making of claim 1, wherein the method of forming the nucleation block comprises:

4. The method of manufacturing of claim 1, wherein the method of forming the second window comprises:

5. The method of claim 1, wherein the single crystal silicon block is rectangular; the first window and the second window are correspondingly arranged on two opposite side edges of the rectangle respectively, and the second insulating layer outside the other two opposite side edges of the rectangle is in contact with the first insulating layer to serve as a supporting structure of the gap structure.

6. The method of claim 1, wherein there are a plurality of single crystal silicon blocks, and the second insulating layer is in contact with the first insulating layer between two adjacent single crystal silicon blocks.

7. The method of claim 1, wherein the thickness of the single crystal silicon block is in the range of 100nm to 900nm.

8. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate prepared by the method of any one of claims 1-7;

9. The method of manufacturing of claim 8, wherein the method of forming the third window comprises:

10. The method of manufacturing of claim 8, wherein the method of forming the third window comprises:

11. The method of fabricating of claim 8, wherein forming the functional structure on the GaN layer surface comprises:

12. A semiconductor substrate prepared by the method of any one of claims 1-7, wherein the semiconductor substrate comprises:

13. A semiconductor device, comprising:

the semiconductor substrate prepared by the method according to any one of claims 1 to 7, wherein the semiconductor substrate has a GaN layer, and two opposite sides of the GaN layer are respectively covered with an insulating layer;

wherein one of the insulating layers has a window exposing the GaN layer;