CN116176454A

CN116176454A - Dormancy and awakening circuit, circuit board and automobile controller

Info

Publication number: CN116176454A
Application number: CN202310073284.6A
Authority: CN
Inventors: 陈智红; 凌健鸿; 张鹏
Original assignee: Guangzhou Ligong Science And Technology Co ltd
Current assignee: Guangzhou Ligong Science And Technology Co ltd
Priority date: 2023-01-31
Filing date: 2023-01-31
Publication date: 2023-05-30

Abstract

The embodiment of the application provides a dormancy and awakening circuit, a circuit board and an automobile controller, and relates to the technical field of automobile control, wherein in the dormancy and awakening circuit, a power supply end of a power chip module is connected with a power supply pin of a connector, and a first power supply pin of a core processor is connected with an output end of the power chip module; the CAN transceiver is connected with the core processor through a bus, the CAN transceiver is also connected with the connector through a twisted pair, the second power supply pin is connected with the output end of the power supply chip module, the dormant power supply pin is connected with the power supply pin, the forbidden control pin is connected with the external enabling end of the power supply chip module, the input end of the IGN signal conversion module is connected with the IGN signal pin, the first output end of the IGN signal conversion module is connected with the wake-up pin, and the second output end of the IGN signal conversion module is connected with the general input pin of the core processor. The circuit design of this scheme is simple, and can reduce the generated consumption effectively.

Description

Dormancy and awakening circuit, circuit board and automobile controller

Technical Field

The embodiment of the application relates to the technical field of automobile control, in particular to a dormancy and awakening circuit, a circuit board and an automobile controller.

Background

Under the wave-tide mat of information technology development, intellectualization, networking and electrodynamic technology have become the main direction of development of the automobile industry. Whether it is a three-electric system (battery, motor and electric control) or various vehicle-mounted parts, the demand of automobiles for chips is increasing. The number of chips required for 2021 average vehicle manufacturing is more than 1000, and the number of processors required is 70-100. The automobile needs more chips, and even if the control system of the automobile is in a dormant mode, the power consumption brought by the chips is larger.

In view of cost and energy, low power consumption design of automobile control systems is important for such a large number of power consumption chips. In the related art, for a control system adopting a complex processor, the adopted low-power-consumption circuit is complex in design, more devices are needed, the power consumption generated in a low-power-consumption mode is still higher, the current is above milliamp level, and the low-power-consumption requirement is difficult to meet.

Disclosure of Invention

The embodiment of the application provides a dormancy and awakening circuit, a circuit board and an automobile controller, wherein the circuit design is simple, and the generated power consumption can be effectively reduced.

In a first aspect, embodiments of the present application provide a sleep and wake-up circuit that includes a connector, a power chip module, a core processor, a CAN transceiver, and an IGN signal conversion module.

The connector comprises a power supply pin and an IGN signal pin; the power supply end of the power supply chip module is connected with the power supply pin of the connector, and the power supply chip module is used for providing working voltage for each device; the first power supply pin of the core processor is connected with the output end of the power supply chip module; the CAN transceiver is connected with the core processor through a bus, and is also connected with the connector through a twisted pair; the CAN transceiver further comprises a second power supply pin, a dormant power supply pin, a wake-up pin and a disabling control pin, wherein the second power supply pin is connected with the output end of the power supply chip module; the input end of the IGN signal conversion module is connected with the IGN signal pin, the first output end of the IGN signal conversion module is connected with the wake-up pin, the second output end of the IGN signal conversion module is connected with the general input pin of the core processor, and the IGN signal conversion module is used for controlling the input of the wake-up pin and the input of the general input pin according to the output of the IGN signal pin.

In a second aspect, embodiments of the present application further provide a circuit board that includes the sleep and wake-up circuit described in the above embodiments.

In a third aspect, embodiments of the present application further provide an automobile controller, where the automobile controller includes a circuit board as described in the foregoing embodiments.

The dormancy and wake-up circuit CAN realize compatibility of IGN signals and CAN signals through the IGN signal conversion module and the CAN transceiver, and realize switch between dormancy and wake-up. The design of the dormancy and the wake-up circuit can enable fewer chips to be in a working state in a dormancy mode, so that the lowest-level power consumption is effectively realized; meanwhile, the circuit design is simple, a complex hardware architecture is not needed, and the hardware cost is saved.

Drawings

FIG. 1 is a schematic diagram of a low power sleep and wake-up circuit supporting CAN and IGN signals in the related art;

FIG. 2 is a schematic diagram of another low power sleep and wake-up circuit supporting CAN and IGN signals in the related art;

FIG. 3 is a schematic block diagram of a sleep and wake-up circuit provided in an embodiment of the present application;

fig. 4 is a schematic circuit diagram of a first signal conversion unit according to an embodiment of the present application;

fig. 5 is a schematic circuit diagram of a second signal conversion unit according to an embodiment of the present application;

fig. 6 is a schematic circuit diagram of a sleep and wake-up circuit according to an embodiment of the present application.

Detailed Description

The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the embodiments described herein are for purposes of illustration and not limitation. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings.

It should be noted that, for the sake of brevity, this specification is not exhaustive of all of the alternative embodiments, and after reading this specification, one skilled in the art will appreciate that any combination of features may constitute an alternative embodiment as long as the features are not mutually inconsistent.

It should be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action or object from another entity or action or object without necessarily requiring or implying any actual such relationship or order between such entities or actions or objects. The number of the objects to be distinguished by "first", "second", etc. is not limited, and may be one or plural, and it is conceivable that "plural" is represented as two or more in the description of the present application.

In the related art, two wake-up modes exist in an automobile control system, namely, an automobile controller switches a sleep mode into a working mode by detecting an IGN signal output by an ignition switch so as to wake-up; secondly, the automobile controller detects a CAN signal, wherein the CAN signal includes but is not limited to a wake-up instruction (also called a message, a signal, a message, etc.) transmitted through a CAN bus, so that the switching from the sleep mode to the working mode is realized.

The control system compatible with the two wake-up modes has larger power consumption, and even in the sleep mode, the chips such as the processor and the like are in a low power consumption mode, the working current of the control system is still in the milliamp level or above, and the control system still cannot realize lower power consumption operation. As shown in fig. 1, fig. 1 is a schematic diagram of a low-power sleep and wake-up circuit supporting CAN signals and IGN signals in the related art, in which two power chips convert a power voltage provided by a connector into an operating voltage adapted to a core processor and provide the core processor with the operating voltage, the connector is further connected to a CAN transceiver through a twisted pair, and the CAN transceiver is in communication connection with the core processor, such as being connected by a bus and performing signal transmission. The connector may also transmit IGN signals to the core processor. When the circuit is in a sleep mode with low power consumption, the CAN transceiver and the two power supply chips in the circuit are still in a working state, so that more chips work in the circuit, the power consumption is still higher, the power consumption is not effectively reduced, and the current of the circuit is in the milliamp level.

Fig. 2 is a schematic diagram of another low-power sleep and wake-up circuit supporting CAN signals and IGN signals in the related art, as shown in fig. 2, two power chips convert the power voltage provided by the connector into an operating voltage adapted to the core processor, and provide the core processor with the operating voltage. The connector also connects to the CAN transceiver via the twisted pair wire, and the CAN transceiver needs to be connected to the core processor via the coprocessor, and similarly, the connector also needs to transmit IGN signals to the core processor via the coprocessor. In addition, the CAN transceiver and the coprocessor provide operating voltages through another power chip. When the circuit is in the sleep mode with low power consumption, the CAN transceiver and the power chip in the circuit are in a working state, and the circuit shown in fig. 2 CAN effectively reduce power consumption compared with the circuit shown in fig. 1, but the power consumption generated when the circuit runs with low power consumption is still larger, and the cost of circuit devices is higher.

Therefore, the embodiment of the application provides a dormancy and awakening circuit, which has a simple circuit structure and can effectively reduce the power consumption generated during low-power-consumption operation. Referring to fig. 3, fig. 3 is a schematic block diagram of a sleep and wake-up circuit according to an embodiment of the present application. The sleep and wake-up circuit of the present application includes a connector 301, a power chip module 302, a core processor 303, a CAN transceiver 304, and an IGN signal conversion module 305.

The connector 301 is used as a connection device between a circuit and an external device, and a power supply pin, an IGN signal pin, and a CAN signal pin are provided thereon. The power supply pin is used to connect the power supply chip module 302 to a power supply, so that the power supply pin is connected to a power supply terminal of the power supply chip module 302, and the power supply chip module 302 is used to provide an operating voltage for each device in the circuit, and it is conceivable that the first power supply pin of the core processor 303 is connected to an output terminal of the power supply chip module 302.

CAN transceiver 304 is coupled to connector 301 via twisted pair wires, such as on CAN signal pins of connector 301. In addition, the CAN transceiver 304 is also connected to the core processor 303 through a bus so that the CAN transceiver 304 CAN receive a control signal or the like transmitted from the core processor 303. The CAN transceiver 304 comprises a second power supply pin for accessing the operating voltage of the CAN transceiver 304; CAN transceiver 304 also includes a sleep power pin that is connected to the power pin of connector 301. It should be noted that the CAN transceiver 304 of the present application has a wake-up function, and further includes a wake-up pin and a disable control pin, where the wake-up pin CAN be used to control the output of the disable control pin, and the disable control pin is connected to an external enable terminal of the power chip module 302, where the external enable terminal CAN be used to control the working state of the power chip module 302, such as to control the power chip module 302 to start or stop providing the working voltage, so that the output of the power chip module 302 CAN be controlled by controlling the level change of the wake-up pin.

The first output end of the IGN signal conversion module 305 is connected to the wake-up pin, and the input end of the IGN signal conversion module 305 is connected to the IGN signal pin, so that the IGN signal conversion module 305 can control the input of the wake-up pin according to the received IGN signal, so that the level change at the wake-up pin is effectively controlled. In addition, the second input terminal of the IGN signal conversion module 305 is connected to the general input pin of the core processor, so that the IGN signal conversion module 305 can also control the input of the general input pin. The core processor 303 may determine the control signal sent to the CAN transceiver 304 based on the level change of the universal input pin.

According to the scheme, the dormancy and awakening circuit CAN realize compatibility of IGN signals and CAN signals through the IGN signal conversion module and the CAN transceiver, and realize the switch between dormancy and awakening. The design of the dormancy and the wake-up circuit can enable fewer chips to be in a working state in a dormancy mode, so that the lowest-level power consumption is effectively realized; meanwhile, the circuit design is simple, a complex hardware architecture is not needed, and the hardware cost is saved.

In some embodiments, the power chip module includes a first power chip and a second power chip, a first input pin of the first power chip is connected to the power pin, a first enable pin of the first power chip is connected to the disable control pin, a first output pin of the first power chip is connected to a second input pin and a second enable pin of the second power chip, and a second output pin of the second power chip is connected to the first power pin. The first power chip is used for providing a first working voltage, such as 5V, and the second power chip is used for providing a second working voltage, such as 3.3V.

Moreover, the working state of the first power chip is controlled by the CAN transceiver, and the working state of the second power chip is controlled by the first power chip, so that the CAN transceiver CAN control the power chip module. For example, the first power chip and the second power chip both enable and output corresponding voltages when their corresponding enable pins are at a high level, and when the disable control pin of the CAN transceiver outputs a high level, the first power chip enables and outputs a first operating voltage, and at this time, since the first output pin of the first power chip is connected to the second enable pin of the second power chip and the first power chip outputs a high level, the second power chip enables and outputs a second operating voltage. When the forbidden control pin of the CAN transceiver outputs a low level, the first power chip and the second power chip are not enabled, and corresponding working voltage cannot be provided.

Therefore, the first power chip and the second power chip can be enabled to operate simultaneously, and the first power chip and the second power chip can be further controlled to be not operated, so that the power consumption in the sleep mode is reduced.

In some embodiments, the power chip module includes a first power chip and a second power chip, and the second power pin of the CAN transceiver includes a primary power pin and an auxiliary power pin. Therefore, the main power supply pin is connected with the first output pin of the first power supply chip, and CAN provide working voltage for the CAN transceiver, such as working voltage of 5V; the auxiliary power supply pin is connected with a second output pin of the second power supply chip so as to internally carry out level adjustment on digital transceiving of the CAN transceiver.

Therefore, after the system enters the sleep mode, the CAN transceiver is only connected with voltage through the sleep power supply pin, so that the power supply current in the system is in microampere level, and the low-power consumption design is effectively realized.

In some embodiments, the IGN signal conversion module includes a first signal conversion unit and a second signal conversion unit, where the first signal conversion unit is used as a detection unit for an IGN signal, an input end of the first signal conversion unit is connected to an IGN signal pin, an output end of the first signal conversion unit is connected to a wake-up pin of the CAN transceiver, and the first signal conversion unit CAN adjust a level change of the wake-up pin according to an output of the IGN signal pin, for example, when the IGN signal pin outputs a corresponding level so that the first signal conversion unit is in conduction, the level of the wake-up pin changes, so that the CAN transceiver CAN control the power chip module.

In addition, the input end of the second signal conversion unit is connected with the output end of the first signal conversion unit, and the output end of the second signal conversion unit is connected with the general input pin of the core processor. Therefore, the first signal conversion unit can also be used for controlling the conduction state of the second signal conversion unit, so that the level change of the input to the general input pin can be controlled. That is, the IGN signal conversion module may control the input to the wake-up pin and the general input pin according to the on state of the first signal conversion unit and the on state of the second signal conversion unit.

Specifically, fig. 4 is a circuit schematic diagram of a first signal conversion unit according to an embodiment of the present application, as shown in fig. 4, in an embodiment, the first signal conversion unit includes a first current limiting resistor R1, a first pull-down resistor R2, a filter capacitor C1, a first switching tube Q1, and a first pull-up resistor R3. The two ends of the first current limiting resistor R1 are respectively connected with the IGN signal pin and the control end of the first switching tube Q1, the first pull-down resistor R2 and the filter capacitor C1 are connected in parallel, one end of the first pull-down resistor R2 is connected with the control end of the first switching tube Q1, the other end of the first pull-down resistor R2 is grounded, the parallel first pull-down resistor R2 and the filter capacitor C1 can effectively avoid suspending the control end of the first switching tube Q1, and the effect of avoiding misoperation caused by interference is also achieved. In addition, the input end of the first switching tube Q1 is connected with a first pull-up resistor R3, and is connected with a power supply voltage through the first pull-up resistor R3, the input end of the first switching tube Q1 is also connected with a wake-up pin, and the output end of the first switching tube Q1 is grounded.

The first switching transistor Q1 may be an NPN triode, a base terminal of the NPN triode is used as a control terminal of the first switching transistor Q1, a collector terminal of the NPN triode is used as an input terminal of the first switching transistor Q1, and an emitter terminal of the NPN triode is used as an output terminal of the first switching transistor Q1.

Therefore, it can be understood that, when the first switching tube Q1 is not turned on, since the wake-up pin is connected to the input terminal of the first switching tube Q1, that is, when the first switching tube Q1 is not turned on, the wake-up pin is also connected to the power supply voltage through the first pull-up resistor R3, and thus the wake-up pin is at a high level. When the control end of the first switch tube Q1 receives the IGN signal, the first switch tube Q1 CAN meet the conducting condition, so that the first switch tube Q1 is conducted, the wake-up pin is changed from high level to low level, the disable control pin of the CAN transceiver outputs high level, the power supply chip module is enabled, the system is waken, and the sleep mode is used for entering the working mode.

It should be noted that, in some embodiments, the first switching tube may further use an NMOS tube, for example, a gate terminal of the NMOS tube is used as a control terminal of the first switching tube, a drain terminal of the NMOS tube is used as an input terminal of the first switching tube, and a source terminal of the NMOS tube is used as an output terminal of the first switching tube.

Specifically, fig. 5 is a schematic circuit diagram of a second signal conversion unit according to an embodiment of the present application, as shown in the drawing, in an embodiment, the second signal conversion unit includes a second current limiting resistor R4, a second switching tube Q2, a second pull-up resistor R5, and a second pull-down resistor R6. The two ends of the second current limiting resistor R4 are respectively connected with the output end of the first signal conversion unit and the control end of the second switching tube Q2, the input end of the second switching tube Q2 is connected with working voltage through a second pull-up resistor R5, the output end of the second switching tube Q2 is grounded through a second pull-down resistor R6, and the output end of the second switching tube Q2 is also connected with a general input pin of the core processor.

The second switching tube Q2 may be a PNP triode, the base terminal of the PNP triode is used as the control terminal of the second switching tube Q2, the emitter terminal of the PNP triode is used as the input terminal of the second switching tube Q2, and the collector terminal of the PNP triode is used as the output terminal of the second switching tube Q2.

It will be appreciated that in the case where the first signal conversion unit is not conductive, the second signal conversion unit is also in a non-conductive state, i.e. the first switching tube is non-conductive, the control terminal of the second switching tube is at a high level, and the second switching tube is non-conductive, so that the general input pin is at a low level. And when the first switching tube is conducted, the control end of the second switching tube is grounded, and after the second switching tube meets the conduction condition, the second switching tube is conducted, so that the general input pin is in a high level.

It should be noted that, in some embodiments, the second switching tube may further use a PMOS tube, where a gate end of the PMOS tube is used as a control end of the second switching tube, a source end of the PMOS tube is used as an input end of the second switching tube, and a drain end of the PMOS tube is used as an output end of the second switching tube.

Fig. 6 is a schematic circuit diagram of a sleep and wake-up circuit according to an embodiment of the present application, where, as shown in the fig. 6, a connector J1 includes a power pin for accessing a power source, a CAN signal pin, and an IGN signal pin, where the power pin is used for providing a power source voltage for a first power chip U1; the CAN signal pins comprise two CAN_H pins and CAN_L pins, which are respectively the CAN_H pins and the CAN_L pins of the connector J1 are connected to corresponding pins of the CAN transceiver U4 through twisted pairs.

The OUT pin of the first power chip U1 is connected as an output pin to the IN pin of the second power chip U2, i.e. to the input pin of the second power chip U2, and IN addition, the OUT pin of the first power chip U1 is also connected to the enable pin of the second power chip, such as the EN pin IN the figure. The OUT pin of the second power chip is connected to the first power pin of the core processor U3.

The power supply pins of the CAN transceiver comprise a VCC pin and a VIO pin, wherein the VCC pin is used as a main power supply pin to be connected with the output pin of the first power supply chip U1, and the VIO pin is used as an auxiliary power supply pin to be connected with the output pin of the second power supply chip U2. The VBAT pin of the CAN transceiver is connected to the power pin of the connector J1 as a dormant power pin.

In addition, the IGN signal conversion module includes a first current limiting resistor R1, a first pull-down resistor R2, a filter capacitor C1, a first switching tube Q1, a first pull-up resistor R3, a second current limiting resistor R4, a second switching tube Q2, a second pull-up resistor R5, and a second pull-down resistor R6.

The first switching tube Q1 is an NPN triode, and the second switching tube Q2 is a PNP triode. The both ends of first current-limiting resistor R1 are connected IGN signal pin and first switch tube Q1's base terminal respectively, and first pull-down resistor R2 and filter capacitor C1 connect in parallel, and first switch tube Q1's control end is connected to first pull-down resistor R2's one end, and first pull-down resistor R2's the other end ground connection, and parallelly connected first pull-down resistor R2 and filter capacitor C1 can avoid first switch tube Q1's base end unsettled effectively, and still play the effect that avoids the interference to arouse the maloperation. In addition, the collector terminal of the first switching tube Q1 is connected to the first pull-up resistor R3, and is connected to the power supply voltage through the first pull-up resistor R3, and the collector terminal of the first switching tube Q1 is further connected to the WAKE-up pin (e.g. WAKE pin in the figure) of the CAN transceiver U4, where the emitter terminal of the first switching tube Q1 is grounded.

The two ends of the second current limiting resistor R4 are respectively connected with the collector electrode end of the first switching tube Q1 and the base electrode end of the second switching tube Q2, the emitter end of the second switching tube Q2 is connected with working voltage through a second pull-up resistor R5, the collector end of the second switching tube Q2 is grounded through a second pull-down resistor R6, and the collector electrode end of the second switching tube Q2 is also connected with a general input pin (namely a GPIO1 pin) of the core processor U3.

Therefore, when the system is in the sleep mode, the IGN signal pin is low level, the first switch tube Q1 and the second switch tube Q2 are not conducted, the first power chip U1, the second power chip U2 and the core processor U3 are in an inactive state, and only the VBAT pin is used for supplying power in the CAN transceiver U4, so that the sleep mode with low power consumption is realized, and the supply current is in a microampere level and CAN reach 60 microamps.

When the IGN signal pin of the connector J1 is at a high level, the first switching tube Q1 is turned on, and the WAKE pin of the CAN transceiver U4 is changed from a high level to a low level, so as to trigger the disable control pin (i.e., INH pin) of the CAN transceiver U4 to be at a high level, enabling the first power chip U1, and further enabling the second power chip U2, the core processor U3 and the CAN transceiver U4 to be in a working state, so that the whole circuit is in a working mode. When the IGN signal pin of the connector J1 is at a low level, the first switching tube Q1 is not turned on, the second switching tube Q2 is turned on, the level of the GPIO1 pin of the core processor U3 is changed from a high level to a low level, so that sleep interrupt is generated, the core processor U3 CAN inform the CAN transceiver U4 of entering a low power consumption mode through a bus signal after the related process is processed, so that the level of the INH pin is pulled down, the first power chip U1, the second power chip U2 and the core processor U3 are in an inactive state, the inside of the CAN transceiver U4 is only powered by the VBAT pin, the power supply current is at a microampere level, and the sleep mode with low power consumption is realized.

When the CAN transceiver U4 receives the CAN signal for triggering wake-up sent by the host through the connector J1, the INH pin of the CAN transceiver U4 outputs a high level, so that the first power chip U1 is enabled, and therefore, the first power chip U1, the second power chip U2 and the core processor U4 are in a working state. When the CAN transceiver U4 receives a CAN signal which is sent by the host and is used for triggering dormancy, the CAN transceiver U4 informs the core processor U3 of processing related processes through a bus, and the core processor U3 CAN inform the CAN transceiver U4 of entering a low-power consumption mode through the bus signal after the related processes are processed, so that an INH pin is set to be at a low level, the first power chip U1, the second power chip U2 and the core processor U3 do not work, and the CAN transceiver U4 is only powered by a VBAT pin, so that a low-power consumption dormancy mode is realized.

According to the workflow, only VBAT of the CAN transceiver U4 is powered in a low power consumption mode, and the VBAT power supply current in the low power consumption mode is only at the microampere level, so that the lowest-level power consumption CAN be truly realized; meanwhile, the peripheral circuit is simple in design, a complex hardware architecture is not needed, and the hardware cost is saved; the power supply current of the peripheral power supply and the processor is not needed to be considered in the low-power mode, and the current can be directly qualitatively determined, so that the platform design is realized.

The embodiment of the application also provides a circuit board, which comprises the dormancy and wake-up circuit according to the embodiment, and has the functions and beneficial effects of the dormancy and wake-up circuit.

The embodiment of the application also provides an automobile controller, which comprises the circuit board provided by the embodiment, and has the functions and beneficial effects of the dormancy and wake-up circuit. The automobile controller CAN simultaneously support the triggering of the IGN signal and the CAN signal, so that the switching of the working modes is performed, and the power consumption generated by the chip is lower in the dormant mode, so that the microampere level CAN be achieved, and the low-power consumption design is effectively realized.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.

Note that the above is only a preferred embodiment of the present application and the technical principle applied. Those skilled in the art will appreciate that the present application is not limited to the particular embodiments described herein, but is capable of numerous obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the present application. Therefore, while the present application has been described in connection with the above embodiments, the present application is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the present application, the scope of which is defined by the scope of the appended claims.

Claims

1. A sleep and wake-up circuit comprising:

a connector comprising a power pin and an IGN signal pin;

the power supply end of the power supply chip module is connected with the power supply pin of the connector, and the power supply chip module is used for providing working voltage for each device;

the first power supply pin of the core processor is connected with the output end of the power supply chip module;

the CAN transceiver is connected with the core processor through a bus and is also connected with the connector through a twisted pair; the CAN transceiver further comprises a second power supply pin, a dormant power supply pin, a wake-up pin and a disable control pin, wherein the second power supply pin is connected with the output end of the power chip module, the dormant power supply pin is connected with the power supply pin, the disable control pin is connected with the external enabling end of the power chip module, the wake-up pin is used for controlling the output of the disable control pin, and the external enabling end is used for controlling the working state of the power chip module;

the input end of the IGN signal conversion module is connected with the IGN signal pin, the first output end of the IGN signal conversion module is connected with the wake-up pin, the second output end of the IGN signal conversion module is connected with the general input pin of the core processor, and the IGN signal conversion module is used for controlling the input of the wake-up pin and the input of the general input pin according to the output of the IGN signal pin.

2. The sleep and wake-up circuit of claim 1, wherein the power chip module comprises a first power chip and a second power chip;

the first input pin of the first power chip is connected with the power pin, the first enabling pin of the first power chip is connected with the disabling control pin, the first output pin of the first power chip is connected with the second input pin and the second enabling pin of the second power chip, and the second output pin of the second power chip is connected with the first power supply pin.

3. The sleep and wake-up circuit of claim 2, wherein the second power supply pin of the CAN transceiver comprises a main power supply pin and an auxiliary power supply pin, the main power supply pin being connected to the first output pin, the auxiliary power supply pin being connected to the second output pin.

4. The sleep and wake-up circuit of claim 1, wherein the IGN signal conversion module comprises a first signal conversion unit and a second signal conversion unit, an input end of the first signal conversion unit is connected to the IGN signal pin, an output end of the first signal conversion unit is connected to the wake-up pin, an input end of the second signal conversion unit is connected to an output end of the first signal conversion unit, and an output end of the second signal conversion unit is connected to the general input pin;

the first signal conversion unit is used for controlling the conduction state of the second signal conversion unit, and the IGN signal conversion module is used for controlling the input of the wake-up pin and the input of the general input pin according to the conduction state of the first signal conversion unit and the conduction state of the second signal conversion unit.

5. The sleep and wake-up circuit of claim 4, wherein the first signal conversion unit comprises a first current limiting resistor, a first pull-down resistor, a filter capacitor, a first switch tube and a first pull-up resistor, one end of the first current limiting resistor is connected with the IGN signal pin, the other end of the first current limiting resistor is connected with the control end of the first switch tube, one end of the first pull-down resistor is connected with the control end of the first switch tube, the other end of the first pull-down resistor is grounded, the filter capacitor is connected in parallel with the first pull-down resistor, the input end of the first switch tube is connected with a power supply voltage through the first pull-up resistor, the input end of the switch tube is connected with the wake-up pin, and the output end of the first switch tube is grounded.

6. The sleep and wake-up circuit of claim 5, wherein the first switching tube is an NPN transistor, a base terminal of the NPN transistor is connected to the first current limiting resistor as the control terminal, a collector terminal of the NPN transistor is connected to the wake-up pin as the input terminal, and an emitter of the NPN transistor is grounded as the output terminal.

7. The sleep and wake-up circuit according to claim 4 or 5, wherein the second signal conversion unit comprises a second current limiting resistor, a second switching tube, a second pull-up resistor and a second pull-down resistor, one end of the second current limiting resistor is connected with the output end of the first signal conversion unit, the other end of the second current limiting resistor is connected with the control end of the second switching tube, the input end of the second switching tube is connected with an operating voltage through the second pull-up resistor, the output end of the second switching tube is grounded through the second pull-down resistor, and the output end of the second switching tube is further connected with the general input pin.

8. The sleep and wake-up circuit of claim 7, wherein the second switching tube is a PNP transistor, a base terminal of the PNP transistor is connected to the second current limiting resistor as the control terminal, an emitter terminal of the PNP transistor is connected to the second pull-up resistor as the input terminal, and a collector terminal of the PNP transistor is connected to the second pull-down resistor as the output terminal.

9. A circuit board comprising a sleep and wake-up circuit as claimed in any one of claims 1-8.

10. An automotive controller for switching the operation mode of an automotive control system, characterized in that the automotive controller comprises a circuit board according to claim 9.