CN116170706A

CN116170706A - Analog-to-digital conversion circuit for optimizing dual conversion gain operation and operation method thereof

Info

Publication number: CN116170706A
Application number: CN202211480762.7A
Authority: CN
Inventors: 田在熏; 权赫彬; 周雄
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2021-11-25
Filing date: 2022-11-23
Publication date: 2023-05-26

Abstract

Disclosed is a circuit comprising: the first amplifier generates a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal and generates a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal, and the second amplifier generates a third output signal based on the first output signal and a fourth output signal based on the second output signal, the first conversion gain being higher than the second conversion gain, and a first power current of the first amplifier when comparing the first pixel signal and the first ramp signal is different from a second power current of the first amplifier when comparing the second pixel signal and the second ramp signal.

Description

Analog-to-digital conversion circuit for optimizing dual conversion gain operation and operation method thereof

Cross Reference to Related Applications

The U.S. non-provisional patent application claims priority from korean patent application No. 10-2021-0164970 filed on 25 th 11 th year 2021 and korean patent application No. 10-2022-0059736 filed on 16 th 5 th year 2022, which disclosures are incorporated herein by reference in their entireties.

Technical Field

Embodiments of the present disclosure relate to analog-to-digital converters, and more particularly, to analog-to-digital conversion circuits for optimizing dual conversion gain operation and methods of operation thereof.

Background

Types of image sensors include Charge Coupled Device (CCD) image sensors, complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS), and the like. The CMOS image sensor generates pixel values using CMOS transistors to generate electric signals by converting light energy into electric signals using a photoelectric conversion element (or device) included for each pixel. The CMOS image sensor obtains information about a captured/photographed image by using an electric signal generated for each pixel.

An analog-to-digital converter (ADC) receives an analog input voltage generated for a pixel and converts the received analog input voltage to a digital signal. The converted digital signal may be provided to other devices. ADCs may be used in a variety of signal processing devices. As the performance of signal processing devices increases, there is now a need for increased resolution of analog signals. Thus, ADCs are used that are capable of processing many signals simultaneously or within the same period of time or that provide improved resolution for each signal. However, ADCs can result in increased power consumption.

Disclosure of Invention

Embodiments of the present disclosure provide an analog-to-digital conversion circuit for optimizing current consumption of a dual conversion gain operation and time taken to perform the dual conversion gain operation, an operation method thereof, and an image sensor including the same.

According to some embodiments, a circuit comprises: a first amplifier configured to generate a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal, and to generate a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal; and a second amplifier configured to generate a third output signal based on the first output signal and a fourth output signal based on the second output signal; and a counter configured to count pulses of the third output signal and the fourth output signal and output the count result as a digital signal. The first conversion gain is higher than the second conversion gain. The first power current of the first amplifier when comparing the first pixel signal and the first ramp signal is different from the second power current of the first amplifier when comparing the second pixel signal and the second ramp signal.

According to some embodiments, an image sensor includes: a pixel array configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing the floating diffusion region; a ramp signal generator configured to generate a first ramp signal and a second ramp signal; and an analog-to-digital conversion circuit configured to output a digital signal based on the first pixel signal and the second pixel signal. The analog-to-digital conversion circuit includes an amplifier configured to generate a first output signal by comparing the first pixel signal and the first ramp signal, and to generate a second output signal by comparing the second pixel signal and the second ramp signal. The first conversion gain is higher than the second conversion gain. The first power current of the amplifier when comparing the first pixel signal and the first ramp signal is different from the second power current of the amplifier when comparing the second pixel signal and the second ramp signal.

According to some embodiments, the analog-to-digital conversion circuit comprises an amplifier. The operation method of the analog-to-digital conversion circuit comprises the following steps: generating, at the amplifier, a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal based on a first power current; generating, at the amplifier, a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal based on a second power current; and adjusting the power current of the amplifier, and the first conversion gain is higher than the second conversion gain.

According to some embodiments, a circuit comprises: a first transistor configured to receive a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain; a second transistor configured to receive the first ramp signal and the second ramp signal; a first current source connected to the first source terminal of the first transistor and the second source terminal of the second transistor at a common node and configured to output a first sub-power current; a switch connected to the first source terminal and the second source terminal at a common node; and a second current source connected to the switch and configured to output a second sub-power current. The first conversion gain is higher than the second conversion gain. The first power current of the circuit when comparing the first pixel signal and the first ramp signal is different from the second power current of the circuit when comparing the second pixel signal and the second ramp signal. When comparing the first pixel signal and the first ramp signal, the switch is turned on and the first power current is equal to the sum of the first sub-power current and the second sub-power current. When comparing the second pixel signal and the second ramp signal, the switch is turned off and the second power current is equal to the first sub-power current. The first output signal is generated by comparing the first pixel signal with the first ramp signal, and the second output signal is generated by comparing the second pixel signal with the second ramp signal.

Drawings

The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

Fig. 1 shows an example of a configuration of an image processing block according to an embodiment of the present disclosure.

Fig. 2 shows an example of a configuration of an image sensor of the image processing block of fig. 1.

Fig. 3 is a circuit diagram illustrating an example of one pixel group among pixel groups of a pixel array of the image sensor of fig. 2.

Fig. 4A is a circuit diagram illustrating a floating diffusion region in a high conversion gain condition in which the dual conversion transistors of the pixel group of fig. 3 are turned off.

Fig. 4B is a circuit diagram showing the floating diffusion region in a low conversion gain condition in which the double conversion transistor of the pixel group of fig. 3 is turned on.

Fig. 5 shows an example of a configuration of an analog-to-digital conversion circuit of the image sensor of fig. 2.

Fig. 6 is a circuit diagram showing an example of the first amplifier of the analog-to-digital conversion circuit of fig. 5.

Fig. 7A is a timing chart showing a procedure in which the ADC circuit of the analog-to-digital conversion circuit of fig. 5 processes a pixel signal depending on a reset-signal-reset (RSSR) method.

Fig. 7B is a timing chart showing a procedure in which the ADC circuit of the analog-to-digital conversion circuit of fig. 5 processes a pixel signal depending on a reset-reset-signal (RRSS) method.

Fig. 8A shows an example in which the offset of the RAMP signal RAMP is adjusted in the timing chart of fig. 7A.

Fig. 8B shows an example in which the offset of the RAMP signal RAMP is adjusted in the timing chart of fig. 7B.

Fig. 8C shows another example in which the offset of the RAMP signal RAMP is adjusted in the timing chart of fig. 7B.

Fig. 9 is a flowchart illustrating a method of operation of an analog-to-digital conversion (ADC) circuit for optimizing dual conversion gain operation according to an embodiment of the disclosure.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that the teachings of the present disclosure are readily implemented by those skilled in the art.

In the detailed description, components described with reference to the terms "unit," "module," "block," "machine," or the like and functional blocks shown in the drawings will be implemented in software, hardware, or a combination thereof. For example, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include circuitry, electronic circuitry, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

Fig. 1 shows an example of a configuration of an image processing block 10 according to an embodiment of the present disclosure. The image processing block 10 may be implemented as part of various electronic devices, such as smartphones, digital cameras, laptop computers, and desktop computers. The image processing block 10 may include a lens 12, an image sensor 14, an ISP front end block 16 (image signal processor front end block), and an image signal processor 18.

The light may be reflected by an object, a landscape, or the like, which is a target of photographing, and the lens 12 may receive the reflected light. The image sensor 14 may generate an electrical signal based on light received through the lens 12. For example, the image sensor 14 may be implemented with a Complementary Metal Oxide Semiconductor (CMOS) image sensor or the like. For example, the image sensor 14 may be a multi-pixel image sensor having a two-pixel structure or a four-cell structure.

The image sensor 14 may include an array of pixels. The pixel array may convert light into an electrical signal and may generate a pixel value for each pixel. The ratio at which light is converted into an electrical signal (e.g., voltage) may be defined as the conversion gain. Specifically, the pixel array may generate the pixel signal under the low conversion gain condition and the high conversion gain condition by using a change in the conversion gain, i.e., the dual conversion gain.

Further, the image sensor 14 may include analog-to-digital conversion (ADC) circuitry for performing correlated double sampling (correlated double sampling, CDS) operations on the pixel values. The configuration of the image sensor 14 will be described in detail with reference to fig. 2.

The ISP front end block 16 may perform preprocessing on the electrical signals output from the image sensor 14 such that the inputs of the image signal processor 18 are suitable for processing by the image signal processor 18. Further, based on the output of the image sensor 14, the ISP front end block 16 of the present disclosure may selectively perform preprocessing on the (e.g., first) electrical signal corresponding to the low conversion gain condition and perform preprocessing on the (e.g., second) electrical signal corresponding to the high conversion gain condition.

The image signal processor 18 may generate image data associated with a photographed subject or landscape by appropriately processing the electrical signals preprocessed by the ISP front-end block 16. To this end, the image signal processor 18 may perform various processing operations such as color correction, automatic white balance, gamma correction, color saturation correction, formatting, bad pixel correction, and tone correction.

One lens 12, one image sensor 14, and one ISP front end block 16 are shown in fig. 1. However, in another embodiment, the image processing block 10 may include a plurality of lenses, a plurality of image sensors, and a plurality of ISP front end blocks. In this case, the plurality of lenses may have different fields of view. Further, the plurality of image sensors may have different functions, different performances, and/or different characteristics, and may include pixel arrays of different configurations, respectively.

Fig. 2 shows an example of the configuration of the image sensor 14 of the image processing block of fig. 1. The image sensor 100 may correspond to the image sensor 14 of fig. 1, and may include a pixel array 110, a row driver 120, a ramp signal generator 130, a voltage buffer 140, an ADC circuit 150, a timing controller 160, and a buffer 170.

The pixel array 110 may include a plurality of pixels arranged in a matrix form, i.e., arranged along rows and columns. In the context of pixel array 110, references to pixels should be understood as references to discrete hardware circuit elements or discrete combinations of hardware circuit elements for each pixel represented in the pixel array. Each of the plurality of pixels may include a photoelectric conversion element. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or the like.

The pixel array 110 may include a plurality of pixel groups PG. Each pixel group PG may include two or more pixels, i.e., a plurality of pixels. A plurality of pixels constituting the pixel group PG may share one floating diffusion region or a plurality of floating diffusion regions. Fig. 2 shows an example in which the pixel array 110 includes pixel groups PG arranged in a matrix form of four rows and four columns (i.e., includes 4×4 pixel groups PG). However, the present disclosure is not limited thereto.

The pixel group PG may include pixels of the same color. For example, the pixels of the pixel group PG may include red pixels that convert light of a red spectrum into an electrical signal, green pixels that convert light of a green spectrum into an electrical signal, or blue pixels that convert light of a blue spectrum into an electrical signal. For example, pixels constituting the pixel array 110 may be arranged in a four Bayer (tetra-Bayer) pattern.

The pixels of the pixel array 110 may be configured to output pixel signals through the column lines CL1 to CL4 depending on the intensity or amount of light received from the outside. For example, the pixel array 110 may be configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing the floating diffusion region. For example, the pixel signal may be an analog signal corresponding to the intensity or amount of light received from the outside.

As described with reference to fig. 1, the pixel array 110 may generate pixel signals under a low conversion gain condition and a high conversion gain condition depending on the ambient brightness of the subject. Hereinafter, the pixel signal generated under the low conversion gain condition may be referred to as a low conversion gain pixel signal, and the pixel signal generated under the high conversion gain condition may be referred to as a high conversion gain pixel signal. The pixel signals may be provided to the ADC circuit 150 through a voltage buffer (e.g., a source follower) and then through column lines CL1 to CL 4. The ADC circuit 150 may be configured to output a digital signal based on a pixel signal (such as based on a first pixel signal corresponding to a first conversion gain or based on a second pixel signal corresponding to a second conversion gain). The pixel array 110 may change the conversion gain by turning on or off the double conversion transistor, which will be described in detail with reference to fig. 3, 4A, and 4B.

The row driver 120 may select and drive a row of the pixel array 110. The row driver 120 may decode the address and/or control signals generated by the timing controller 160 and may generate control signals for selecting and driving the rows of the pixel array 110. For example, the control signal may include a signal for selecting a pixel, a signal for resetting a floating diffusion region, and the like.

The RAMP signal generator 130 may generate the RAMP signal RAMP under the control of the timing controller 160. For example, the ramp signal generator 130 may operate in response to a control signal such as a ramp enable signal. When the RAMP enable signal is activated, the RAMP signal generator 130 may generate the RAMP signal RAMP depending on preset values (e.g., a start level, an end level, and a slope). In other words, the RAMP signal RAMP may be a signal that increases or decreases along a preset slope during a specific time. The RAMP signal RAMP may be provided to the ADC circuit 150 through the voltage buffer 140.

The ADC circuit 150 may receive pixel signals from a plurality of pixels through column lines CL1 to CL 4. The ADC circuit 150 may receive the RAMP signal RAMP from the RAMP signal generator 130 through the voltage buffer 140. The ADC circuit 150 may operate based on a Correlated Double Sampling (CDS) technique for obtaining a reset signal and an image signal from a received pixel signal and extracting a difference between the reset signal and the image signal as an effective signal component. The ADC circuit 150 may include a plurality of comparators COMP and a plurality of counters CNT.

In detail, each of the comparators COMP may compare a reset signal of the pixel signal and a RAMP signal RAMP, may compare an image signal of the pixel signal and the RAMP signal RAMP, and may perform Correlated Double Sampling (CDS) of the comparison result. Each of the counters CNT may count pulses of a signal subjected to correlated double sampling, and may output a count result as a digital signal. An example in which the ADC circuit 150 includes four comparators COMP and four counters CNT is shown in fig. 2, but the present disclosure is not limited thereto.

Further, the ADC circuit 150 of the present disclosure can make the current consumption in the comparison operation for the low conversion gain pixel signal different from the current consumption in the comparison operation for the high conversion gain pixel signal. Further, the RAMP signal generator 130 may generate the RAMP signal RAMP in the comparison operation for the low conversion gain pixel signal and the RAMP signal RAMP in the comparison operation for the high conversion gain pixel signal so as to be different from each other. Further, even if the pixel signals have the same conversion gain, the RAMP signal RAMP may be generated differently in the comparison operation for the reset signal and the comparison operation for the image signal.

The timing controller 160 may generate control signals and/or clocks for controlling the operation and/or timing of each of the row driver 120, the ramp signal generator 130, and the ADC circuit 150.

The buffer 170 may include a memory MEM and a sense amplifier SA. The memory MEM may store a digital signal output from a corresponding counter CNT of the ADC circuit 150. The sense amplifier SA may sense and amplify the digital signal stored in the memory MEM. The sense amplifier SA may output the amplified digital signal as image data IDAT. The image data IDAT may be provided to the ISP front-end block 16 of fig. 1.

Fig. 3 is a circuit diagram illustrating an example of one of the pixel groups PG of the pixel array 110 of the image sensor of fig. 2. Fig. 4A is a circuit diagram showing the floating diffusion FD1 in a high conversion gain condition in which the double conversion transistor DC of the pixel group of fig. 3 is turned off. Fig. 4B is a circuit diagram showing floating diffusion regions FD1 and FD2 in a low conversion gain condition in which the double conversion transistor DC of the pixel group of fig. 3 is turned on.

For example, the pixel group PG may include pixels PX1 to PX4, photoelectric conversion elements PD1 to PD4, transfer transistors Tx1 to Tx4, a reset transistor RST, a double conversion transistor DC, a driving transistor Dx, and a selection transistor SEL. An example in which the pixel group PG has a four-cell (tetracell) structure in which four pixels PX1 to PX4 include photoelectric conversion elements PD1 to PD4, respectively, is shown in fig. 3, but the present disclosure is not limited thereto. For example, the pixel group PG may be implemented to have various different structures.

The first pixel PX1 may include a first photoelectric conversion element PD1 and a first transfer transistor Tx1, and each of the remaining pixels PX2, PX3, and PX4 may also include similar components/elements. The pixels PX1 to PX4 may share the reset transistor RST, the double conversion transistor DC, the driving transistor Dx, and the selection transistor SEL. Further, the pixels PX1 to PX4 may share the first floating diffusion FD1.

The first floating diffusion FD1 or the second floating diffusion FD2 may accumulate (or collect) charges corresponding to the amount of incident light. When the transfer transistors Tx1 to Tx4 are turned on by the transfer signals VT1 to VT4, respectively, the first floating diffusion FD1 or the second floating diffusion FD2 may accumulate (or collect) charges supplied from the photoelectric conversion elements PD1 to PD 4. Since the first floating diffusion FD1 is connected to the gate terminal of the driving transistor Dx operating as a source follower amplifier, a voltage corresponding to the charge accumulated in the first floating diffusion FD1 can be formed. For example, the capacitance of the first floating diffusion region FD1 is depicted as a first capacitance CFD1.

The double conversion transistor DC may be driven by a double conversion signal VDC. When the double conversion transistor DC is turned off, the capacitance of the first floating diffusion FD1 may correspond to the first capacitance CFD1. Under normal circumstances, since the first floating diffusion FD1 is not easily saturated, it is not necessary to increase the capacitance (i.e., CFD 1) of the first floating diffusion FD1. In this case, the double conversion transistor DC may be turned off.

However, in a high-luminance environment, the first floating diffusion FD1 may be easily saturated. To prevent saturation, the double conversion transistor DC may be turned on such that the first floating diffusion FD1 and the second floating diffusion FD2 are electrically connected. As shown in each of fig. 4A and 4B, each of the first and second floating diffusion regions FD1 and FD2 may be connected to a different capacitor representing a capacitance value such that the pixel group PG of the pixel array 110 includes one or more capacitors connected to the floating diffusion regions in order to obtain a first capacitance value CFD1 in the case of the first floating diffusion region FD1 and a second capacitance value CFD2 in the case of the second floating diffusion region FD2. In this case, the capacitances of the floating diffusion regions FD1 and FD2 may be increased to the sum of the first capacitance CFD1 and the second capacitance CFD2. For example, the pixel array 110 may be configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing the floating diffusion region. For example, the first pixel signal may correspond to the charge stored in the floating diffusion region FD1 having the first capacitance value, and the second pixel signal may correspond to the sum of the charges stored in the floating diffusion region FD1 and the second floating diffusion region FD2 having the second capacitance value.

The transfer transistors Tx1 to Tx4 may be driven by transfer signals VT1 to VT4, respectively. The transfer transistors Tx1 to Tx4 may transfer charges generated (or accumulated) by the photoelectric conversion elements PD1 to PD4 to the first floating diffusion region FD1 or the second floating diffusion region FD2. For example, first terminals of the transfer transistors Tx1 to Tx4 may be connected to the photoelectric conversion elements PD1 to PD4, respectively, and second terminals thereof may be commonly connected to the first floating diffusion FD 1.

The reset transistor RST may be driven by a reset signal VRST and may supply a power supply voltage VDD to the first floating diffusion FD1 or the second floating diffusion FD2. In this way, the charge accumulated in the first floating diffusion FD1 or the second floating diffusion FD2 can be moved to the terminal of the power supply voltage VDD, and the voltage of the first floating diffusion FD1 or the second floating diffusion FD2 can be reset.

The driving transistor Dx may amplify the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2, and may generate a pixel signal PIX corresponding to the amplified result. The selection transistor SEL may be driven by a selection signal VSEL, and may select pixels to be read in units of rows. When the selection transistor SEL is turned on, the pixel signal PIX may be output to the ADC circuit 150 of fig. 2 through the column line CL.

Fig. 5 shows an example of a configuration of an ADC circuit 150 (analog-to-digital conversion circuit) of the image sensor of fig. 2. The ADC circuit 150 may include a comparator 151 and a counter 152. The ADC circuit 150 may convert and output the analog pixel signal PIX from the pixel array 110 into a digital signal DS. For clarity of description and brevity of the drawings, an example in which the pixel array 110 includes only one pixel is shown in fig. 5, and the configuration and function of the pixel array 110 are the same as described with reference to fig. 3, 4A and 4B.

In detail, as described with reference to fig. 2, the comparator 151 may compare the reset signal and the RAMP signal RAMP of the pixel signal PIX in the first and fourth operation periods, may compare the image signal and the RAMP signal RAMP of the pixel signal PIX in the second and third operation periods, and may perform Correlated Double Sampling (CDS) of the comparison result. The counter 152 may count pulses of a signal subjected to Correlated Double Sampling (CDS), and may output the count result as a digital signal. Fig. 5 will be described with reference to fig. 2, 3, 4A, and 4B.

For example, the comparator 151 may have a two-stage structure including two amplifiers (i.e., a first amplifier 151_1 and a second amplifier 151_2). Each of the first and second amplifiers 151_1 and 151_2 may be implemented as an operational transconductance amplifier (operational transconductance amplifier, OTA). However, the present disclosure is not limited thereto. For example, the comparator 151 may have a structure including more amplifiers. In addition, the ADC circuit 150 may include a plurality of comparators and a plurality of counters, although one comparator 151 and one counter 152 are shown in fig. 5 for clarity of description.

The first amplifier 151_1 may receive the pixel signal PIX from the pixel array 110 through the column line CL, and may receive the RAMP signal RAMP from the RAMP signal generator 130 through the voltage buffer 140. The first amplifier 151_1 may output a first output signal ota1_out based on the received signal. For example, in a period in which the level of the RAMP signal RAMP is higher than the level of the pixel signal PIX, the first amplifier 151_1 may output the first output signal ota1_out having a high level. In a period in which the level of the RAMP signal RAMP is lower than the level of the pixel signal PIX, the first amplifier 151_1 may output the first output signal ota1_out having a low level. Further, when the first amplifier 151_1 compares the reset signal of the pixel signal PIX and the RAMP signal RAMP, and when the first amplifier 151_1 compares the image signal of the pixel signal PIX and the RAMP signal RAMP, both may perform the comparison operation of the above-described comparator 151.

As an example operation of the first amplifier 151_1, the first amplifier 151_1 may be configured to compare a reset signal and a ramp signal of a pixel signal in some operation periods, and may be configured to compare an image signal and a ramp signal of a pixel signal in other operation periods. As one specific example, the first amplifier 151_1 may be configured to: comparing a reset signal of the first pixel signal and the first ramp signal in a first operation period; comparing the image signal of the first pixel signal with the first ramp signal in a second operation period; comparing the image signal of the second pixel signal and the second ramp signal in a third operation period; and comparing the reset signal of the second pixel signal and the second ramp signal in the fourth operation period. In another example, the first amplifier 151_1 may be configured to: comparing the reset signal of the second pixel signal and the second ramp signal in the first operation period; comparing the reset signal of the first pixel signal and the first ramp signal in the second operation period; comparing the image signal of the first pixel signal and the first ramp signal in a third operation period; and comparing the image signal of the second pixel signal with the second ramp signal in the fourth operation period.

The second amplifier 151_2 may amplify the first output signal ota1_out and may output the second output signal ota2_out as a comparison signal. For example, the second output signal ota2_out may be an inverted version of the first output signal ota1_out. In other words, the second amplifier 151_2 may output the second output signal ota2_out having a low level during a high level of the first output signal ota1_out, and may output the second output signal ota2_out having a high level during a low level of the first output signal ota1_out.

In the following description, when the comparator 151 performs a comparison operation, a transition of the voltage level of the first output signal ota1_out or the second output signal ota2_out from a high level to a low level or from a low level to a high level may be referred to as a decision of the ADC circuit 150. In other words, the decision of the ADC circuit 150 may refer to when the voltage level of the first output signal ota1_out or the second output signal ota2_out changes from high level to low level or from low level to high level. In the auto-zero period before the comparison operation is performed, the comparator 151 may be initialized in response to the auto-zero signal AZ, and then the comparison operation may be performed again.

The counter 152 may operate under the control of the timing controller 160, may count pulses of the second output signal ota2_out, and may output the count result as the digital signal DS. The counter 152 may receive a counter clock signal cnt_clk and an inversion signal CONV for inverting an inner portion of the counter 152. For example, the counter 152 may operate in response to control signals such as a counter clock signal cnt_clk and an inversion signal CONV.

For example, the counter 152 may include an up/down counter, a bit-wise counter, and the like. The operation of the bit-wise counter may be similar to that of the up/down counter. For example, the bitwise-inversion counter may perform a function of performing only up-counting, and a function of converting all internal parts of the counter to obtain a complement of 1 when a specific signal is input thereto. The bit-wise inverting counter may perform a reset count and then may invert the reset count result to convert to a complement of 1, i.e., a negative value.

Through the above-described operation of the ADC circuit 150, a low conversion gain digital signal corresponding to a low conversion gain pixel signal and a high conversion gain digital signal corresponding to a high conversion gain pixel signal can be output. The image data IDAT may be generated based on the low conversion gain digital signal and the high conversion gain digital signal. The image data IDAT thus generated may correspond to a High Dynamic Range (HDR) image having a high dynamic range. The quality of the HDR image may be determined by the signal-to-noise ratio (SNR) of the image sensor 100.

SNR may be affected by the amplitude of the signal and the amplitude of the noise; as the signal amplitude becomes larger and the noise amplitude becomes smaller, the SNR may become higher. For example, the signal amplitude may be determined by the level of the power current flowing to the first amplifier 151_1. For example, noise that can occur in the process of generating an image may include thermal noise, flicker noise, dark noise, shot noise, quantization error, stabilization error, and the like. Specifically, under low conversion gain conditions, shot noise caused by light may be the most important factor in determining SNR. Further, under the low conversion gain condition, since shot noise included in the SNR is large, even if the signal amplitude is reduced, the SNR is not significantly reduced to such an extent that the quality of the image data is affected.

That is, the ADC circuit 150 may be configured such that the current consumption in the comparison operation for the low conversion gain pixel signal is smaller than that in the comparison operation for the high conversion gain pixel signal, insofar as the quality of the image data is uniformly maintained without a large decrease in SNR. For example, the level of the power current flowing to the first amplifier 151_1 or the second amplifier 151_2 in the comparison operation for the low conversion gain pixel signal may be adjusted to be lower than that in the comparison operation for the high conversion gain pixel signal. In this way, current consumption in dual conversion gain operation can be optimized, and power consumption of the ADC circuit 150 can be reduced. The current consumption optimizing operation will be described in detail with reference to fig. 6.

Furthermore, when the ambient brightness of the object is small, shot noise may be large enough; in this case, even if the comparison operation for the low conversion gain pixel signal is not completely performed (i.e., even if Correlated Double Sampling (CDS) for the low conversion gain pixel signal is not completely performed), the quality of the image data is not significantly affected. In this case, when comparing the image signal of the low conversion gain pixel signal and the RAMP signal RAMP, a part of the count period may be omitted by increasing or decreasing the offset of the RAMP signal RAMP. Therefore, the period of the comparison operation for the low conversion gain pixel signal can be shortened, and the time taken to perform the double conversion gain operation (hereinafter referred to as "required time") can be reduced. The required time optimizing operation will be described in detail with reference to fig. 7A, 7B, 8A, 8B, and 8C.

Fig. 6 is a circuit diagram illustrating an example of the first amplifier 151_1 of the ADC circuit 150 of fig. 5. The first amplifier 200a may include a plurality of transistors (including a first transistor TR11, a second transistor TR12, a third transistor TR13, a fourth transistor TR4, and a fifth transistor TR 15), a first current source 210, a second current source 220, and a switch SW. For example, the first transistor TR11, the second transistor TR12, and the fifth transistor TR15 may be NMOS transistors, and the third transistor TR13 and the fourth transistor TR14 may be PMOS transistors. However, the present disclosure is not limited thereto. The first transistor TR11, the second transistor TR12, the third transistor TR13, the fourth transistor TR14, and the fifth transistor TR15 may be implemented with transistors of types different from those shown in fig. 6.

Referring to fig. 6, the RAMP signal RAMP may be input to the gate terminal of the first transistor TR11, and the pixel signal PIX may be input to the gate terminal of the second transistor TR 12. The source terminals of the first and second transistors TR11 and TR12 may be commonly connected with the first current source 210 and the switch SW at a common node COMM. For example, the third transistor TR13 and the fourth transistor TR14 may be connected in the form of a current mirror. The sum of currents flowing to the first transistor TR11 and the second transistor TR12 may be equal to the power current ISS1.

The gate and drain terminals of the third transistor TR13 and the drain terminal of the first transistor TR11 may be commonly connected to the second output node OUT12, and the drain terminal of the fourth transistor TR14 and the drain terminal of the second transistor TR12 may be commonly connected to the first output node OUT 11. The fifth transistor TR15 may be connected between the first output node OUT11 and the second output node OUT 12. For example, the fifth transistor TR15 may limit a voltage level of the signal output from the first output node OUT 11.

The first output signal ota1_out may be output from the first output node OUT 11. For example, in a period in which the level of the RAMP signal RAMP is higher than the level of the pixel signal PIX, the first output signal ota1_out may have a high level. In a period in which the level of the RAMP signal RAMP is lower than the level of the pixel signal PIX, the first output signal ota1_out may have a low level. The first output signal ota1_out may be provided to the second amplifier 151_2 of fig. 5.

The first current source 210 is configured to output and may output a first sub-power current ISS11. The second current source 220 is configured to output and may output the second sub-power current ISS12 when the switch SW is turned on, and is not operated when the switch SW is turned off. That is, when the switch SW is turned on, the power current ISS1 may be equal to the sum of the first and second sub-power currents ISS11 and ISS 12. When the switch SW is turned off, the power current ISS1 may be equal to only the first sub power current ISS11.

For example, when the first amplifier 200a performs a comparison operation on a low conversion gain pixel signal, the switch SW may be turned off so that only the first current source 210 operates. Thus, the power current ISS1 may be equal to the first sub-power current ISS11. In contrast, when the first amplifier 200a performs a comparison operation on the high conversion gain pixel signal, the switch SW may be turned on so that both the first current source 210 and the second current source 220 operate. Thus, the power current ISS1 may be equal to the sum of the first sub-power current ISS11 and the second sub-power current ISS 12.

For example, the magnitudes of the first and second sub-power currents ISS11 and ISS12 may be differently determined depending on the magnitude of shot noise. Furthermore, the ratio of the first sub-power current ISS11 and the second sub-power current ISS12 may be optimized in designing the first amplifier 200 a. Further, the switch SW may be turned on or off in response to a signal that is deactivated when a comparison operation for a low conversion gain pixel signal is performed and activated when a comparison operation for a high conversion gain pixel signal is performed. In this way, the current consumption in the dual conversion gain operation can be optimized by the operation of the first amplifier 200a, and the current consumption in the comparison operation for the low conversion gain pixel signal can be reduced. This may mean that the power consumption of the ADC circuit 150 is reduced.

An embodiment of adjusting the power current of the first amplifier 151_1 of fig. 5 when performing a comparison operation for a low conversion gain pixel signal is described with reference to fig. 6, but the present disclosure is not limited thereto. For example, the power current of the first amplifier 151_1 may be adjusted in a different method from that described with reference to fig. 6. Further, in the comparison operation for the low conversion gain pixel signal and the comparison operation for the high conversion gain pixel signal, the power current of the second amplifier 151_2 of fig. 5 may be differently adjusted.

Fig. 7A is a timing chart showing a procedure in which the ADC circuit 150 of the analog-to-digital conversion circuit of fig. 5 processes the pixel signal PIX depending on a reset-signal-reset (RSSR) method. Fig. 7B is a timing chart showing a procedure in which the ADC circuit 150 of the analog-to-digital conversion circuit of fig. 5 processes the pixel signal PIX depending on a reset-signal (RRSS) method. Next, fig. 7A and 7B will be described together with fig. 5.

The 1H period is shown in fig. 7A and 7B. The 1H period may refer to a time that should be basically ensured to drive a plurality of pixels of the pixel array 110 in a row unit. For example, the 1H period may include a high conversion gain reset signal period HRST, a high conversion gain image signal period HSIG, a low conversion gain reset signal period LRST, and a low conversion gain image signal period LSIG.

Referring to fig. 7A, the high conversion gain Reset signal period HRST, the high conversion gain image signal period HSIG, the low conversion gain image signal period LSIG, and the low conversion gain Reset signal period LRST may be sequentially performed (Reset-signal-Reset (Reset-Sig-Reset): RSSR).

The high conversion gain reset signal VHRST, the high conversion gain image signal VHSIG, the low conversion gain image signal VLSIG, and the low conversion gain reset signal VLRST may be output as components of the pixel signal PIX in a plurality of periods HRST, HSIG, LSIG and LRST, respectively, to be sequentially converted into digital signals.

First, a reset signal VRST of a logic high level is applied to the gate of the reset transistor RST, and then a reset signal VRST of a logic low level is applied to the gate of the reset transistor RST. Next, the adjustment between the voltage level of the RAMP signal RAMP and the voltage level of the pixel signal PIX may be performed in response to the auto-zero signal AZ. Then, the logic low level double-conversion signal VDC may be applied to the gate of the double-conversion transistor DC. Accordingly, the high conversion gain reset signal VHRST may be output in the high conversion gain reset signal period HRST. Thereafter, a transfer signal VT of a logic high level may be applied to the gate of the transfer transistor Tx. Accordingly, the high conversion gain image signal VHSIG may be output in the high conversion gain image signal period HSIG.

Next, the adjustment between the voltage level of the RAMP signal RAMP and the voltage level of the pixel signal PIX may be performed again in response to the auto-zero signal AZ. When the reset signal VRST of a logic low level is applied to the gate of the reset transistor RST, the double-conversion signal VDC of a logic high level is applied to the gate of the double-conversion transistor DC, and the transfer signal VT of a logic high level is applied to the gate of the transfer transistor Tx, the low-conversion gain image signal VLSIG may be output in the low-conversion gain image signal period LSIG. After that, a reset signal VRST of a logic high level may be applied to the gate of the reset transistor RST. Accordingly, the low conversion gain reset signal VLRST may be output in the low conversion gain reset signal period LRST.

Referring to fig. 7B, the low conversion gain Reset signal period LRST, the high conversion gain Reset signal period HRST, the high conversion gain image signal period HSIG, and the low conversion gain image signal period LSIG may be sequentially performed (Reset-signal (Reset-Sig): RRSS).

First, a reset signal VRST of a logic high level is applied to the gate of the reset transistor RST, and then a reset signal VRST of a logic low level is applied to the gate of the reset transistor RST. Next, the adjustment between the voltage level of the RAMP signal RAMP and the voltage level of the pixel signal PIX may be performed in response to the auto-zero signal AZ. Then, the double conversion signal VDC of a logic high level may be applied to the gate of the double conversion transistor DC, and thus the low conversion gain reset signal VLRST may be output in the low conversion gain reset signal period LRST. After the adjustment between the voltage level of the RAMP signal RAMP and the voltage level of the pixel signal PIX is performed again in response to the auto-zero signal AZ, the double conversion signal VDC of the logic low level may be applied to the gate of the double conversion transistor DC. Accordingly, the high conversion gain reset signal VHRST may be output in the high conversion gain reset signal period HRST.

Thereafter, a transfer signal VT of a logic high level may be applied to the gate of the transfer transistor Tx. Accordingly, the high conversion gain image signal VHSIG may be output in the high conversion gain image signal period HSIG. Since the double conversion signal VDC of a logic high level is applied to the gate of the double conversion transistor DC and the transfer signal VT of a logic high level is applied to the gate of the transfer transistor Tx, the low conversion gain image signal VLSIG may be output in the low conversion gain image signal period LSIG.

Fig. 8A shows an example in which the offset of the RAMP signal RAMP is adjusted in the timing chart of fig. 7A, and fig. 8B shows an example in which the offset of the RAMP signal RAMP is adjusted in the timing chart of fig. 7B. As described above, when shot noise is sufficiently large, the quality of image data is not significantly affected even if the comparison operation for the low conversion gain pixel signal is not completely performed. In this case, during the LSIG period, the RAMP signal generator (e.g., 130 of fig. 2) may omit a portion of the count by increasing the offset of the RAMP signal RAMP by "a" as shown in fig. 8A or decreasing the offset by "a" as shown in fig. 8B. For example, the ramp signal generator 130 may determine the offset amount "a" to be increased or decreased based on the ratio of the low conversion gain and the high conversion gain.

Referring to fig. 8A, since the offset amount of the RAMP signal RAMP is increased by "a" in the LSIG section, as compared with fig. 7A, some of the comparison operation and count between the low conversion gain image signal VLSIG and the RAMP signal RAMP may be omitted. Accordingly, the length of the LSIG interval of fig. 8A may be shorter than that of the LSIG interval of fig. 7A, and the length of the 1H time interval of fig. 8A may also be shorter than that of the 1H time interval of fig. 7A.

Referring to fig. 8B, since the offset amount of the RAMP signal RAMP is reduced by "a" in the LSIG section as compared with fig. 7B, some of the comparison operation and count between the low conversion gain image signal VLSIG and the RAMP signal RAMP may be omitted. Similarly, the length of the LSIG interval of fig. 8B may be shorter than that of fig. 7B, and the length of the 1H time interval of fig. 8B may also be shorter than that of the 1H time interval of fig. 7B.

Meanwhile, fig. 8C shows another example in which the offset of the RAMP signal RAMP is adjusted in the timing chart of fig. 7B. Referring to fig. 8C, after the end of the HSIG interval, the level of the RAMP signal RAMP may be adjusted to be lower than that (e.g., lowered by a) after the end of the LRST interval or HRST interval. Therefore, as shown in fig. 8B, the same effect as the offset of the RAMP signal RAMP is reduced by a in the LSIG interval can be obtained, and some of the comparison operation and count between the low conversion gain image signal VLSIG and the RAMP signal RAMP can be omitted. Accordingly, the length of the LSIG interval of fig. 8C may be shorter than the interval of the LSIG period of fig. 7B, and the length of the 1H time interval of fig. 8C may also be shorter than the length of the 1H time interval of fig. 7B. By the above operation, the time required for the dual conversion gain operation can be reduced.

Fig. 9 is a flowchart illustrating a method of operation of an analog-to-digital conversion (ADC) circuit for optimizing dual conversion gain operation according to an embodiment of the disclosure. Next, fig. 9 will be described together with fig. 5.

In operation S110, the first amplifier 151_1 may generate an output signal by comparing the ramp signal and the high conversion gain pixel signal corresponding to the high conversion gain condition based on the first power current. In operation S120, the first amplifier 151_1 may generate an output signal by comparing the ramp signal and the low conversion gain pixel signal corresponding to the low conversion gain condition based on the second power current.

In operation S130, the first amplifier 151_1 may adjust a power current. For example, the second power current of the first amplifier 151_1 corresponding to the low conversion gain condition may be adjusted to be smaller than the first power current of the first amplifier 151_1 corresponding to the high conversion gain condition. In order to adjust the power current depending on the conversion gain, the first amplifier 151_1 may be implemented as shown in fig. 6.

According to the embodiments of the present disclosure, the power consumption of the analog-to-digital conversion circuit can be optimized by differently setting the current consumption in the low conversion gain operation and the current consumption in the high conversion gain operation.

Further, according to the embodiments of the present disclosure, the time taken to perform the dual conversion gain operation can be optimized by differently setting the ramp signal in the low conversion gain operation and the ramp signal in the high conversion gain operation.

Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A circuit, comprising:

a first amplifier configured to generate a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal, and to generate a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal;

a second amplifier configured to generate a third output signal based on the first output signal and a fourth output signal based on the second output signal; and

a counter configured to count pulses of the third output signal and the fourth output signal and output a count result as a digital signal,

wherein the first conversion gain is higher than the second conversion gain, and

Wherein a first power current of the first amplifier when comparing the first pixel signal and the first ramp signal is different from a second power current of the first amplifier when comparing the second pixel signal and the second ramp signal.

2. The circuit of claim 1, wherein the first amplifier comprises:

a first current source configured to output a first sub-power current;

a second current source configured to output a second sub-power current; and

a switch connected to the second current source,

wherein when comparing the first pixel signal and the first ramp signal, the switch is turned on and the first power current is equal to the sum of the first sub-power current and the second sub-power current, and

wherein the switch is turned off and the second power current is equal to the first sub-power current when comparing the second pixel signal and the second ramp signal.

3. The circuit of claim 2, wherein the magnitudes of the first and second sub-power currents are determined based on a magnitude of shot noise.

4. The circuit of claim 1, wherein the first amplifier is configured to:

comparing a reset signal of the first pixel signal and the first ramp signal in a first operation period;

Comparing the image signal of the first pixel signal with the first ramp signal in a second operation period;

comparing the image signal of the second pixel signal and the second ramp signal in a third operation period; and

the reset signal of the second pixel signal and the second ramp signal are compared in the fourth operation period.

5. The circuit of claim 1, wherein the first amplifier is configured to:

comparing the reset signal of the second pixel signal and the second ramp signal in the first operation period;

comparing the reset signal of the first pixel signal and the first ramp signal in the second operation period;

comparing the image signal of the first pixel signal and the first ramp signal in a third operation period; and

the image signal of the second pixel signal and the second ramp signal are compared in the fourth operation period.

6. An image sensor, comprising:

a pixel array configured to output a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing the floating diffusion region;

a ramp signal generator configured to generate a first ramp signal and a second ramp signal; and

an analog-to-digital conversion circuit configured to output a digital signal based on the first pixel signal and the second pixel signal,

Wherein, the analog-to-digital conversion circuit includes:

an amplifier configured to generate a first output signal by comparing the first pixel signal and the first ramp signal, and to generate a second output signal by comparing the second pixel signal and the second ramp signal,

wherein a first power current of the amplifier when comparing the first pixel signal and the first ramp signal is different from a second power current of the amplifier when comparing the second pixel signal and the second ramp signal.

7. The image sensor of claim 6, wherein the first pixel signal corresponds to a charge stored in a floating diffusion region having a first capacitance value, and

wherein the second pixel signal corresponds to a charge stored in the floating diffusion region having a second capacitance value.

8. The image sensor of claim 7, wherein the pixel array includes a capacitor connected to the floating diffusion for obtaining a second capacitance value.

9. The image sensor of claim 6, wherein the amplifier comprises:

a first current source configured to output a first sub-power current;

A second current source configured to output a second sub-power current; and

a switch connected to the second current source,

10. The image sensor of claim 9, wherein the magnitudes of the first and second sub-power currents are determined based on a magnitude of shot noise.

11. The image sensor of claim 6, wherein the amplifier is configured to:

12. The image sensor of claim 6, wherein the amplifier is configured to:

13. A method of operation of an analog to digital conversion circuit comprising an amplifier, the method comprising:

generating, at the amplifier, a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal based on a first power current;

generating, at the amplifier, a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal based on a second power current; and

the power current of the amplifier is regulated and,

wherein the first conversion gain is higher than the second conversion gain.

14. The method of claim 13, wherein regulating the power current comprises:

the second power current is regulated to be less than the first power current.

15. The method of claim 14, wherein the amplifier comprises:

A first current source configured to output a first sub-power current;

a second current source configured to output a second sub-power current; and

and a switch connected to the second current source.

16. The method of claim 15, wherein adjusting the second power current to be less than the first power current comprises:

when comparing the first pixel signal and the first ramp signal, turning on the switch; and

the switch is turned off when the second pixel signal and the second ramp signal are compared.

17. The method of claim 16, wherein the first power current is equal to a sum of the first and second sub-power currents, and the second power current is equal to the first sub-power current.

18. The method of claim 15, wherein the magnitudes of the first and second sub-power currents are determined based on a magnitude of shot noise.

19. The method of claim 13, wherein the generating of the first pixel signal comprises:

comparing a reset signal of the first pixel signal and the first ramp signal in a first operation period; and

in a second operation period subsequent to the first operation period, the image signal of the first pixel signal and the first ramp signal are compared,

Wherein the generating of the second pixel signal comprises:

in a third operation period subsequent to the second operation period, comparing the image signal of the second pixel signal with the second ramp signal; and

in a fourth operation period after the third operation period, the reset signal of the second pixel signal and the second ramp signal are compared.

20. The method of claim 13, wherein the generating of the first pixel signal comprises:

wherein the generating of the second pixel signal comprises:

in a third operation period before the first operation period, comparing the reset signal of the second pixel signal with the second ramp signal; and

in a fourth operation period subsequent to the second operation period, the image signal of the second pixel signal and the second ramp signal are compared.