CN116166595A - Data transmission system, method and chip for SOC bus - Google Patents

Data transmission system, method and chip for SOC bus Download PDF

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Publication number
CN116166595A
CN116166595A CN202310460082.7A CN202310460082A CN116166595A CN 116166595 A CN116166595 A CN 116166595A CN 202310460082 A CN202310460082 A CN 202310460082A CN 116166595 A CN116166595 A CN 116166595A
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Prior art keywords
write transaction
queue
write
soc bus
monitoring
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CN202310460082.7A
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CN116166595B (en
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王少虎
张力航
耿平
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Shanghai Lichi Semiconductor Co ltd
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Shanghai Lichi Semiconductor Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data transmission system, method and chip for SOC bus, the data transmission system for SOC bus includes: the monitoring module is configured to monitor the write transaction on the SOC bus and output the write transaction needing to be split; the monitoring queue module is configured to receive the write transaction needing to be split, store the write transaction as a monitoring queue and output the monitoring queue; and the SOC bus adaptation module comprises an address channel queue, is configured to receive the write transaction on the SOC bus and the monitoring queue sent by the monitoring queue module, performs mode switching based on the information in the monitoring queue and the current address channel queue, and outputs a write transaction data packet. According to the data transmission system, for data transmission of the SOC bus, automatic splitting of write transactions can be achieved, byte enabling limitation which must meet PCIE TLP definition is removed, accordingly PCIE transmission data errors can be effectively avoided, and link interruption phenomenon after multiple retries is avoided.

Description

Data transmission system, method and chip for SOC bus
Technical Field
The present disclosure relates to the field of data transmission technologies, and in particular, to a data transmission system, method and chip for an SOC bus.
Background
In a mainstream PC (Personal Computer personal computer) system, PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is used as a main motherboard-level interconnection bus to connect a host system processor with various integrated peripherals, thereby expanding storage space, computing power, and network communication bandwidth. PCIE is continuously perfected and is capable of supporting the speed of 64Gbps and the bus width of x16, so that the PCIE not only becomes the most favorable interconnection bus competitor in the emerging cloud computing field, but also is excellent in the low-power consumption field. In addition, in the IoT (Internetof Things ) and Mobile (Mobile) fields, PCIE buses are also often used as expansion buses for a main SOC (System On Chip).
In the related art, in the PCIE TLP (Transaction Layer Packet, transmission transaction packet), only Byte Enable fields of a head address and a tail address of a DWord (double-Byte data) are defined, and Byte Enable fields of middle-segment data are not defined. However, in the SOC internal bus, in order to improve the efficiency of reading and writing, a read-write operation is avoided, and each byte data usually has an enable attribute.
Therefore, the PCIE controller serves as a control conversion interface between the SOC internal bus and the PCIE bus, and proposes a use constraint for software and system layers: in the write operation sent out by the internal bus, the Byte Enable attribute must completely conform to the PCIE TLP definition. Otherwise, PCIE transmission data errors occur, and the phenomenon of link interruption after multiple retries is avoided.
Disclosure of Invention
In order to solve at least one problem in the prior art, an object of the present application is to provide a data transmission system, method and chip for an SOC bus, which can realize automatic splitting of write transactions for data transmission of the SOC bus, and remove byte enabling restrictions that must meet PCIE TLP definitions, so as to effectively avoid PCIE transmission data errors and avoid link interruption phenomenon occurring after multiple retries.
To achieve the above object, a data transmission system for SOC bus provided in the present application includes:
the monitoring module is communicated with the SOC bus and is configured to monitor the write transaction on the SOC bus and output the write transaction needing to be split;
the monitoring queue module is connected with the monitoring module and is configured to receive the write transaction needing to be split, store the write transaction as a monitoring queue and output the monitoring queue;
and the SOC bus adaptation module is communicated with the SOC bus, is connected with the monitoring queue module, comprises an address channel queue, and is configured to receive the write transaction on the SOC bus and the monitoring queue sent by the monitoring queue module, and perform mode switching based on the information in the monitoring queue and the current address channel queue and output a write transaction data packet.
Further, the SOC bus adaptation module is further configured to send a response message to the SOC bus for notifying the SOC bus that the transmission is completed after the transmission is completed.
Further, the system further comprises:
the SOC bus arbitration module is communicated with the plurality of SOC buses, is connected with the SOC bus adaptation module, and is configured to receive the write transactions on the plurality of SOC buses, order the plurality of write transactions according to priority and then send the write transactions to the SOC bus adaptation module;
the SOC bus adapter module is further configured to receive the write transaction sent by the SOC bus arbitration module.
Further, the write transaction includes: address of write transaction, control information, write data, and write enable information.
Further, the monitoring module is further configured to determine, based on the write enable information of the write transaction, whether the write transaction needs to be split, if the write enable information of the write transaction is a preset value, determine that the write transaction needs to be split, and if the write enable information of the write transaction is not the preset value, determine that the write transaction does not need to be split.
Still further, the SOC bus adaptation module further includes a data channel queue configured to receive the monitor queue and the write transaction, and based on a preset finite state machine, switch between a bypass mode and a non-bypass mode according to whether the monitor queue is empty and whether the write transaction in the address channel queue that is currently cached needs to be split, in the bypass mode, output the write transaction, in the non-bypass mode, cache the address and the control information in the write transaction to the address channel queue, and cache the write data and the write enable information of the write transaction to the data channel queue.
Still further, the step of switching between the bypass mode and the non-bypass mode based on the monitor queue and the address channel queue currently cached includes:
in a bypass mode, if the write transaction in the address channel queue does not need to be split and the monitoring queue is empty, maintaining a bypass mode based on a preset finite state machine;
in a bypass mode, if the write transaction in the address channel queue needs to be split currently or the monitoring queue is not empty, switching to a non-bypass mode based on a preset finite state machine;
in a non-bypass mode, if the write transaction in the address channel queue does not need to be split and the monitoring queue is empty, switching to a bypass mode based on a preset finite state machine;
in the non-bypass mode, if the write transaction in the address channel queue needs to be split currently or the monitoring queue is not empty, the non-bypass mode is maintained based on a preset finite state machine.
To achieve the above object, the present application further provides a method for data transmission of an SOC bus, to which the data transmission system for an SOC bus as described above is applied, the method including:
monitoring a write transaction on an SOC bus, and outputting the write transaction needing to be split;
receiving the write transaction needing to be split, storing the write transaction as a monitoring queue and outputting the monitoring queue;
and receiving the write transaction and the monitoring queue on the SOC bus, performing mode switching based on the monitoring queue and the current address channel queue, and outputting a write transaction data packet.
To achieve the above object, the present application further provides a chip on which the system for data transmission of SOC bus as described above is integrated.
In order to achieve the above purpose, the circuit board further comprises the chip.
In order to achieve the above purpose, the vehicle machine further comprises the chip.
To achieve the above object, the present application further provides an electronic device including a memory and a processor, the memory having stored therein computer instructions configured to execute the instructions to perform the steps of the method for data transmission of an SOC bus as described above.
To achieve the above object, the present application also provides a computer-readable storage medium having stored thereon computer instructions which, when executed, perform a method for data transmission of an SOC bus as described above.
According to the data transmission system, the method and the chip for the SOC bus, the write transaction on the SOC bus is monitored through the monitoring module, the write transaction needing to be split is output, the write transaction needing to be split is received through the monitoring queue module and stored as the monitoring queue and output, the write transaction on the SOC bus and the monitoring queue sent by the monitoring queue module are received through the SOC bus adaptation module, and mode switching is performed based on the information in the monitoring queue and the current address channel queue, and a write transaction data packet is output. Therefore, for data transmission of the SOC bus, automatic splitting of write transactions can be realized, byte enabling limitation which must meet the definition of PCIE TLP is removed, and therefore PCIE transmission data errors can be effectively avoided, and the phenomenon of link interruption after multiple retries is avoided.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and explain the application and do not limit it. In the drawings:
FIG. 1 is a schematic diagram of a data transfer system for an SOC bus according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a data transmission system for an SOC bus according to another embodiment of the present application;
FIG. 3 is a schematic diagram of an SOC bus adapter module application according to an embodiment of the present application;
FIG. 4 is a schematic diagram of mode switching according to an embodiment of the present application;
FIG. 5 is a flow chart of a method for data transfer of an SOC bus according to an embodiment of the present application;
FIG. 6 is a block diagram of a chip structure according to an embodiment of the present application;
FIG. 7 is a block diagram of a circuit board structure according to an embodiment of the present application;
FIG. 8 is a block diagram of a vehicle structure according to an embodiment of the present application;
fig. 9 is a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and examples of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that references to "one" or "a plurality" in this application are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a data transmission system for an SOC bus according to an embodiment of the present application, and referring to fig. 1, a data transmission system 10 for an SOC bus includes: the system comprises a monitoring module 11, a monitoring queue module 12 and an SOC bus adaptation module 13.
The monitoring module 11 is in communication with the SOC bus and is configured to monitor write transactions on the SOC bus and output write transactions that need to be split.
Specifically, referring to fig. 2, the Monitor module (Monitor) 11 may be a plurality of hosts, such as a CPU (Central Processing Unit ), a GPU (Graphic Processing Unit, a graphics processor), a DMA (DirectMemory Access ), and the like, respectively, configured in a one-to-one correspondence with a plurality of hosts of the SOC bus to Monitor write transactions on the SOC bus.
In this embodiment of the present application, the write transaction may be a write transaction of PCIE, and specifically includes an address, control information, write data, and write enable information of the write transaction.
In a specific example, when the monitoring module 11 monitors the write transaction on the SOC bus, the length of the write data may be determined first. If the length is less than or equal to the length threshold (e.g., 8 bytes), determining that the write transaction does not need to be split; if its length is greater than a length threshold (e.g., 8 bytes), then a determination is made that the write transaction needs to be split, or that the write transaction needs further policy determination whether it needs to be split.
In this embodiment, the monitoring module 11 is further configured to determine, based on the write enable information of the write transaction, whether the write transaction needs to be split, if the write enable information of the write transaction is a preset value, determine that the write transaction needs to be split, and if the write enable information of the write transaction is not the preset value, determine that the write transaction does not need to be split.
In particular, the write enable information may be 1 or 0, the value of which is relatively random on the software application. When the write enable information of the write transaction is 0 (the above-mentioned preset value), the monitoring module 13 determines that the write transaction needs to be split.
It should be noted that, since the splitting of the write transaction needs the corresponding overhead, in order to avoid unnecessary splitting, the monitoring module 11 may first determine whether the received write transaction needs to be split, and then split the write transaction that needs to be split through the SOC bus adapter module 13, and pass through the write transaction that does not need to be split, so as to effectively control the overhead, reduce the bandwidth utilization loss, and improve the duty ratio of the effective data during automatic splitting.
The monitoring queue module 12 is connected with the monitoring module and is configured to receive the write transaction needing to be split, store the write transaction as a monitoring queue and output the monitoring queue. That is, the Monitor Queue module 12 receives the write transaction to be split sent by the Monitor module 11, writes it into a Monitor Queue (Monitor Queue), and outputs it to the SOC bus adaptation module 13.
Referring to fig. 2-3, SOC bus adapter module 13, in communication with the SOC bus, is coupled to monitor queue module 12 and includes address channel queue (Address Channel Queue) 131. The SOC bus adaptation module 13 is configured to receive the write transaction on the SOC bus and the monitor queue sent by the monitor queue module 12, perform mode switching based on the information in the monitor queue and the current address channel queue 131, and output a write transaction packet.
Specifically, the address channel queue 131 includes address and control information of the write transaction, as shown in fig. 3, the SOC bus adaptation module 13 may determine, through the arbitration unit (arbiter) 132, a bypass mode (bypass_granted) or a non-bypass mode (non_bypass_granted), and control, through the finite state machine 134, switching between the bypass mode (data transmission is shown as a dotted line not passing through the corresponding channel queue in fig. 3) and the non-bypass mode (data transmission is shown as a solid line passing through the corresponding channel queue in fig. 3), and output a write transaction packet to the PCIE controller in the corresponding mode, so that the PCIE controller transmits data through the PCIE bus.
Note that, in the PCIE TLP, the Byte Enable fields of the first address and the last address of the DWord are defined, and the Byte Enable field of the intermediate segment data is not defined. Therefore, in a specific example, if the monitoring module 11 monitors that the write enable information of the write transaction data is 0, it is determined that the transaction data packet needs to be split, then the monitoring queue module 12 receives the write transaction that needs to be split and stores the write transaction as a monitoring queue and outputs the monitoring queue to the SOC bus adapting module 13, and then the SOC bus adapting module 13 splits the write transaction data packet according to the address of the data with the write enable information of 0, specifically, the byte with the write enable information of 0 can be configured as a DWord First address (First DWord) or a DWord Last address (Last DWord) of the PCIE TLP, so that the enable information of the middle segment data in the PCIE TLP is 1, that is, all data in the shortened PCIE TLP also has the enable attribute, and byte enable restrictions that must meet the PCIE TLP definition are eliminated, thereby effectively avoiding the PCIE transmission data errors and avoiding the link interruption phenomenon that occurs after multiple retries.
In this embodiment, the SOC bus adaptation module 13 further includes a data channel queue (Data Channel Queue) 133. The SOC bus adaptation module 13 is configured to receive the monitor queue and the write transaction and switch between the bypass mode and the non-bypass mode (mode_sel) via the MUX (data selector) based on a preset finite state machine (FSM, finite State Machine) 134, depending on whether the monitor queue is empty and whether the write transaction in the currently cached address channel queue 131 needs to be split.
In particular, the data channel queue 133 may include write data and write enable information for a write transaction. For the non-bypass mode, the processing mode is configured to be the non-bypass mode when the monitor queue is not empty and the write transaction in the currently cached address channel queue 131 needs to be split. In the non-bypass mode, SOC bus adaptation module 13 buffers address and control information in the write transaction to address channel queue 131 and buffers write data and write enable information of the write transaction to data channel queue 133. For the bypass mode, the processing mode is configured to bypass mode when the monitor queue is empty or the write transaction in the currently cached address channel queue 131 does not need to be split. In bypass mode, the SOC bus adaptation module 13 transparently outputs write transactions.
Further, referring to fig. 4, the step of switching between the bypass mode and the non-bypass mode based on the monitor queue and the currently cached address channel queue includes: in the bypass mode, if the write transaction in the current address channel queue does not need to be split and the monitoring queue is empty, maintaining the bypass mode based on a preset finite state machine; in the bypass mode, if the write transaction in the current address channel queue needs to be split or the monitoring queue is not empty, switching to the non-bypass mode based on a preset finite state machine; in the non-bypass mode, if the write transaction in the current address channel queue does not need to be split and the monitoring queue is empty, switching to the bypass mode based on a preset finite state machine; in the non-bypass mode, if the write transaction in the current address channel queue needs to be split or the monitoring queue is not empty, the non-bypass mode is maintained based on a preset finite state machine.
In this embodiment, the SOC bus adaptation module 13 is further configured to send a response message to the SOC bus after the transmission is completed, for notifying the SOC bus that the transmission is completed. Specifically, as shown in fig. 3, for transmission in the non-bypass mode, a response may be made through the response channel queue (Response Channel Queue) 135.
In the embodiment of the present application, as shown in fig. 3, the data transmission system 10 for SOC bus further includes an SOC bus arbitration module 14. The SOC bus arbitration module 14 is in communication with the plurality of SOC buses, is connected to the SOC bus adaptation module 13, and is configured to receive the write transactions on the plurality of SOC buses, order the plurality of write transactions according to priority, and send the write transactions to the SOC bus adaptation module 13. The SOC bus adaptation module 13 is further configured to receive write transactions sent by the SOC bus arbitration module 14.
In summary, according to the data transmission system for the SOC bus in the embodiment of the present application, a monitoring module monitors a write transaction on the SOC bus, outputs a write transaction to be split, receives the write transaction to be split through a monitoring queue module and stores the write transaction as a monitoring queue and outputs the write transaction, and receives the write transaction on the SOC bus and the monitoring queue sent by the monitoring queue module through an SOC bus adapter module, and performs mode switching based on information in the monitoring queue and a current address channel queue and outputs a write transaction data packet. Therefore, for data transmission of the SOC bus, automatic splitting of write transactions can be realized, byte enabling limitation which must meet the definition of PCIE TLP is removed, and therefore PCIE transmission data errors can be effectively avoided, and the phenomenon of link interruption after multiple retries is avoided. In addition, since the automatic splitting of the writing transaction is completely transparent to software, the opposite terminal equipment does not need to be changed, and the implementation is convenient.
Fig. 5 is a flowchart of a method for data transmission of an SOC bus according to an embodiment of the present application. Referring to fig. 5, a method for data transmission of an SOC bus, to which the data transmission system for an SOC bus in the above-described embodiment is applied, includes the steps of:
in step 201, a write transaction on the SOC bus is monitored, outputting the write transaction that needs to be split.
In step 202, write transactions requiring splitting are received and stored as a monitor queue and output.
In step 203, a write transaction and a monitor queue on the SOC bus are received, mode switching is performed based on the monitor queue and the current address channel queue, and a write transaction packet is output.
In the embodiment of the application, the method further comprises the following steps: to send a response message to the SOC bus when the transfer is completed, for informing the SOC bus that the transfer is completed.
In the embodiment of the application, the method further comprises the following steps: the SOC bus arbitration module receives the write transactions on the plurality of SOC buses, sorts the plurality of write transactions according to priority and sends the write transactions to the SOC bus adaptation module.
Further, the method further comprises: based on the write enabling information of the write transaction, judging whether the write transaction needs to be split, if the write enabling information of the write transaction is a preset value, determining that the write transaction needs to be split, and if the write enabling information of the write transaction is not the preset value, determining that the write transaction does not need to be split.
Further, the method further comprises: and receiving a monitoring queue and a writing transaction, switching between a bypass mode and a non-bypass mode according to whether the monitoring queue is empty or not and whether the writing transaction in the address channel queue which is cached currently needs to be split or not based on a preset finite state machine, outputting the writing transaction in the bypass mode, caching the address and control information in the writing transaction in the address channel queue in the non-bypass mode, and caching the writing data and writing enabling information of the writing transaction in the data channel queue.
Further, the step of switching between the bypass mode and the non-bypass mode based on the monitor queue and the currently cached address channel queue includes: in the bypass mode, if the write transaction in the current address channel queue does not need to be split and the monitoring queue is empty, maintaining the bypass mode based on a preset finite state machine; in the bypass mode, if the write transaction in the current address channel queue needs to be split or the monitoring queue is not empty, switching to the non-bypass mode based on a preset finite state machine; in the non-bypass mode, if the write transaction in the current address channel queue does not need to be split and the monitoring queue is empty, switching to the bypass mode based on a preset finite state machine; in the non-bypass mode, if the write transaction in the current address channel queue needs to be split or the monitoring queue is not empty, the non-bypass mode is maintained based on a preset finite state machine.
It should be noted that, the explanation of the data transmission system for SOC bus in the above embodiment is also applicable to the method for data transmission of SOC bus in the above embodiment, and will not be repeated here.
Fig. 6 is a block diagram of a chip structure according to an embodiment of the present application. Referring to fig. 6, a chip 100 has integrated thereon the system 10 for data transfer of an SOC bus in the above-described embodiment.
Fig. 7 is a block diagram of a circuit board structure according to an embodiment of the present application. Referring to fig. 7, a circuit board 200 includes the chip 100 in the above-described embodiment.
Fig. 8 is a block diagram of a vehicle structure according to an embodiment of the present application. Referring to fig. 8, a vehicle 300 includes the chip 100 in the above embodiment.
Fig. 9 is a block diagram of an electronic device according to an embodiment of the present application. Referring to fig. 9, an electronic device 400 includes a memory 401 and a processor 402, the memory 401 having stored therein computer instructions, the processor 402 being configured to execute the instructions to perform the steps of the method for data transfer of an SOC bus in the above-described embodiments.
In one embodiment of the present application, there is also provided a computer readable storage medium, which may be included in the system described in the above embodiment; or may exist alone without being assembled into the system. The computer readable storage medium carries one or more computer instructions which, when executed, implement the steps of the data transfer system for an SOC bus of the above-described embodiments.
Embodiments of the present application, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
It should be understood that, although the steps in the flowcharts of the specification are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
It is noted that the specific values mentioned above are only for the purpose of illustrating the implementation of the present application in detail as examples and should not be construed as limiting the present application. In other examples or embodiments or examples, other values may be selected according to the present application, without specific limitation.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present application, and is not intended to limit the present application, but although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the technical solutions described in the foregoing embodiments, or that equivalents may be substituted for part of the technical features thereof. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (13)

1. A data transfer system for an SOC bus, comprising:
the monitoring module is communicated with the SOC bus and is configured to monitor the write transaction on the SOC bus and output the write transaction needing to be split;
the monitoring queue module is connected with the monitoring module and is configured to receive the write transaction needing to be split, store the write transaction as a monitoring queue and output the monitoring queue;
and the SOC bus adaptation module is communicated with the SOC bus, is connected with the monitoring queue module, comprises an address channel queue, and is configured to receive the write transaction on the SOC bus and the monitoring queue sent by the monitoring queue module, and perform mode switching based on the information in the monitoring queue and the current address channel queue and output a write transaction data packet.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the SOC bus adaptation module is further configured to send a response message to the SOC bus after the transmission is completed, and the response message is used for informing the SOC bus that the transmission is completed.
3. The system of claim 1, further comprising:
the SOC bus arbitration module is communicated with the plurality of SOC buses, is connected with the SOC bus adaptation module, and is configured to receive the write transactions on the plurality of SOC buses, order the plurality of write transactions according to priority and then send the write transactions to the SOC bus adaptation module;
the SOC bus adapter module is further configured to receive the write transaction sent by the SOC bus arbitration module.
4. The system of claim 1, wherein the write transaction comprises: address of write transaction, control information, write data, and write enable information.
5. The system of claim 4, wherein the monitoring module is further configured to determine whether the write transaction needs to be split based on write enable information of the write transaction, determine that the write transaction needs to be split if the write enable information of the write transaction is a preset value, and determine that the write transaction does not need to be split if the write enable information of the write transaction is not a preset value.
6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
the SOC bus adaptation module further comprises a data channel queue, is configured to receive the monitoring queue and the write transaction, and based on a preset finite state machine, switches between a bypass mode and a non-bypass mode according to whether the monitoring queue is empty and whether the write transaction in the address channel queue which is cached currently needs to be split, outputs the write transaction in the bypass mode, caches the address and the control information in the write transaction in the address channel queue in the non-bypass mode, and caches the write data and the write enabling information of the write transaction in the data channel queue.
7. The system of claim 6, wherein the step of switching between bypass mode and non-bypass mode based on the monitor queue and the address channel queue currently cached comprises:
in a bypass mode, if the write transaction in the address channel queue does not need to be split and the monitoring queue is empty, maintaining a bypass mode based on a preset finite state machine;
in a bypass mode, if the write transaction in the address channel queue needs to be split currently or the monitoring queue is not empty, switching to a non-bypass mode based on a preset finite state machine;
in a non-bypass mode, if the write transaction in the address channel queue does not need to be split and the monitoring queue is empty, switching to a bypass mode based on a preset finite state machine;
in the non-bypass mode, if the write transaction in the address channel queue needs to be split currently or the monitoring queue is not empty, the non-bypass mode is maintained based on a preset finite state machine.
8. A method for data transmission of an SOC bus, applied to the data transmission system for an SOC bus of any of claims 1 to 7, the method comprising:
monitoring a write transaction on an SOC bus, and outputting the write transaction needing to be split;
receiving the write transaction needing to be split, storing the write transaction as a monitoring queue and outputting the monitoring queue;
and receiving the write transaction and the monitoring queue on the SOC bus, performing mode switching based on the monitoring queue and the current address channel queue, and outputting a write transaction data packet.
9. A chip, characterized in that the system for data transmission of SOC bus according to any of claims 1 to 7 is integrated on the chip.
10. A circuit board comprising the chip of claim 9.
11. A vehicle comprising the chip of claim 9.
12. An electronic device comprising a memory and a processor, wherein the memory has stored therein computer instructions configured to execute the instructions to perform the steps of the method for data transfer of an SOC bus of claim 8.
13. A computer readable storage medium having stored thereon computer instructions which when executed perform the method for data transfer of an SOC bus as claimed in claim 8.
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