CN116155430A

CN116155430A - Optical fiber bidirectional signal transmission delay error elimination method and time-frequency system

Info

Publication number: CN116155430A
Application number: CN202310038558.8A
Authority: CN
Inventors: 邓意峰; 曾迎春; 朱敏; 简和兵; 温学斌; 严波; 杨彩芳
Original assignee: Chengdu Jinnuoxin High Tech Co ltd
Current assignee: Chengdu Jinnuoxin High Tech Co ltd
Priority date: 2023-01-11
Filing date: 2023-01-11
Publication date: 2023-05-23

Abstract

The invention discloses a method for eliminating optical fiber bidirectional signal transmission delay errors and a time-frequency system, wherein the method comprises three stages, namely: initializing a delay measurement stage; a pulse transmission stage; and a dynamic time delay measuring stage. The method combines the optical fiber bidirectional signal transmission delay error elimination technology with the time service technology, realizes time service synchronization among all stations, synchronously transmits communication signals (instruction pulses) generated by the DBF host to all DBF extensions, and keeps synchronization of the communication signals of all DBF extensions and the DBF host, thereby realizing delay error elimination of the communication signals, ensuring signal synchronism among communication equipment and ensuring reliability of a communication system; in addition, the time service signals and the communication signals are transmitted by using the same optical fiber link, so that the saving of link resources is also realized.

Description

Optical fiber bidirectional signal transmission delay error elimination method and time-frequency system

Technical Field

The invention belongs to the field of time unification and the technical field of signal communication, and particularly relates to a method for eliminating time delay errors of optical fiber bidirectional signal transmission and a time-frequency system.

Background

The time service synchronization is carried out between the communication devices through time unification field devices (time-frequency devices) carried by self sites, time service transmission is carried out between the time unification field devices through optical fibers, the traditional optical fiber time service mode is PTP optical fiber time service, before PTP optical fiber time service is carried out, optical fiber link connection is required to be built between the time unification field devices, time service between the communication devices is completed based on PTP message transmission through the optical fiber link connection, time service transmission is carried out based on the optical fiber links which are independently built, the signal communication links between the time unification field devices and the communication devices are in a separated state, service communication signals between the communication devices cannot be synchronously transmitted while PTP time service transmission is carried out, and service communication signal time delay between the communication devices cannot be corrected. The time service signals are transmitted through the optical fiber links which are independently built among the devices in the unified time field, and the service communication signals among the communication devices are transmitted through the communication links, so that great line resource waste is caused, and particularly for the long-distance communication devices, the resource waste is extremely prominent; meanwhile, the time delay of the service communication signals between the communication devices cannot be eliminated, which results in poor synchronization performance between the communication devices. If the communication device is a radar communication terminal in the radar detection system, the signals are not synchronous, so that the performance of the radar detection system is drastically reduced and even cannot work normally.

In summary, how to reduce the cost of link establishment between communication devices, complete signal communication while completing timing synchronization, and complete high-precision delay error elimination between communication signals is the key content of device research in the current unified time domain.

Disclosure of Invention

The invention aims to overcome one or more defects in the prior art and provides a method for eliminating delay errors of optical fiber bidirectional signal transmission and a time-frequency system.

The aim of the invention is realized by the following technical scheme:

first aspect

The first aspect of the present invention provides a method for eliminating delay errors in optical fiber bidirectional signal transmission, the method is applied to a communication system, the communication system comprises a master station and a plurality of slave stations, the master station comprises a time-frequency master and a DBF master, each slave station comprises a time-frequency slave and a DBF slave, the DBF master is connected with the time-frequency master, the time-frequency slave is connected with the DBF slave, the time-frequency master is connected with each time-frequency slave through optical fiber communication, the method comprises the following steps:

powering up and initializing a communication system;

the time-frequency host generates an initialization pulse based on time service information acquired by the time-frequency host, generates a first time service code which does not contain service information based on the initialization pulse, and sends the first time service code to each slave station, wherein the initialization pulse is synchronous with the first time service code;

The time-frequency host receives the first time service codes returned by the slave stations, and determines each time delay value used for representing the link transmission delay between the master station and each slave station according to the first time service codes sent by the time-frequency host and the first time service codes returned by the slave stations, wherein each time delay value corresponds to each slave station one by one;

the time-frequency host determines the time delay adjustment value corresponding to each slave station according to the time delay value corresponding to each slave station, determines the time delay adjustment value of the master station according to all the time delay values, delays the initialization pulse according to each time delay adjustment value, and obtains the target pulse corresponding to the time delay adjustment value after delay, wherein the delay value between the target pulse and the initialization pulse is the time delay adjustment value;

generating second time service codes containing service information based on the target pulses by the time-frequency host in a one-to-one correspondence manner, framing the instruction pulses generated by the DBF host with the second time service codes respectively, generating communication serial codes corresponding to the second time service codes after framing the SerDes, transmitting the communication serial codes to the slave stations in a one-to-one correspondence manner, and transmitting the communication serial codes corresponding to the master station back to the master station, wherein the slave stations and the master station receive the communication serial codes corresponding to the slave stations at the same time;

The time-frequency host and each time-frequency extension respectively carry out SerDes frame decoding on the communication serial code received by the time-frequency host and each time-frequency extension, after the SerDes frame decoding, instruction pulses and second time service codes are obtained, the time-frequency host transmits the instruction pulses obtained by the frame decoding to the DBF host, master station time correction is carried out according to the second time service codes, the time-frequency extension transmits the instruction pulses obtained by the frame decoding to the corresponding connected DBF extension, and slave station time correction is carried out according to the second time service codes.

Preferably, the method further comprises:

each time-frequency extension transmits the second time service code obtained after the serDes deframes to the time-frequency host computer;

the time-frequency host determines the dynamic update value of each time delay value according to the first time service code sent by the time-frequency host and the second time service code returned by each slave station, and updates each time delay value stored in the time-frequency host into the dynamic update value of each time delay value in a one-to-one correspondence manner.

Preferably, the code patterns of the first time service code and the second time service code are non-standard IRIG-B codes, wherein the non-standard IRIG-B codes are IRIG-B codes with different code rates and symbol pulse widths from the standard IRIG-B codes; the command pulses generated by the DBF host include BW pulses, CPI pulses, FR pulses, and sub FR pulses.

Preferably, the time-frequency host generates an initialization pulse based on time service information acquired by the time-frequency host, and specifically comprises the following sub-steps:

The time-frequency host receives time service information generated by a satellite receiver connected with the master station;

and the time-frequency host machine disciplines the local crystal oscillator according to the time service information, and generates an initialization pulse after the crystal oscillator is disciplined.

Preferably, the time-frequency host determines the time-delay adjustment value corresponding to each secondary station according to the time-delay value corresponding to each secondary station, and determines the time-delay adjustment value of the master station according to all the time-delay values, which specifically comprises the following sub-steps:

the time-frequency host judges the maximum value in the corresponding time delay values of each slave station;

the time-frequency host determines the time delay adjustment value of the slave station corresponding to the maximum time delay value as a zero value, and determines the time delay adjustment value corresponding to each other slave station as a difference value between the maximum time delay value and the time delay value corresponding to the slave station;

and the time-frequency host determines the time-delay adjustment value of the master station as the sum of the maximum time-delay value and a first preset value according to all the time-delay values, wherein the first preset value is the hardware time delay of the SerDes frame decoding of the time-frequency extension of each slave station, and the hardware time delay corresponding to each slave station is the same.

The first aspect of the invention has the following beneficial effects:

（1）、

through the first stage: after the system is powered on and initialized, a time-frequency host transmits a first time service code (the service information is in an empty code pattern and does not contain information such as years, days, time, minutes, seconds and the like required by time service transmission) which does not contain service information to each time-frequency extension, each time-frequency extension transmits the first time service code back to the time-frequency host, and the time-frequency host completes the measurement of the time delay of a transmission link between the time-frequency host and each time-frequency extension based on the first round-trip time service code;

Through the second stage: the time-frequency host determines each time delay adjustment value according to each transmission link time delay value, then carries out corresponding delay on a second time service code for transmitting service information required by time service to each slave station, carries out SerDes framing on the delayed second time service code and each communication signal (instruction pulse) generated by the DBF host, and sends communication serial codes obtained after SerDes framing to each slave station and a transmission master station in a one-to-one correspondence manner so that the communication serial codes received by the time-frequency host and each time-frequency extension are synchronous; the time-frequency host and the time-frequency extension machine perform SerDes frame-decoding operation on the communication serial code received by the time-frequency host and the time-frequency extension machine to obtain a second time service code and each communication signal generated by the DBF host, and each communication signal generated by the DBF host is transmitted to each DBF extension machine and each DBF host;

the method of the first aspect of the invention combines the optical fiber bidirectional signal transmission delay error elimination technology with the time service technology, realizes time service synchronization among all stations, synchronously transmits the communication signals (instruction pulses) generated by the DBF host to all DBF extensions, and keeps synchronous communication signals of all DBF extensions and the DBF host, thereby realizing delay error elimination of the communication signals, ensuring signal synchronism among communication equipment and ensuring reliability of a communication system; in addition, the time service signals and the communication signals are transmitted by using the same optical fiber link, so that the saving of link resources is also realized.

(2) And each time-frequency extension transmits the second time service code obtained after the serDes deframes back to the time-frequency host, and the time-frequency host dynamically updates each locked time delay value in real time, so that the accuracy of eliminating the signal transmission time delay errors is further improved.

Second aspect

The second aspect of the invention provides a time-frequency system, which comprises a time-frequency host and a plurality of time-frequency extensions, wherein the time-frequency host and each time-frequency extension have the same internal structure, the time-frequency host is arranged in a master station, each time-frequency extension is respectively and correspondingly arranged in each slave station, the time-frequency host is used for being connected with a DBF host in the master station and a reference clock source connected with the master station, the time-frequency extension is used for being connected with a DBF extension in a slave station where the time-frequency extension is positioned, and the time-frequency host is connected with each time-frequency extension through optical fiber communication; the time-frequency host comprises an FPGA module, a TDC time difference measuring module and a master control module, wherein the master control module is connected with the FPGA module, the master control module is also used for being connected with the reference clock source, the FPGA module is used for being connected with the DBF host, the FPGA module is also used for being connected with each time-frequency extension set through optical fibers, and the FPGA module is also connected with the TDC time difference measuring module;

The main control module is used for acquiring time service information from the reference clock source, generating an initialization pulse based on the acquired time service information and sending the initialization pulse to the FPGA module;

the FPGA module is used for generating a first time service code which does not contain service information according to the initialization pulse, and sending the first time service code to each time-frequency extension set through an optical fiber, wherein the initialization pulse and the first time service code are kept synchronous;

the FPGA module is also used for receiving the first time service codes returned by each time-frequency extension set, and sending the first time service codes sent by the FPGA module and the first time service codes returned by each time-frequency extension set to the TDC time difference measuring module;

the TDC time difference measurement module is used for measuring the time difference between a first time service code sent by the FPGA module and a first time service code returned by each time-frequency extension, and sending each time difference to the main control module through the FPGA module;

the master control module is used for determining each time delay value according to each time difference, each time delay value is used for representing the link transmission time delay between the master station and each slave station in a one-to-one correspondence manner, each time delay value corresponds to each slave station one by one, then determining a time delay adjustment value corresponding to each slave station according to the time delay value corresponding to each slave station, determining the time delay adjustment value of the master station according to all the time delay values, and sending each time delay adjustment value to the FPGA module;

The FPGA module is used for respectively delaying the initialization pulse according to each time delay adjustment value, and obtaining a target pulse corresponding to the time delay adjustment value after delaying, wherein the delay value between the target pulse and the initialization pulse is the time delay adjustment value;

the FPGA module is further used for generating second time service codes containing service information based on one-to-one correspondence of target pulses, then carrying out SerDes framing on command pulses generated by the DBF host and the second time service codes respectively, generating communication serial codes corresponding to the second time service codes after the SerDes framing is completed, sending the communication serial codes to the slave stations in one-to-one correspondence, and returning the communication serial codes corresponding to the master station, wherein the slave stations and the master station receive the communication serial codes corresponding to the slave stations at the same moment;

the FPGA module is also used for carrying out SerDes frame decoding on the communication serial code received by the FPGA module, obtaining an instruction pulse and a second time service code after SerDes frame decoding, and the time-frequency host computer is used for transmitting the instruction pulse obtained by frame decoding to the DBF host computer and carrying out master station time correction according to the second time service code.

Preferably, the time-frequency host further comprises a DPLL phase modulation module and an optical module; the DPLL phase modulation module is respectively connected with the FPGA module and the main control module, the optical module is connected with the FPGA module, the optical module is also used for being connected with an optical terminal in the main station, and the optical terminal in the main station is connected with each time-frequency extension through optical fibers;

The optical module is used for carrying out electro-optical conversion on the first time service code and each communication serial code generated by the FPGA module, and sending the first time service code and each communication serial code after the electro-optical conversion to an optical terminal in the master station;

the master control module is also used for generating a first working clock based on the acquired time service information and sending the first working clock to the FPGA module and the DPLL phase modulation module;

the main control module is further configured to correspondingly decompose each delay adjustment value into a first value and a second value, send the first value to the FPGA module, and send the second value to the DPLL phase modulation module, where the first value is a product of a quotient value obtained by dividing the delay adjustment value by a first working clock period and a first working clock period, and the second value is a remainder value obtained by dividing the delay adjustment value by the first working clock period;

the DPLL phase modulation module is used for respectively shifting the phase of the first working clock according to each second numerical value, generating each local delay clock corresponding to each second numerical value one by one after the phase shifting, and sending each local delay clock to the FPGA module, wherein the delay of each local delay clock compared with the first working clock is the second numerical value corresponding to the local delay clock; the FPGA module is further used for delaying the initialization pulse in a register beat mode according to each first numerical value, and generating target pulses corresponding to the first numerical values one by one after delaying, wherein delay values between the target pulses and the initialization pulses are delay adjustment values corresponding to the first numerical values corresponding to the target pulses, the number of the register beats is a quotient value obtained by dividing the first numerical values by a first working clock period, the clocks of the register beats are corresponding local delay clocks, and the corresponding local delay clocks are corresponding to the second numerical values corresponding to the delay adjustment values corresponding to the first numerical values.

Preferably, the FPGA module in the time-frequency extension is used for connecting with the DBF extension in the slave station where the time-frequency extension is located; the FPGA module in each time-frequency extension carries out SerDes frame decoding on the communication serial code received by the time-frequency extension, command pulses and second time service codes are obtained after SerDes frame decoding, the command pulses obtained by frame decoding are transmitted to the DBF extension correspondingly connected, and secondary station time correction is carried out according to the second time service codes;

the FPGA module in each time-frequency extension also transmits the second time service code obtained after the SerDes deframes to the FPGA module in the time-frequency host;

the FPGA module in the time-frequency host is also used for transmitting the second time service codes returned by each slave station to the TDC time difference measuring module;

the TDC time difference measuring module in the time-frequency host is also used for measuring the new time difference between the first time service code sent by the FPGA module in the time-frequency host and the second time service code returned by each time-frequency extension, and sending each new time difference to the main control module in the time-frequency host through the FPGA module;

the main control module in the time-frequency host is also used for determining the dynamic update value of each time delay value according to each new time difference, and updating each stored time delay value into the dynamic update value of each time delay value in a one-to-one correspondence manner.

Preferably, the reference clock source is a satellite receiver connected with the main station; the frequency of the first working clock is 200MHz; the DPLL phase modulation module adopts a DPLL chip with the model of AD 9545.

Preferably, the master control module determines the delay adjustment value corresponding to each slave station according to the delay value corresponding to each slave station, and determines the delay adjustment value of the master station according to all the delay values, and the specific process is as follows:

the master control module judges the maximum value in the delay values corresponding to the slave stations;

the master control module determines the delay adjustment value of the slave station corresponding to the maximum delay value as a zero value, and determines the delay adjustment value corresponding to each other slave station as a difference value between the maximum delay value and the delay value corresponding to the slave station;

the master control module determines the own delay adjustment value of the master station as the sum of the maximum delay value and a first preset value according to all delay values, wherein the first preset value is the hardware delay of a SerDes frame decoding for the FPGA module of each slave station, and the hardware delay corresponding to each slave station is the same.

The second aspect of the present invention brings about the same advantageous effects as the first aspect of the present invention and is not described in detail herein. Meanwhile, through the setting of the DPLL phase modulation module, the DPLL phase modulation module realizes first-stage delay adjustment, the FPGA module realizes second-stage delay adjustment, the value of the first-stage delay adjustment is lower than the first working clock period, the value of the second-stage delay adjustment is an integral multiple of the first working clock period, and high-precision delay compensation of each station is realized through selecting the first working clock frequency and the DPLL chip matched with the required phase-shifting precision. For example, the first working clock frequency selected by the embodiment of the invention is 200MHz, the DPLL chip is selected as AD9545, and the phase shifting precision of the AD9545 is ps-level, so that the time delay compensation of ns-level of each station is realized, and the synchronization of ns-level of the command pulse after the time delay compensation is realized when reaching each station.

Drawings

FIG. 1 is a flow chart of a method for eliminating delay errors in optical fiber bi-directional signal transmission;

FIG. 2 is a schematic diagram of a networking of a communication system;

FIG. 3 is a schematic diagram of a networking of a time-frequency system;

FIG. 4 is a block diagram of a time-frequency master/time-frequency slave;

fig. 5 is a schematic diagram of a time delay of a first time service code reaching each time-frequency extension in a first stage of time delay measurement;

FIG. 6 is a schematic diagram showing the arrival of each communication string at the DBF host and each DBF extension after the second phase delay compensation;

FIG. 7 is a diagram illustrating a second timing code and a pattern of command pulses during SerDes framing;

FIG. 8 is a first part of a timing diagram of a method for eliminating delay errors in bi-directional signal transmission of an optical fiber;

fig. 9 is a second part of a timing diagram of a method for eliminating delay errors in optical fiber bi-directional signal transmission.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.

The following is an explanation of the technical terms involved in the following examples:

DBF: a radar upper computer;

BW pulse: radar signal wave level indication pulses;

FR pulse: a radar signal frame length pulse;

sub FR pulse: a sub-frame length pulse;

CPI pulse: pulses of a specific length;

fr_lock pulse: a frame lock indication pulse;

SerDes: abbreviation SERializer/deserialzer;

IRIG-B code: inter-range instrumentationgroup-B, which is a power noun published in 2020, has become a standard code pattern in terms of international time codes.

Example 1

Referring to fig. 1-9, the present embodiment provides a method for eliminating transmission delay errors of optical fiber bidirectional signals, which is applied to a communication system, wherein the communication system includes a master station and a plurality of slave stations, the master station includes a time-frequency master and a DBF master, each slave station includes a time-frequency slave and a DBF slave, the DBF master is connected with the time-frequency master, the time-frequency slave is connected with the DBF slave, the time-frequency master is connected with each time-frequency slave through optical fibers, time service information and communication signals are transmitted between the master station and each slave station through optical fibers, the communication signals are command pulses generated by the DBF master, the command pulses include BW pulses, CPI pulses, FR pulses, sub FR pulses, FR data pulses (FR data pulses), FR CLK pulses (FR clock pulses) and fr_lock pulses, wherein the master station is connected with a satellite receiver and a satellite antenna, and receives the time service information sent by a GNSS satellite through the satellite receiver and the satellite antenna.

As shown in fig. 1, a method for eliminating delay errors of optical fiber bidirectional signal transmission includes the following two steps:

s100, a first stage:

and initializing delay measurement.

S200, a second stage:

and (5) pulse transmission.

Specifically, the first stage comprises the following sub-steps:

s101, powering up and initializing a communication system.

S102, the time-frequency host generates an initialization pulse based on time service information acquired by the time-frequency host, generates a first time service code which does not contain service information based on the initialization pulse, and sends the first time service code to each slave station. Wherein the first time service code generated based on the initialization pulse is synchronized with the initialization pulse.

Specifically, the time-frequency host generates an initialization pulse based on self-acquired time service information, and the process adopts a time service process based on crystal oscillator taming in a common embodiment, and comprises the following sub-steps: the time-frequency host receives time service information generated by a satellite receiver connected with the master station; the time-frequency host machine disciplines the local crystal oscillator according to the time service information, and generates an initialization pulse after the crystal oscillator is disciplined. The type of time service information generated by the satellite receiver is preferably a 1pps+tod signal. The frequency of the initialization pulse is 10MHz. As known, the instruction pulse generated by the DBF host is an indefinite period signal, and the minimum interval time between two instruction pulses is 200us, so in this embodiment, the first time service code adopts an nonstandard IRIG-B code in the nonstandard time code, where the nonstandard IRIG-B code is an IRIG-B code with a different rate and symbol pulse width from those of the standard IRIG-B code. Specifically, the rate of the nonstandard IRIG-B code is 10MHz, the pulse width of each symbol is 0.1us, and a total of 100 symbols, 100 symbols occupy 10us, thereby ensuring that the first phase delay measurement is completed within the minimum separation time between instruction pulses. In addition, other rates of non-standard IRIG-B codes may be used as long as it is ensured that the first stage delay measurement can be completed within a minimum interval time between two command pulses. Because the time delay measurement is needed after the communication system is powered on and initialized, the generated first time service code does not transmit time service information, and only the time delay measurement is performed based on the optical fiber bidirectional transmission technology, therefore, the fact that the communication system does not contain service information means that: the time service transmission information such as day, time, minute, second and the like is not included.

S103, the time-frequency host receives the first time service codes returned by the slave stations, and determines each time delay value used for representing the link transmission delay (optical fiber link delay) between the master station and each slave station according to the first time service codes sent by the time-frequency host and the first time service codes returned by the slave stations, wherein each time delay value corresponds to each slave station one by one.

Specifically, the second stage includes the following sub-steps:

s201, a time-frequency host determines delay adjustment values corresponding to slave stations according to delay values corresponding to the slave stations, determines own delay adjustment values of the master station according to all the delay values, delays initialization pulses according to each delay adjustment value, and obtains target pulses corresponding to the delay adjustment values after delay, wherein delay values between the target pulses and the initialization pulses are the delay adjustment values.

S202, the time-frequency host generates second time service codes containing service information based on one-to-one correspondence of target pulses, the target pulses are synchronous with the second time service codes, the instruction pulses generated by the DBF host are respectively subjected to SerDes framing with the second time service codes, after the SerDes framing is completed, communication serial codes corresponding to the second time service codes are generated, the communication serial codes are sent to the slave stations in one-to-one correspondence, the communication serial codes corresponding to the master station are returned to the master station, the slave stations and the master station receive the corresponding communication serial codes at the same moment, and one schematic diagram that the communication serial codes synchronously reach the DBF host and the DBF extensions is shown in FIG. 6. For example: determining a delay adjustment value corresponding to a first slave station according to a delay value (optical fiber link delay between the first slave station and a master station) corresponding to the first slave station, delaying an initialization pulse to obtain a target pulse, generating a second time service code containing service information based on the target pulse corresponding to the delay adjustment value, carrying out SerDes framing on an instruction pulse generated by a DBF host and the second time service code, and generating a communication serial code corresponding to the second time service code after the SerDes framing is completed, wherein the communication serial code is correspondingly transmitted to the first slave station. In this step, the time service information and the command pulse are transmitted, so that the second time service code includes service information, and the service information includes information such as day, time, minute, second, etc. required for time service transmission, and the code pattern of the nonstandard IRIG-B code of 10MHz and the code pattern of each command pulse when the SerDes frames are as shown in fig. 7.

S203, the time-frequency host and each time-frequency extension respectively carry out SerDes frame decoding on the communication serial codes received by the time-frequency host and each time-frequency extension, after the SerDes frame decoding, instruction pulses and second time service codes are obtained, the time-frequency host transmits the instruction pulses obtained by frame decoding to the DBF host, master station time correction is carried out according to the second time service codes, the time-frequency extension transmits the instruction pulses obtained by frame decoding to the corresponding connected DBF extension, and slave station time correction is carried out according to the second time service codes. The SerDes framing and SerDes de-framing are inverse processes, and are preferably implemented based on a SerDes serial de-serialization unit in the time-frequency host, and the SerDes framing and SerDes de-framing processes are both based on processes in the common embodiment.

Through the first stage and the second stage, the master station transmits command pulses while carrying out time service on each slave station, and enables each command pulse to reach the DBF extension and the DBF host at the same time, so that the asynchronism between the command pulses reaching each DBF extension and the DBF host is eliminated.

In a preferred embodiment, in S201, the time-frequency master determines a delay adjustment value corresponding to each slave according to a delay value corresponding to each slave, and determines a delay adjustment value of the master according to all delay values, which specifically includes the following sub-steps:

The time-frequency host judges the maximum value in the time delay values corresponding to the slave stations.

And the time-frequency host determines the time delay adjustment value of the slave station corresponding to the maximum time delay value as a zero value, and determines the time delay adjustment value corresponding to each other slave station as the difference value between the maximum time delay value and the time delay value corresponding to the slave station.

The time-frequency host determines the time-delay adjustment value of the master station as the sum of the maximum time-delay value and a first preset value according to all the time-delay values, wherein the first preset value is the hardware time delay of the time-frequency extension of each slave station for the SerDes frame decoding, the hardware time delay of the corresponding SerDes frame decoding of each slave station is the same, and the hardware time delay of the time-frequency host of the master station for the SerDes frame decoding is also the same as that of each slave station.

The following describes a procedure of determining delay adjustment values corresponding to the respective slave stations based on delay values corresponding to the slave stations, taking an example in which the number of the slave stations is three and distances between the three slave stations and the master station are different from each other. When the number of slave stations is changed, conversion of the delay value into the delay adjustment value may be performed based on the following procedure and the like.

The method comprises the following steps: as shown in fig. 5, the three secondary stations are a first secondary station, a second secondary station, and a third secondary station, respectively. The delay value of the optical fiber link between the first slave station and the master station, which is measured in the first stage, is t ₁ The delay value of the optical fiber link between the second slave station and the master station is t ₂ The delay value of the optical fiber link between the third slave station and the master station is t ₃ And t ₁ <t ₂ <t ₃ . First, the delay adjustment value of the third slave station is determined as zero value, and the delay adjustment value of the second slave station is determined as t ₃ - t ₂ And determining a delay adjustment value of the first slave station as t ₃ - t ₁ Finally, determining the delay adjustment value of the master station itself as t according to all the delay values ₃ The time-frequency extension of each secondary station is used for carrying out the hardware time delay of SerDes frame decomposition, the corresponding hardware time delay of SerDes frame decomposition of each secondary station is the same, meanwhile, the hardware time delay of the time-frequency host of the primary station for carrying out SerDes frame decomposition is the same as that of each secondary station, in the embodiment, the value of a is 6ns based on the specific hardware structures of the time-frequency extension and the time-frequency extension, and finally the delay of command pulses received by the DBF extension of each secondary station and the DBF host of the primary station compared with the initializing pulse is t ₃ +6ns, realizes that each instruction pulse reaches each secondary station and primary station simultaneously, finishesTime delay compensation is achieved. In addition, in this embodiment, because the transmission link between the DBF host and the time-frequency host is very short, and the transmission link between the DBF extension and the time-frequency extension is very short, no delay is defaulted, if the delay size of the transmission link needs to be precisely determined, the cable delay measurement method in the common embodiment may be adopted to test the actual cable of the transmission link to determine a specific delay value.

Further, S200 further includes the following steps:

s300, third stage:

and dynamically measuring the time delay.

Specifically, the third stage comprises the following sub-steps:

s301, each time-frequency extension transmits the second time service code obtained after the SerDes deframes to the time-frequency host machine.

S302, the time-frequency host determines dynamic update values of all time delay values according to a first time service code sent by the time-frequency host and a second time service code returned by each slave station, and updates all time delay values stored in the time-frequency host into dynamic update values of all time delay values in a one-to-one correspondence mode.

Example two

The embodiment provides a time-frequency system, which is used for performing time-frequency transmission and communication signal transmission based on the optical fiber bidirectional signal transmission delay error elimination method provided by the embodiment.

In particular, as shown in fig. 3, the time-frequency system is applied in a communication system, and is used for time service transmission and communication signal transmission between a master station and each slave station in the communication system. The time-frequency system comprises a time-frequency host and a plurality of time-frequency extensions, wherein the internal structures of the time-frequency host and each time-frequency extension are the same, the time-frequency host is arranged in a master station of the communication system, each time-frequency extension is arranged in each slave station of the communication system in a one-to-one correspondence manner, the time-frequency host is used for being connected with a DBF host in the master station and a reference clock source connected with the master station, the time-frequency host is also used for being connected with an array optical transceiver in the master station, the array optical transceiver in the master station is connected with an intra-cabin optical transceiver in the master station, the time-frequency extension is used for being connected with the DBF extension in the slave station where the time-frequency extension is located, and the time-frequency extension is also used for being connected with the array optical transceiver in the slave station where the time-frequency extension is located, the array optical transceiver in the slave station is connected with the intra-cabin optical transceiver in the slave station, and the intra-cabin optical transceiver in the master station is connected with the intra-cabin optical transceiver in the slave station through optical fiber communication.

As shown in fig. 4, the time-frequency host comprises an FPGA module, a TDC time difference measurement module, a main control module, a crystal oscillator and a PLL module, where the main control module is connected with the FPGA module, the crystal oscillator and the PLL module respectively, the main control module is further connected with a reference clock source, the FPGA module is further connected with the DBF host, the FPGA module is further connected with each time-frequency extension through an array surface optical transceiver in the main station, an in-cabin optical transceiver in the main station and an optical fiber, and the FPGA module is further connected with the TDC time difference measurement module.

The main control module is used for acquiring time service information from a reference clock source, generating an initialization pulse based on the acquired time service information, and sending the initialization pulse to the FPGA module. In this embodiment, the reference clock source is preferably a satellite receiver connected to the master station, the type of time service information sent by the satellite receiver to the master control module is preferably a 1pps+tod signal, and the initializing pulse frequency is preferably 10MHz. After receiving the time service information of the satellite receiver, the main control module carries out local crystal oscillator taming according to the time service information of the satellite receiver, when the local crystal oscillator is tamed, the PLL module is used for measuring the time difference between a local reference clock output by the crystal oscillator and 1PPS second pulse generated by the satellite receiver, the main control module generates a voltage control signal according to the time difference measuring result, the crystal oscillator adjusts the output frequency according to the voltage control signal, and further, taming of the crystal oscillator and timing of the local reference clock are realized, and according to the description, the crystal oscillator taming process is the taming process in the common embodiment.

The FPGA module is used for generating a first time service code which does not contain service information according to the initialization pulse and sending the first time service code to each time-frequency extension set through the optical fiber. The first time service code generated based on the initialization pulse is synchronized with the initialization pulse. The first time service code is preferably a non-standard time code, wherein the non-standard time code is preferably a non-standard IRIG-B code, and the non-standard IRIG-B code is an IRIG-B code with different code rate and symbol pulse width. In this embodiment, the rate of the nonstandard IRIG-B code is 10MHz, the pulse width of each symbol is 0.1us, and the total of 100 symbols, and the fact that no service information is included means that: the time service transmission information such as day, time, minute, second and the like is not included.

The FPGA module is also used for receiving the first time service codes returned by each time-frequency extension set and sending the first time service codes sent by the FPGA module and the first time service codes returned by each time-frequency extension set to the TDC time difference measuring module.

The TDC time difference measuring module is used for measuring the time difference between the first time service code sent by the FPGA module and the first time service code returned by each time-frequency extension, and sending each time difference to the main control module through the FPGA module.

The master control module is used for determining each time delay value according to each time difference, each time delay value is used for representing the link transmission time delay between the master station and each slave station in a one-to-one correspondence mode, each time delay value corresponds to each slave station in a one-to-one correspondence mode, then the master control module determines a time delay adjustment value corresponding to each slave station according to the time delay value corresponding to each slave station, determines the time delay adjustment value of the master station according to all the time delay values, and sends each time delay adjustment value to the FPGA module. In addition, the main control module is also used for storing each time delay value.

The FPGA module is used for delaying the initialization pulse according to each time delay adjustment value, and obtaining a target pulse corresponding to the time delay adjustment value after delaying, wherein the delay value between the target pulse and the initialization pulse is the time delay adjustment value.

The FPGA module is further used for generating second time service codes containing service information based on one-to-one correspondence of target pulses, then carrying out SerDes framing on command pulses generated by the DBF host and the second time service codes respectively, generating communication serial codes corresponding to the second time service codes after the SerDes framing is completed, sending the communication serial codes to the slave stations in one-to-one correspondence, and returning the communication serial codes corresponding to the master station, wherein the slave stations and the master station receive the communication serial codes corresponding to the slave stations at the same time.

The FPGA module is also used for carrying out SerDes frame decoding on the communication serial code received by the FPGA module, obtaining an instruction pulse and a second time service code after SerDes frame decoding, and the time-frequency host machine is used for transmitting the instruction pulse obtained by frame decoding to the DBF host machine and carrying out master station time correction according to the second time service code. The SerDes framing and SerDes de framing by the FPGA module are inverse processes, and the SerDes framing and SerDes de framing are preferably realized based on a SerDes serial de-serialization unit in the FPGA module, and the SerDes framing and SerDes de framing processes are based on processes in the common embodiment.

As one preferable mode, the master control module determines the delay adjustment value corresponding to each slave station according to the delay value corresponding to each slave station, and determines the delay adjustment value of the master station according to all the delay values, and the specific process is as follows:

the master control module judges the maximum value in the delay values corresponding to the slave stations.

The master control module determines the delay adjustment value of the slave station corresponding to the maximum delay value as a zero value, and determines the delay adjustment value corresponding to each other slave station as a difference value between the maximum delay value and the delay value corresponding to the slave station.

The master control module determines the own delay adjustment value of the master station as the sum of the maximum delay value and a first preset value according to all delay values, the first preset value is the hardware delay of the SerDes frame decoding for the FPGA module of each slave station, the hardware delay of the SerDes frame decoding corresponding to each slave station is the same, and the hardware delay of the SerDes frame decoding for the FPGA module of the master station is the same as that of each slave station.

The following describes a procedure of determining delay adjustment values corresponding to the respective slave stations based on delay values corresponding to the slave stations, taking an example in which the number of the slave stations is three and distances between the three slave stations and the master station are different from each other. When the number of slave stations is changed, conversion of the delay value into the delay adjustment value may be performed based on the following procedure and the like. The method comprises the following steps: each secondary station is a first secondary station, a second secondary station and a third secondary station respectively; the main control module sorts the time delay values according to the order from small to large, and the time delay values after sorting are time delay values t in turn ₁ Delay value t ₂ And a delay value t ₃ Wherein the delay value t ₁ For the delay value corresponding to the first slave station, the delay value t ₂ For the delay value t corresponding to the second slave station ₃ For the delay value, t, corresponding to the third slave station ₁ <t ₂ <t ₃ The method comprises the steps of carrying out a first treatment on the surface of the Determining the delay adjustment value of the third slave station as zero value and the delay adjustment value of the second slave station as t ₃ - t ₂ And determining a delay adjustment value of the first slave station as t ₃ - t ₁ The method comprises the steps of carrying out a first treatment on the surface of the Determining the time delay adjustment value of the master station as t according to all the time delay values ₃ And +a, wherein a is a first preset value and represents the hardware time delay of the SerDes frame decoding by the FPGA module of each slave station, and the hardware time delay of the SerDes frame decoding in each slave station and the master station is the same. In this embodiment, the FPGA module performs hardware delay a of SerDes de frame decoding to take a value of 6ns, and performs delay compensation based on the delay adjustment value, so that delay of command pulses received by the DBF slave of each slave station and the DBF host of the master station compared with the initialization pulse is t ₃ +6ns。

Preferably, the time-frequency host further comprises a DPLL phase modulation module and an optical module. The DPLL (digital phase-locked loop) phase modulation module is respectively connected with the FPGA module and the main control module, the optical module is connected with the FPGA module, and the optical module is also used for being connected with an array plane optical transceiver in the main station. The DPLL phase modulation module is preferably a DPLL chip model AD 9545.

The optical module is used for carrying out electro-optical conversion on the first time service code and each communication serial code generated by the FPGA module, and sending the first time service code and each communication serial code after the electro-optical conversion to the array plane optical transceiver in the master station.

The master control module is also used for generating a first working clock based on the acquired time service information and sending the first working clock to the FPGA module and the DPLL phase modulation module. In this embodiment, the frequency of the first operation clock is preferably 200MHz.

The main control module is further configured to correspondingly decompose each delay adjustment value into a first value and a second value, send the first value to the FPGA module, and send the second value to the DPLL phase modulation module, where the first value is a product of a quotient value obtained by dividing the delay adjustment value by a first working clock period and a first working clock period, and the second value is a remainder value obtained by dividing the delay adjustment value by the first working clock period. For example, the delay adjustment value is 5005ps, then the first value=5 ns and the second value=5 ps.

The DPLL phase modulation module is used for respectively shifting the phase of the first working clock according to each second numerical value, generating each local delay clock corresponding to each second numerical value one by one after the phase shifting, and sending each local delay clock to the FPGA module, wherein the delay of each local delay clock compared with the first working clock is the second numerical value corresponding to the local delay clock.

The FPGA module is further configured to delay the initialization pulse in a register beat manner according to each first value, and generate a target pulse corresponding to each first value one by one after delay, where a delay value between the target pulse and the initialization pulse is a delay adjustment value corresponding to the first value corresponding to the target pulse, the number of the register beats is a quotient value obtained by dividing the first value by a first working clock period, the clock of the register beats is a corresponding local delay clock, and the corresponding local delay clock is a local delay clock corresponding to a second value corresponding to the delay adjustment value corresponding to the first value. For example, when the delay adjustment value is 5005ps, the first value is equal to 5ns, the second value is 5ps, the number of the register beats is 1, the clock of the register beats is a local delay clock delayed by 5ps compared with the first working clock, the number of the register beats is 1, namely, the delay of the initialization pulse is 1 first working clock period, and the delay of the final target pulse compared with the initialization pulse is 5005ps. Correspondingly, if the first value is equal to 10ns, the number of the beats of the register is 2, which means that the initialization pulse is delayed by 2 first working clock cycles, namely 10ns; if the first value is equal to 15ns, the number of beats of the register is 3, which means that the initialization pulse is delayed by 3 first working clock cycles, namely 15ns; and (5) sequentially analogizing.

Because the internal structures of the time-frequency extension and the time-frequency host are the same, it is known to those skilled in the art that the FPGA module in the time-frequency extension is used for connecting with the DBF extension in the slave station where the time-frequency extension is located, the FPGA module in each time-frequency extension also respectively carries out SerDes frame decoding on the communication serial code received by the time-frequency extension itself, the SerDes frame obtains the instruction pulse and the second time service code after frame decoding, and the instruction pulse obtained by frame decoding is transmitted to the correspondingly connected DBF extension, and the slave station time correction is carried out according to the second time service code.

Preferably, the FPGA module in each time-frequency extension further transmits the second time service code obtained after the SerDes deframes are decoded back to the FPGA module in the time-frequency host. The FPGA module in the time-frequency host is also used for transmitting the second time service codes returned by the slave stations to the TDC time difference measuring module. The TDC time difference measuring module in the time-frequency host is also used for measuring new time differences between a first time service code sent by the FPGA module in the time-frequency host and a second time service code returned by each time-frequency extension, and sending each new time difference to the main control module in the time-frequency host through the FPGA module. The main control module in the time-frequency host is also used for determining the dynamic update value of each time delay value according to each new time difference, and updating each stored time delay value into the dynamic update value of each time delay value in a one-to-one correspondence manner.

Preferably, the FPGA module further receives an associated clock (associated CLK) generated by the DPLL phase modulation module, and when the second time service code and the instruction pulse generated by the DBF host are subjected to SerDes framing, the associated clock is also subjected to SerDes framing, and the frequency of the associated clock is 50MHz, and the associated clock enters the optical module, the array optical transceiver and the cabin optical transceiver, so that calibration and optimization of sampling delays in the optical module, the array optical transceiver and the cabin optical transceiver are performed.

Fig. 8 and 9 are timing diagrams of performing optical fiber bidirectional signal transmission delay error cancellation by using the time-frequency system according to the present embodiment.

As can be seen from fig. 8, after the delay measurement of the first stage is performed, the delay value t corresponding to the first slave station ₁ Delay value t corresponding to second slave station ₂ Delay value t corresponding to the third slave station ₃ All can be calculated by the following formula one:

the time delay value= [ (T6-T3) - (T5-T4) ]/2 (formula one), where T5-T4 = T3-T2 represents the hardware time delay caused by the transmission processing performed by the FPGA module, and is about 5-6 ns, and in this embodiment, the time delay value is labeled as 6ns, and T6-T3 is the time difference between the first time service code sent by the FPGA module and the first time service code returned by each slave station and calculated by the TDC time difference measurement module.

In the figure, ofm1 represents a time delay value t ₁ Ofm2 represents a time delay value t ₂ Ofm3 represents a time delay value t ₃ . The ofm1 +nonstandard time code represents a second time service code transmitted to the first secondary station and is included in a communication string code transmitted to the first secondary station. The ofm2 +nonstandard time code represents a second time service code transmitted to the second secondary station and is included in the communication string code transmitted to the second secondary station. The ofm3+ non-standard time code represents the second time service code transmitted to the third slave station and is included in the communication string code transmitted to the third slave station.

After the synchronism of the instruction pulse is tested, the instruction pulse realized by the time-frequency system realized by the embodiment achieves the synchronous precision of 3ns (1 segma), and the peak-to-peak value is synchronous within 10ns, so that the time delay error elimination of ns level is realized, and the time service precision achieves the synchronous precision within 10ns, thereby also realizing the time service precision of ns level.

The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims

1. The method is characterized in that the method is applied to a communication system, the communication system comprises a master station and a plurality of slave stations, the master station comprises a time-frequency master station and a DBF master station, each slave station comprises a time-frequency slave station and a DBF slave station, the DBF master station is connected with the time-frequency master station, the time-frequency slave station is connected with the DBF slave station, and the time-frequency master station is connected with each time-frequency slave station through optical fiber communication, and the method comprises the following steps:

powering up and initializing a communication system;

2. The method for eliminating delay error of optical fiber bi-directional signal transmission according to claim 1, further comprising:

3. The method for eliminating delay error of optical fiber bidirectional signal transmission according to claim 1, wherein the code patterns of the first time service code and the second time service code are non-standard IRIG-B codes, wherein the non-standard IRIG-B codes are IRIG-B codes with different code rate and symbol pulse width from standard IRIG-B codes; the command pulses generated by the DBF host include BW pulses, CPI pulses, FR pulses, and sub FR pulses.

4. The method for eliminating the delay error of the bidirectional signal transmission of the optical fiber according to claim 1, wherein the time-frequency host generates an initialization pulse based on the time service information acquired by the time-frequency host, and the method specifically comprises the following sub-steps:

5. The method for eliminating delay error of optical fiber bi-directional signal transmission according to claim 1, wherein,

The time-frequency host determines the time-delay adjustment value corresponding to each secondary station according to the time-delay value corresponding to each secondary station, and determines the time-delay adjustment value of the master station according to all the time-delay values, and the time-frequency host specifically comprises the following sub-steps:

6. The time-frequency system is characterized by comprising a time-frequency host and a plurality of time-frequency extensions, wherein the time-frequency host and each time-frequency extension have the same internal structure, the time-frequency host is arranged in a master station, each time-frequency extension is arranged in each slave station in a one-to-one correspondence manner, the time-frequency host is used for being connected with a DBF host in the master station and a reference clock source connected with the master station, the time-frequency extension is used for being connected with the DBF extension in the slave station where the time-frequency extension is located, and the time-frequency host is connected with each time-frequency extension through optical fiber communication; the time-frequency host comprises an FPGA module, a TDC time difference measuring module and a master control module, wherein the master control module is connected with the FPGA module, the master control module is also used for being connected with the reference clock source, the FPGA module is used for being connected with the DBF host, the FPGA module is also used for being connected with each time-frequency extension set through optical fibers, and the FPGA module is also connected with the TDC time difference measuring module;

7. The time-frequency system of claim 6, wherein the time-frequency host further comprises a DPLL phase modulation module and an optical module; the DPLL phase modulation module is respectively connected with the FPGA module and the main control module, the optical module is connected with the FPGA module, the optical module is also used for being connected with an optical terminal in the main station, and the optical terminal in the main station is connected with each time-frequency extension through optical fibers;

the DPLL phase modulation module is used for respectively shifting the phase of the first working clock according to each second numerical value, generating each local delay clock corresponding to each second numerical value one by one after the phase shifting, and sending each local delay clock to the FPGA module, wherein the delay of each local delay clock compared with the first working clock is the second numerical value corresponding to the local delay clock;

The FPGA module is further used for delaying the initialization pulse in a register beat mode according to each first numerical value, and generating target pulses corresponding to the first numerical values one by one after delaying, wherein delay values between the target pulses and the initialization pulses are delay adjustment values corresponding to the first numerical values corresponding to the target pulses, the number of the register beats is a quotient value obtained by dividing the first numerical values by a first working clock period, the clocks of the register beats are corresponding local delay clocks, and the corresponding local delay clocks are corresponding to the second numerical values corresponding to the delay adjustment values corresponding to the first numerical values.

8. A time-frequency system as claimed in claim 6, wherein,

the FPGA module in the time-frequency extension is used for being connected with the DBF extension in the secondary station where the time-frequency extension is located; the FPGA module in each time-frequency extension carries out SerDes frame decoding on the communication serial code received by the time-frequency extension, command pulses and second time service codes are obtained after SerDes frame decoding, the command pulses obtained by frame decoding are transmitted to the DBF extension correspondingly connected, and secondary station time correction is carried out according to the second time service codes;

9. A time-frequency system according to claim 7, wherein the reference clock source is a satellite receiver connected to the master station; the frequency of the first working clock is 200MHz; the DPLL phase modulation module adopts a DPLL chip with the model of AD 9545.

10. A time-frequency system as claimed in claim 6, wherein,

the master control module determines the time delay adjustment value corresponding to each slave station according to the time delay value corresponding to each slave station, and determines the time delay adjustment value of the master station according to all the time delay values, and the specific process is as follows: