CN116153990A - Super-junction IGBT device with improved terminal structure and manufacturing method - Google Patents
Super-junction IGBT device with improved terminal structure and manufacturing method Download PDFInfo
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- CN116153990A CN116153990A CN202211686094.3A CN202211686094A CN116153990A CN 116153990 A CN116153990 A CN 116153990A CN 202211686094 A CN202211686094 A CN 202211686094A CN 116153990 A CN116153990 A CN 116153990A
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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Abstract
The invention provides a super-junction IGBT device with an improved terminal structure and a manufacturing method thereof, relating to the technical field of semiconductor device manufacturing, and comprising the following steps: the substrate is provided with a current collecting structure on the back surface, an active region and a terminal region are arranged on the upper surface of the current collecting structure, and the active region and the terminal region are isolated by an isolation trench; a super junction structure and a grid electrode are formed in the active region; a deep trench terminal structure is arranged in the terminal region; the dielectric layer is formed on the upper surfaces of the active area and the terminal area; the collector electrode covers the lower surface of the collector structure; and the emitter is covered on the upper surface of the active region and the upper surface of part of the terminal region. The deep trench terminal structure has the beneficial effects that the design size of the deep trench terminal structure in the terminal region is smaller than that of the terminal structure of the traditional super-junction IGBT device, and meanwhile, the deep trench terminal structure can bear breakdown voltage which can be born by the traditional terminal structure through smaller width, so that the area utilization rate of the active region can be effectively improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a super-junction IGBT device with an improved terminal structure and a manufacturing method thereof.
Background
With the development and progress of power electronics technology, electric energy as a green energy source has gradually replaced non-clean energy sources such as thermal power generation. Data has shown that new power electronics technologies with insulated gate bipolar transistor (InsulatedGateBipolarTransistor, IGBT) devices as components have saved carbon dioxide emissions of about 334 hundred million tons over the past twenty years, corresponding to 390 decades of power generation in large power plants of 1 GW. With the continuous rising global electric energy demand, power semiconductor devices such as IGBTs are also continuously pursuing lower losses as important components for electric energy control and conversion. The super-junction IGBT device is taken as a novel silicon-based semiconductor power device, the excellent electrical performance of the super-junction IGBT device is demonstrated through experiments, and the super-junction IGBT device can achieve higher current density and lower switching loss. Because the substrate concentration of the super-junction IGBT device is higher than that of the common IGBT device, the terminal structure of the super-junction IGBT device needs to be redesigned. While a high concentration substrate requires a larger termination area to achieve the target voltage level, an increase in termination area reduces the silicon wafer utilization. Therefore, a novel small-sized terminal design is required for the super-junction IGBT device.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a super-junction IGBT device with an improved terminal structure, which comprises the following components:
the substrate, the back of the said substrate has collector structure, the upper surface of the said collector structure has active area and terminal area, isolate through isolating the ditch groove between said terminal area and the said active area;
a super junction structure and a grid electrode are formed in the active region;
a deep trench terminal structure is arranged in the terminal region;
the dielectric layer is formed on the upper surfaces of the active area and the terminal area;
the collector electrode covers the lower surface of the collector structure;
and the emitter is covered on the upper surface of the active region and part of the upper surface of the terminal region.
Preferably, the super junction structure comprises a plurality of N-type columns and P-type columns which are alternately arranged, a P-type base region is formed on the upper surface of each N-type column, and the grid electrode and the isolation groove are respectively arranged between each P-type base region and each P-type column.
Preferably, P-type active structures are formed on top of each P-type base region.
Preferably, an N-type active structure is further formed on top of the P-type base region near the gate and on top of one end of the deep trench termination structure.
Preferably, the dielectric layer is provided with a plurality of contact holes corresponding to the P-type base regions and the isolation trenches respectively; and the emitter is connected with the P-type base regions and the isolation trenches through the contact holes.
Preferably, the current collecting structure comprises a P-type current collecting layer and an N-type buffer layer;
the N-type buffer layer is formed on the lower surfaces of the active region and the terminal region;
the P-type collector layer forms the lower surface of the N-type buffer layer.
Preferably, the gate and the isolation trench penetrate through the P-type base region and extend towards the superjunction structure.
Preferably, the grid electrode is a trench grid structure or a planar grid structure.
The invention also provides a manufacturing method of the super-junction IGBT device with the improved terminal structure, which is applied to the super-junction IGBT device, and comprises the following steps:
step S1, providing a substrate, and forming a deep trench on the upper surface of the substrate;
s2, filling insulating materials in the deep trenches to form deep trench terminal structures;
s3, forming a super-junction groove on the upper surface of the substrate, filling a P-type epitaxial layer in the super-junction groove to form a P-type column, and forming N-type columns on the substrates on two sides of the P-type column;
step S4, forming a gate groove on one side of the P-type column far away from the deep groove terminal structure, forming a first groove on one side of the P-type column near the deep groove terminal structure, forming an oxide layer at the bottoms of the first groove and the gate groove, forming a gate in the gate groove, and forming an isolation groove in the first groove;
s5, forming a P-type base region on the upper surface of each N-type column, and forming an N-type active structure on the top of the P-type base region and the top of one end of the deep trench terminal structure;
s6, forming a dielectric layer on the upper surface of the substrate, and forming a plurality of contact holes corresponding to the P-type base regions and the isolation trenches in the dielectric layer;
s7, forming a P-type active structure on the top of each P-type base region;
s8, covering a metal material on the upper surface of part of the dielectric layer to form an emitter;
s9, thinning the back surface of the substrate, and forming a current collecting structure on the thinned back surface of the substrate;
and S10, covering a metal material on the bottom of the current collection structure to form a current collector.
Preferably, the current collecting structure includes a P-type current collecting layer and an N-type buffer layer, and the step S9 includes:
step S91, thinning the back surface of the substrate, and forming the N-type buffer layer on the thinned back surface of the substrate;
and step S92, forming the P-type collector layer at the bottom of the N-type buffer layer.
The technical scheme has the following advantages or beneficial effects: the design size of the deep trench terminal structure in the terminal region is smaller than that of the terminal structure of the traditional super-junction IGBT device, meanwhile, the deep trench terminal structure can bear breakdown voltage which can be borne by the traditional terminal structure through smaller width, and the area utilization rate of the active region can be effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a superjunction IGBT device with an improved termination structure in a preferred embodiment of the invention;
fig. 2 is a flow chart of a method for fabricating a super-junction IGBT device with an improved termination structure according to a preferred embodiment of the invention;
fig. 3 is a schematic sub-flow diagram of step S8 of the super-junction IGBT device with improved termination structure in the preferred embodiment of the invention;
FIG. 4 is a graph showing the potential distribution of the termination structure during forward breakdown in accordance with a preferred embodiment of the present invention;
fig. 5 to 13 are flowcharts showing a method for fabricating a super-junction IGBT device having an improved termination structure according to a preferred embodiment of the present invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, there is now provided a super-junction IGBT device with an improved termination structure, as shown in fig. 1, comprising:
the substrate 1, the back of the substrate 1 has a collector structure, the upper surface of the collector structure has active area 2 and terminal area 3, keep apart through the isolation ditch groove 4 between terminal area 3 and the active area 2;
a superjunction structure 5 and a grid electrode 6 are formed in the active region 2;
a deep trench terminal structure 7 is arranged in the terminal region 3;
the dielectric layer 8, the dielectric layer 8 is formed on the upper surfaces of the active region 2 and the terminal region 3;
a collector 9, wherein the collector 9 covers the lower surface of the collector structure;
Specifically, in this embodiment, as shown in fig. 4, which is a potential distribution diagram of the termination region in the forward breakdown, it can be seen from the figure that the breakdown voltage can reach 800V when the width of the deep trench termination structure 7 of the termination region 3 is 50 μm. The conventional terminal structure adopting the field limiting ring or the combination of the field limiting ring and the field plate generally needs 200-400 μm to meet the requirement of 800V breakdown voltage, so that the deep trench terminal structure can obviously reduce the area of a terminal region, thereby improving the area utilization rate of an active region.
In a preferred embodiment of the present invention, as shown in fig. 1, the superjunction structure 5 includes a plurality of N-type pillars 501 and P-type pillars 502 alternately arranged, a P-type base region 503 is formed on an upper surface of each N-type pillar 501, and a gate electrode 6 and an isolation trench 4 are respectively disposed between each P-type base region 503 and each P-type pillar 502.
In a preferred embodiment of the present invention, as shown in fig. 1, P-type active structures 504 are formed on top of each P-type base region 503.
In a preferred embodiment of the present invention, as shown in fig. 1, an N-type active structure 505 is also formed on top of the P-type base region 503 near the gate and on top of one end of the deep trench termination structure 7.
In a preferred embodiment of the present invention, as shown in fig. 1, the dielectric layer 11 is provided with a plurality of contact holes 1101 corresponding to the P-type base regions 503 and the isolation trenches 4, respectively; the emitter 10 is connected to each P-type base region 503 and the isolation trench 4 through each contact hole 1101.
In a preferred embodiment of the present invention, as shown in fig. 1, the current collecting structure includes a P-type current collecting layer 12 and an N-type buffer layer 13;
an N-type buffer layer 13 is formed on the lower surfaces of the active region 2 and the terminal region 3;
the P-type collector layer 12 is formed on the lower surface of the N-type buffer layer 13.
In a preferred embodiment of the present invention, as shown in fig. 1, the gate electrode 6 and the isolation trench 4 extend through the P-type base region 503 and toward the superjunction structure 5.
In a preferred embodiment of the present invention, as shown in fig. 1, the gate electrode 6 is a trench gate structure or a planar gate structure.
The invention also provides a manufacturing method of the super-junction IGBT device with the improved terminal structure, which is applied to the super-junction IGBT device, as shown in fig. 2, and comprises the following steps:
step S1, providing a substrate 100, and forming a deep trench 200 on the upper surface of the substrate 100;
step S2, filling insulating materials in the deep trenches 200 to form deep trench terminal structures 7;
step S3, forming a super junction groove 300 on the upper surface of the substrate 100, filling a P-type epitaxial layer in the super junction groove 300 to form a P-type column 502, and forming N-type columns 501 on the substrate at two sides of the P-type column 502;
step S4, forming a gate trench 400 on a side of the P-type pillar 502 away from the deep trench termination structure 7, forming a first trench 500 on a side of the P-type pillar 502 close to the deep trench termination structure 7, forming an oxide layer 600 on the bottoms of the first trench 500 and the gate trench 400, forming a gate 6 in the gate trench 400, and forming an isolation trench 4 in the first trench 500;
step S5, forming a P-type base region 503 on the upper surface of each N-type column 501, and forming an N-type active structure 505 on the top of the P-type base region 503 and the top of one end of the deep trench terminal structure 7;
step S6, forming a dielectric layer 11 on the upper surface of the substrate, and forming a plurality of contact holes 1101 in the dielectric layer 11, wherein the contact holes correspond to the P-type base regions 503 and the isolation trenches 4 respectively;
step S7, forming a P-type active structure 504 on top of each P-type base region 503;
step S8, covering the upper surface of part of the dielectric layer 11 with a metal material to form an emitter 10;
step S9, thinning the back surface of the substrate 100, and forming a current collecting structure on the thinned back surface of the substrate 100;
in step S10, the collector 9 is formed by covering the bottom of the collector structure with a metal material.
Specifically, in this embodiment, as shown in fig. 5, deep trench patterns are first etched on the front surface of the substrate 100, and then deep trenches 200 are formed by dry etching;
as shown in fig. 6, the deep trench 200 is then filled with an insulating material and the upper surface of the insulating material is polished to form a deep trench termination structure 7, in which step the width of the deep trench termination structure 7 is proportional to the critical electric field strength of the filling material, and the voltage withstand level of the deep trench termination structure 7 is brought to the designed voltage withstand level by adjusting the width of the deep trench termination structure and the filling material;
as shown in fig. 7, a superjunction trench pattern is etched in the substrate 100, and then the superjunction trench 300 is etched by dry method, a P-type epitaxial layer is filled in the superjunction trench 300 to form a P-type pillar 502, the substrate on two sides of the P-type pillar 502 is used as an N-type pillar 501, the P-type pillar 502 and the N-type pillar 501 which are alternately arranged form a superjunction structure 5, in this step, the superjunction structure 5 can also be formed in other ways, so long as the manner of forming the superjunction structure 5 in the technical scheme can be used in the technical scheme, in addition, the formation sequence of the deep trench terminal structure 7 and the superjunction structure 5 has no influence on the structure and effect of the technical scheme, and can be adjusted according to the requirement in the production process;
as shown in fig. 8, an isolation trench pattern and a gate trench pattern are then etched in the substrate 100, and the first trench 500 and the gate trench 400 are etched using a dry method, then an oxide layer 600 is formed at the bottoms of the first trench 500 and the gate trench 400, a polysilicon material is deposited in the gate trench 400 to form a gate 6, and a polysilicon material is deposited in the first trench 500 to form an isolation trench 4; the grid electrode 6 in the step is a trench grid, and a planar grid can be adopted as well, and the planar grid is also applicable to the super-junction IGBT device in the technical scheme;
as shown in fig. 9, 10 and 11, P-type impurities are then implanted into the upper surface of each N-type pillar 501 and diffused to form a P-type base region 503, and N-type impurities are implanted into the top of the P-type base region 503 and the top of the deep trench terminal structure 7 side to form an N-type active structure 505; after the N-type active structure 505 is formed, a dielectric layer 11 is formed on the upper surface of the substrate 100, and a plurality of contact holes 1101 corresponding to the P-type base regions 503 and the isolation trenches 4 are formed in the dielectric layer 11; p-type impurities are injected into the top of each P-type base region 503 to form a P-type active region structure 504 and activated, so that ohmic contact between the P-type base regions 503 and other structures is ensured;
as shown in fig. 12, an emitter 10 is formed by sputtering a metal on a part of the surface of the dielectric layer 7 and photolithography the metal. In a preferred embodiment of the present invention, the current collecting structure includes a P-type current collecting layer 12 and an N-type buffer layer 13, and as shown in fig. 3, step S9 includes:
step S91, thinning the back surface of the substrate 100, and forming an N-type buffer layer 13 on the thinned back surface of the substrate 100;
in step S92, the P-type collector layer 12 is formed at the bottom of the N-type buffer layer 13.
Specifically, in this embodiment, as shown in fig. 13, the substrate 100 is thinned, and N-type impurities and P-type impurities are sequentially injected into the thinned substrate 100 to form the N-type buffer layer 13 and the P-type collector layer 12, and finally the collector 9 is formed at the bottom of the P-type collector layer 12 by sputtering or evaporation or other processes.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.
Claims (10)
1. A superjunction IGBT device with improved termination structure, comprising:
the substrate, the back of the said substrate has collector structure, the upper surface of the said collector structure has active area and terminal area, isolate through isolating the ditch groove between said terminal area and the said active area;
a super junction structure and a grid electrode are formed in the active region;
a deep trench terminal structure is arranged in the terminal region;
the dielectric layer is formed on the upper surfaces of the active area and the terminal area;
the collector electrode covers the lower surface of the collector structure;
and the emitter is covered on the upper surface of the active region and part of the upper surface of the terminal region.
2. The super-junction IGBT device of claim 1 wherein the super-junction structure comprises a plurality of N-type pillars and P-type pillars each alternately arranged, a P-type base region is formed on an upper surface of each of the N-type pillars, and the gate and the isolation trench are respectively provided between each of the P-type base region and the P-type pillars.
3. The super-junction IGBT device of claim 2 wherein the top of each of the P-type base regions is formed with a P-type active structure, respectively.
4. The superjunction IGBT device of claim 3 wherein the top of the P-type base region near the gate and the top of one end of the deep trench termination structure are also formed with an N-type active structure.
5. The super-junction IGBT device of claim 2 wherein the dielectric layer has a plurality of contact holes corresponding to each of the P-type base region and the isolation trench, respectively; and the emitter is connected with the P-type base regions and the isolation trenches through the contact holes.
6. The super-junction IGBT device of claim 1 wherein the collector structure comprises a P-type collector layer and an N-type buffer layer;
the N-type buffer layer is formed on the lower surfaces of the active region and the terminal region;
the P-type collector layer forms the lower surface of the N-type buffer layer.
7. The superjunction IGBT device of claim 2 wherein the gate and isolation trench extend through the P type base region and toward the superjunction structure.
8. The super-junction IGBT device of claim 1 wherein the gate is a trench gate structure or a planar gate structure.
9. A method for manufacturing a superjunction IGBT device with an improved termination structure, applied to the superjunction IGBT device according to any one of claims 1 to 8, the method comprising:
step S1, providing a substrate, and forming a deep trench on the upper surface of the substrate;
s2, filling insulating materials in the deep trenches to form deep trench terminal structures;
s3, forming a super-junction groove on the upper surface of the substrate, filling a P-type epitaxial layer in the super-junction groove to form a P-type column, and forming N-type columns on the substrates on two sides of the P-type column;
step S4, forming a gate groove on one side of the P-type column far away from the deep groove terminal structure, forming a first groove on one side of the P-type column near the deep groove terminal structure, forming an oxide layer at the bottoms of the first groove and the gate groove, forming a gate in the gate groove, and forming an isolation groove in the first groove;
s5, forming a P-type base region on the upper surface of each N-type column, and forming an N-type active structure on the top of the P-type base region and the top of one end of the deep trench terminal structure;
s6, forming a dielectric layer on the upper surface of the substrate, and forming a plurality of contact holes corresponding to the P-type base regions and the isolation trenches in the dielectric layer;
s7, forming a P-type active structure on the top of each P-type base region;
s8, covering a metal material on the upper surface of part of the dielectric layer to form an emitter;
s9, thinning the back surface of the substrate, and forming a current collecting structure on the thinned back surface of the substrate;
and S10, covering a metal material on the bottom of the current collection structure to form a current collector.
10. The method according to claim 9, wherein the current collecting structure includes a P-type current collecting layer and an N-type buffer layer, and the step S9 includes:
step S91, thinning the back surface of the substrate, and forming the N-type buffer layer on the thinned back surface of the substrate;
and step S92, forming the P-type collector layer at the bottom of the N-type buffer layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211686094.3A CN116153990A (en) | 2022-12-27 | 2022-12-27 | Super-junction IGBT device with improved terminal structure and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211686094.3A CN116153990A (en) | 2022-12-27 | 2022-12-27 | Super-junction IGBT device with improved terminal structure and manufacturing method |
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| CN116153990A true CN116153990A (en) | 2023-05-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117410347A (en) * | 2023-12-15 | 2024-01-16 | 无锡美偌科微电子有限公司 | Super junction power device with low terminal area and preparation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117410347A (en) * | 2023-12-15 | 2024-01-16 | 无锡美偌科微电子有限公司 | Super junction power device with low terminal area and preparation method |
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