CN116153988A - Semiconductor device, array substrate, display panel and display device - Google Patents

Semiconductor device, array substrate, display panel and display device Download PDF

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Publication number
CN116153988A
CN116153988A CN202310179675.6A CN202310179675A CN116153988A CN 116153988 A CN116153988 A CN 116153988A CN 202310179675 A CN202310179675 A CN 202310179675A CN 116153988 A CN116153988 A CN 116153988A
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China
Prior art keywords
region
semiconductor device
channel region
gate
channel
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CN202310179675.6A
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Chinese (zh)
Inventor
张少虎
陈方
秦旭
许传志
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Priority to CN202310179675.6A priority Critical patent/CN116153988A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

The utility model discloses a semiconductor device, array substrate, display panel and display device, the semiconductor device includes the active layer of range upon range of setting, grid insulating layer and at least one grid, the active layer includes at least one channel region, source region and drain region set up in the both sides of channel region relatively, grid and channel region set up in the both sides of grid insulating layer relatively, the grid includes first grid portion and the second grid portion that are connected, first grid portion extends along first direction, second grid portion extends along the second direction, first direction and second direction are crossing, thereby can reduce the size that occupies in the first direction through addding the second grid portion in the second direction, wherein, first direction can be the width direction of frame district, and then can further reduce the semiconductor device in the length in the first direction that is frame district width direction, further realize the narrowing of frame district.

Description

Semiconductor device, array substrate, display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to a semiconductor device, an array substrate, a display panel and a display device.
Background
Organic Light-Emitting Diode (OLED) display panels have been developed so far, and the acquisition of a larger display area has been a major focus of research. However, in order to achieve light emission, the display panel needs to be provided with some necessary driving structures, such as a gate driving circuit, which creates a frame of the display panel, and how to achieve the narrowing of the frame becomes a big difficulty.
Disclosure of Invention
The invention discloses a semiconductor device, an array substrate, a display panel and a display device, which are used for further realizing a narrow frame.
In a first aspect, the present invention discloses a semiconductor device comprising an active layer, a gate insulating layer and at least one gate electrode arranged in a stack; the active layer comprises at least one channel region, a source region and a drain region, and the source region and the drain region are oppositely arranged at two sides of the channel region; the grid electrode and the channel region are oppositely arranged on two sides of the grid electrode insulating layer, the grid electrode comprises a first grid electrode part and a second grid electrode part which are connected, the first grid electrode part extends along a first direction, the second grid electrode part extends along a second direction, and the first direction and the second direction are intersected.
Optionally, the at least one gate includes a plurality of gates, the plurality of gates are electrically connected, the at least one channel region includes a plurality of channel regions, the plurality of channel regions are arranged in one-to-one correspondence with the plurality of gates, and two sides of each channel region are respectively provided with the source region and the drain region.
Optionally, the plurality of channel regions are arranged along the first direction; and the two adjacent channel regions comprise a first channel region and a second channel region, wherein the source region corresponding to the first channel region is at least partially multiplexed into the source region corresponding to the second channel region, or the drain region corresponding to the first channel region is at least partially multiplexed into the drain region corresponding to the second channel region.
Optionally, the two adjacent channel regions include a first channel region and a second channel region, and an outer side of the first channel region is surrounded by the second channel region; the source region corresponding to the first channel region is multiplexed to the source region corresponding to the second channel region, or the drain region corresponding to the first channel region is multiplexed to the drain region corresponding to the second channel region; preferably, the plurality of channel regions are nested.
Optionally, the gate further includes a third gate portion extending along a third direction, the third direction being the same as or intersecting the first direction, the third gate portion being connected to the second gate portion.
Optionally, an included angle between the first gate portion and the second gate portion is an acute angle.
In a second aspect, the present invention discloses an array substrate comprising a semiconductor device as defined in any one of the preceding claims.
Optionally, the array substrate includes a body region and a frame region surrounding the body region, and the frame region includes the semiconductor device;
optionally, the dimension of the semiconductor device in the first direction is smaller than the dimension of the semiconductor device in the second direction, wherein the first direction is the width direction of the frame region, and the second direction is the length direction of the frame region.
In a third aspect, the present invention discloses a display panel comprising an array substrate as described above;
optionally, the display panel includes a display area and a non-display area, and the non-display area includes a frame area of the array substrate.
In a fourth aspect, the present invention discloses a display device comprising a display panel as described above.
The semiconductor device comprises an active layer, a gate insulating layer and at least one gate, wherein the active layer comprises at least one channel region, a source region and a drain region, the source region and the drain region are oppositely arranged on two sides of the channel region, the gate and the channel region are oppositely arranged on two sides of the gate insulating layer, the gate comprises a first gate part and a second gate part which are connected, the first gate part extends along a first direction, the second gate part extends along a second direction, and the first direction and the second direction are intersected, so that the gate size in the first direction can be reduced by increasing the length of the second gate part in the second direction, the occupied size range of the whole gate in the first direction is reduced, the first direction can correspond to the width direction of a frame region of the semiconductor device, and the occupied size range of the semiconductor device such as a thin film transistor in the width direction of the frame region can be further reduced, and the narrowing of the frame region is further realized.
Drawings
In order to more clearly describe the embodiments of the present invention or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present invention or the background art.
Fig. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure of the semiconductor device shown in fig. 1 along a cutting line AA';
fig. 3 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 4 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 5 is a schematic cross-sectional structure of the semiconductor device shown in fig. 4 along a cutting line BB';
fig. 6 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 7 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 8 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 9 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 10 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 11 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 12 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 13 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 14 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
fig. 15 is a schematic cross-sectional structure of the semiconductor device shown in fig. 14 along a cutting line CC';
fig. 16 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;
fig. 17 is a schematic plan view of a semiconductor device according to another embodiment of the present invention;
FIG. 18 is a schematic diagram of an array substrate according to an embodiment of the present invention;
fig. 19 is a schematic structural view of a display panel according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As an alternative implementation of the present disclosure, an embodiment of the present disclosure discloses a semiconductor device. The semiconductor device may include a thin film transistor TFT, a field effect transistor MOS, or the like.
As shown in fig. 1 and 2, fig. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention, and fig. 2 is a schematic sectional view of the semiconductor device shown in fig. 1 along a cutting line AA'. The semiconductor device includes an active layer 10, a gate insulating layer 11, and at least one gate electrode 12, which are stacked.
Wherein the active layer 10 includes at least one channel region 101, a source region 102 and a drain region 103, the source region 102 and the drain region 103 are oppositely disposed at both sides of the channel region 101, and the gate electrode 12 and the channel region 101 are oppositely disposed at both sides of the gate insulating layer 11. In the active layer 10, opposite sides of each channel region 101 are provided as a source region 102 and a drain region 103, respectively. The gate electrode 12, the gate insulating layer 11 and the channel region 101 are stacked, and the gate electrode 12 and the channel region 101 are in one-to-one correspondence and are respectively located on both sides of the gate insulating layer 11. The region where the projection of the gate electrode 12 onto the active layer 10 overlaps with the active layer 10 may be the channel region 101.
The gate electrode 12 includes a first gate portion 121 and a second gate portion 122 connected, the first gate portion 121 extending in a first direction, the second gate portion 122 extending in a second direction, the first direction and the second direction intersecting. The first direction is the X direction and the second direction is the Y direction. The first gate portion 121 and the second gate portion 122 are provided in the same layer, except for the extending direction.
Since the gate electrode 12 includes the first gate electrode portion 121 extending in the first direction such as the X direction and the second gate electrode portion 122 extending in the second direction such as the Y direction, as exemplified by the gate electrode 12 extending only in the first direction in the related art, the length of the first gate electrode portion 121 required to be disposed in the first direction can be reduced by increasing the length of the gate electrode 12 in the second direction by adding the second gate electrode portion 122 as compared to the gate electrode extending only in the first direction. It is understood that the addition is referred to herein as an addition as compared to the related art in which the gate is disposed only along the first direction. The first direction may be substantially the width direction of the frame region of the array substrate to which the semiconductor device is applied, so that the occupation size of the semiconductor device, such as a thin film transistor, in the first direction, that is, the width direction of the frame region, may be further reduced, and narrowing of the frame region may be further achieved.
It can be appreciated that by increasing the length of the second gate portion 122 in the second direction to reduce the length of the first gate portion 121 to be disposed in the first direction, the total length of the gate 12 may not be reduced, so that the total length of the channel region 101 may not be reduced, and further, the frame region narrowing may be achieved, while maintaining or even improving the driving capability of the semiconductor device. It will be appreciated that the size of the gate affects the performance of the semiconductor device, and thus for one semiconductor device the size of the gate cannot be scaled down indefinitely for a narrow bezel. The proposal can solve the defect that the narrow frame is realized only by reducing the size of the grid electrode. By providing the gate electrode 12 to include the first gate electrode portion 121 and the second gate electrode portion 122 connected, the driving capability can be increased at the same frame size, and further narrowing of the frame is facilitated at the same driving capability. It is understood that in other embodiments, the second direction may correspond to a width direction of a frame region of an array substrate including the semiconductor device. Accordingly, since the first gate portion 121 is disposed in the first direction, the occupied size of the gate electrode 12 in the second direction can be reduced, which is beneficial to narrowing in the second direction.
It should be noted that the semiconductor device may be applied not only to the frame region of the array substrate or the display panel to achieve narrowing of the frame region, but also to other circuits or devices that require downsizing of transistors.
In some embodiments of the present invention, as shown in fig. 1, the first direction, such as the X direction, is perpendicular to the second direction, such as the Y direction, but the present invention is not limited thereto, and in other embodiments, as shown in fig. 3, the angle a between the first direction, such as the X direction, and the second direction, such as the Y direction, is an obtuse angle, or alternatively, the angle a between the first gate portion 121 and the second gate portion 122 is an acute angle. Of course, in other embodiments, the included angle a between the first gate portion 121 and the second gate portion 122 may be an obtuse angle, which is not described herein. Taking the XY coordinate system as an example, the X positive direction and the negative direction are collectively referred to as a first direction in this application, and the Y positive direction and the negative direction are similarly collectively referred to as a second direction.
In some embodiments of the present invention, as shown in fig. 4 and 5, the gate 12 further includes a third gate portion 123, the third gate portion 123 is connected to the second gate portion 122, and the third gate portion 123 extends along a third direction. The first gate portion 121 and the second gate portion 122 are directly connected, and the third gate portion 123 and the second gate portion 122 are directly connected. In some embodiments, as shown in fig. 4, the third direction is the same as the first direction, such as the X direction, and in other embodiments, the third direction intersects the first direction. The length of the first gate portion 121 may be greater than or equal to one half of the length of the gate electrode 12. Alternatively, the length of the first gate portion 121 may be greater than or equal to one third of the length of the gate electrode 12. Alternatively, the length of the first gate portion 121 may be greater than or equal to one-fourth of the length of the gate electrode 12. So as to reduce the manufacturing difficulty while reducing the frame size.
The included angle between the third gate portion 123 and the second gate portion 122 may be an acute angle or a right angle. Referring to fig. 4, the first gate portion 121 and the second gate portion 122 may be located on the same side of the second gate portion 122, which is beneficial to reducing the actual occupation range of the semiconductor device in the first direction and increasing the driving capability of the semiconductor device. It will be appreciated that, as long as the second gate portion 122 is provided, it is advantageous to reduce the size of the gate electrode occupying the first direction with the same gate electrode size, so that the length of the semiconductor device such as a thin film transistor in the first direction can be further reduced, which is advantageous to further achieve narrowing of the frame region. Further, by adding the third gate portion 123, the total length of the gate electrode 12 and the channel region 101 can be increased, and thus the driving capability of the semiconductor device can be enhanced while narrowing the frame region.
In some embodiments, the first gate portion 121, the second gate portion 122, and the third gate portion 123 form a closed structure.
In some embodiments of the present invention, as shown in fig. 6, the gate 12 further includes a fourth gate portion 124, the fourth gate portion 124 is connected to the first gate portion 121, and the fourth gate portion 124 extends along a fourth direction. In some embodiments, as shown in fig. 6, the fourth direction is the same as the second direction, e.g., the Y direction, and in other embodiments, the fourth direction intersects the second direction, e.g., the Y direction, alternatively, the angle between the fourth direction and the second direction may be an obtuse angle or an acute angle. Based on this, it is possible to secure narrowing of the frame region while enhancing the driving capability of the semiconductor device by providing the second gate portion 122, the third gate portion 123, and the fourth gate portion 124.
In some embodiments, the first gate portion 121, the second gate portion 122, the third gate portion 123, and the fourth gate portion 124 form a closed structure.
In some embodiments of the present invention, as shown in fig. 7 to 10, the semiconductor device includes a plurality of gates 12 and a plurality of channel regions 101, the plurality of channel regions 101 are disposed in one-to-one correspondence with the plurality of gates 12, and source regions 102 and drain regions 103 are disposed on two sides of each channel region 101. The semiconductor device including the plurality of gates 12 and the plurality of channel regions 101 is one semiconductor device. For example, for one thin film transistor, it includes a plurality of gates 12 and a plurality of channel regions 101, and the plurality of gates 12 are electrically connected. Specifically, it may be connected through the gate connection part 120.
In some embodiments, the plurality of gates 12 are electrically connected, and narrowing of the frame region can be further achieved by spatial arrangement of the plurality of gates 12, while ensuring that the driving capability of the semiconductor device is not reduced. The plurality of gates 12 may input gate signals through one wire, so as to reduce the occupied space of the wire and the like, and further achieve narrowing of the frame region.
Alternatively, as shown in fig. 7, the plurality of gates 12 may be electrically connected by direct contact connection, or, as shown in fig. 8, 9 and 10, the plurality of gates 12 may be electrically connected by indirect connection through the gate connection part 120. The gate connection portion 120 and the gate 12 may be disposed in the same layer or different layers. In other embodiments, the plurality of gates 12 may not be electrically connected, so as to input gate signals to the plurality of gates 12 through a plurality of wires, respectively.
In some embodiments, the plurality of channel regions 101 are arranged along a first direction, which may be an X-direction or a Y-direction. The X direction may be a width direction of the frame region, and the Y direction may be a length direction of the frame region. When the plurality of channel regions 101 are sequentially arranged in the width direction of the frame region, it is possible to improve the driving capability of the semiconductor device while facilitating the realization of narrowing of the frame region; when the plurality of channel regions 101 are sequentially arranged along the length direction of the frame region, further narrowing of the frame region is facilitated.
As shown in fig. 9, two adjacent channel regions 101 include a first channel region 1011 and a second channel region 1012. It will be appreciated that for two adjacent channel regions 101, one is the first channel region 1011 and the other is the second channel region 1012. In some embodiments, the source region 102 corresponding to the first channel region 1011 is at least partially multiplexed to the source region 102 corresponding to the second channel region 1012 as shown in fig. 9, or, in other embodiments, the drain region 103 corresponding to the first channel region 1011 is at least partially multiplexed to the drain region 103 corresponding to the second channel region 1012 as shown in fig. 10. The first channel region 1011 may be an annular closed structure and the second channel region 1012 may be an annular closed structure. The gate electrode and the channel region have corresponding shapes, and the gate electrode corresponding to the first channel region 1011 and the gate electrode corresponding to the second channel region 1012 are respectively annular closed structures. The region surrounding the first channel region 1011 and the second channel region 1012 may be the source region 102 or may be the drain region 103, which is not limited by the present invention. The first channel region 1011 may be a non-closed structure, the second channel region 1012 may be a non-closed structure, the source region 102 may be between the first channel region 1011 and the second channel region 1012, and the drain region 103 is correspondingly located at the other side of the first channel region 1011; or may be a drain region 103 between the first channel region 1011 and the second channel region 1012, may be a drain region 103, and correspondingly, be a source region 102 on the other side of the first channel region 1011.
In other embodiments, as shown in fig. 11, two adjacent channel regions 101 include a first channel region 1011 and a second channel region 1012, with the outside of the first channel region 1011 being surrounded by the second channel region 1012. The channel regions may be closed structures connected end to end or non-closed structures. Preferably, the plurality of channel regions 101 are nested. Accordingly, the channel region 101 is a closed structure. In some embodiments, as shown in fig. 11, the drain region 103 corresponding to the first channel region 1011 is multiplexed as the drain region 103 corresponding to the second channel region 1012, or in other embodiments, the source region 102 corresponding to the first channel region 1011 is multiplexed as the source region 102 corresponding to the second channel region 1012. In the case where a plurality of channel regions 101 are arranged in a nested manner, a source region 102 or a drain region 103 may be provided between the innermost channel region 101 and the adjacent channel region 101, and the present invention is not limited thereto. Correspondingly, for a channel region 101, around its outer periphery is a source region 102, and inside the channel is a drain region 103.
The plurality of channel regions 101, the plurality of source regions 102, and the plurality of drain regions 103 of the semiconductor device are located in the same layer. The multiplexed source regions 102 are integrally provided; the multiplexed drain region 103 is integrally provided.
In some embodiments of the present invention, as shown in fig. 12, the semiconductor device further includes a first pole 13 and a second pole 14. One of the first pole 13 and the second pole 14 is a source electrode, and the other is a drain electrode. In some embodiments, the first pole 13 is a source and the second pole 14 is a drain, and in other embodiments, the first pole 13 is a drain and the second pole 14 is a source.
The source electrode and the drain electrode can be arranged on the same layer or different layers. Alternatively, the source and drain electrodes may be located at a side of the gate electrode 12 facing away from the active layer 10, and the source and drain electrodes are isolated from the gate electrode 12 by an interlayer insulating layer. The source and the drain regions 102 and 103 are provided in correspondence with each other, and as shown in fig. 13, the source and the source regions 102 and 103 may be electrically connected to each other through a plurality of via holes 100, and the drain regions 103 may be electrically connected to each other through a plurality of via holes 100.
In some embodiments of the present invention, the plurality of first poles 13 are electrically connected and the plurality of second poles 14 are electrically connected. In some embodiments, as shown in fig. 12 and 13, the first pole 13 is disposed around the gate 12, and the gate 12 is disposed around the second pole 14, at this time, a plurality of first poles 13 may be directly connected in contact with electricity, and the first poles 13 of two adjacent gates 12 may be multiplexed, and a plurality of second poles 14 may respectively receive signals through a plurality of wires, or may be electrically connected through a sub-pole connection part 140, and receive signals through one wire, as shown in fig. 14.
In some embodiments of the present invention, as shown in fig. 15, fig. 15 is a schematic cross-sectional structure of the semiconductor device shown in fig. 14 along a cutting line CC', where the first pole 13 and the second pole 14 are arranged in the same layer, but in the case that the first pole 13 completely surrounds the second pole 14, in order to avoid overlapping the sub-pole connection portion 140 with the first pole 13, which affects the signal transmission in the first pole 13, the sub-pole connection portion 140 is arranged in a different layer from the second pole 14. Wherein 15 and 16 are a first interlayer insulating layer and a second interlayer insulating layer, respectively.
In some embodiments, as shown in fig. 14, the second pole 14 and the sub-pole connection part 140 are at least partially overlapped, as shown in fig. 15, the overlapped sub-pole connection part 140 is electrically connected to the active layer 10 through a via hole penetrating through the gate insulating layer 11 and the first interlayer insulating layer 15, the second pole 14 is electrically connected to the sub-pole connection part 140 through a via hole penetrating through the second interlayer insulating layer 16, and the second pole 14 is electrically connected to the active layer 10 through the sub-pole connection part 140. The first electrode 13 is electrically connected to the active layer 10 through a via penetrating the gate insulating layer 11, the first interlayer insulating layer 15, and the second interlayer insulating layer 16.
Of course, the present invention is not limited thereto, and in other embodiments, as shown in fig. 16, the second electrode 14 is electrically connected to the active layer 10 through a via penetrating the gate insulating layer 11 and the first interlayer insulating layer 15, the sub-electrode connection portion 140 of the overlapped portion may also be located at a side of the second electrode 14 facing away from the active layer 10, and the sub-electrode connection portion 140 is electrically connected to the second electrode 14 through a via penetrating the second interlayer insulating layer 16.
In some embodiments of the present invention, as shown in fig. 14, the shape of the orthographic projection of the gate electrode 12 on the active layer 10 is annular, the shape of the orthographic projection of the first electrode 13 on the active layer 10 may be square annular or circular annular, etc., the shape of the orthographic projection of the second electrode 14 on the active layer 10 includes a stripe shape, the orthographic projection of the second electrode 14 on the active layer 10 may be a stripe shape projection extending along the X direction, the orthographic projections of the plurality of second electrodes 14 on the active layer 10 are sequentially arranged along the Y direction, and the shape of the orthographic projection of the plurality of second electrodes 14 on the active layer 10 includes a comb shape.
However, the present invention is not limited thereto, and in other embodiments, as shown in fig. 17, the shape of the orthographic projections of the first and second poles 13 and 14 on the active layer 10 includes a comb-tooth shape, and orthographic projections of the first and second poles 13 and 14 on the active layer 10 are alternately arranged.
Of course, in other embodiments, the shapes of the gate 12, the first pole 13, and the second pole 14 may be adjusted or deformed according to different application scenarios, which is not described herein.
As an optional implementation of the disclosure, an embodiment of the present invention further discloses an array substrate, where the array substrate includes the semiconductor device disclosed in any one of the foregoing embodiments.
In some embodiments, as shown in fig. 18, fig. 18 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, where the array substrate includes a main body area AA and a frame area NA at least partially surrounding the main body area AA, and the frame area NA includes the semiconductor device according to any one of the embodiments. Optionally, the dimension of the semiconductor device in a first direction, such as the X direction, is smaller than the dimension of the semiconductor device in a second direction, such as the Y direction, the first direction, such as the X direction, being the width direction of the frame area NA and the second direction, such as the Y direction, being the length direction of the frame area NA. It will be appreciated that the structure of the side frame region NA is exaggerated for clarity of illustration and the output transistor S is exaggerated, but this does not indicate the actual widths of the side frame region NA and the output transistor S. The main body area AA includes a plurality of gate lines G, a plurality of data lines D, and a plurality of sub-pixels P, the gate lines G providing gate driving signals to the sub-pixels P, and the data lines D providing data driving signals to the sub-pixels P. The frame area NA includes a gate driving circuit connected to the plurality of gate lines G for providing gate driving signals to the plurality of gate lines G, wherein the gate driving circuit includes an output transistor S, a source or drain of which is electrically connected to the gate lines G, optionally the output transistor S is a semiconductor device as disclosed in any of the above embodiments. The output transistor S is degraded in performance in the case of size reduction, affecting the gate drive circuit performance. The influencing gate drive circuit may also comprise other semiconductor devices, which may be arranged conventionally. It will be understood that the sub-pixels P on the array substrate do not include light emitting devices, but include only pixel driving circuits for driving the light emitting devices to emit light, and after the light emitting devices are fabricated on the array substrate, the array substrate forms a display panel.
Of course, the present invention is not limited thereto, and in other embodiments, the semiconductor device disclosed in any of the above embodiments may be also included in other circuits of the frame area NA, which is not described herein again.
Since the output transistor S can reduce the length of the entire transistor in the width direction, such as the X direction, of the frame area NA without reducing the transistor driving capability, narrowing of the frame area NA can be further achieved.
In some embodiments, under the condition that the widths of the channel regions are the same in the same space, as shown in fig. 18, the total length of the channel regions of the output transistor in the embodiments of the present invention may be equal to 3 (2×l2+2×l1), about 180 μm, and the total length of the conventional transistor is about 150 μm, which is increased by about 20% compared to the total length of the output transistor in the embodiments of the present invention. The conventional transistor is a thin film transistor having a gate in a strip shape, and the strip-shaped gate extends along a width direction, such as an X direction, of the frame area NA.
As an optional implementation of the disclosure, an embodiment of the present invention further discloses a display panel, where the display panel includes the array substrate disclosed in any one of the embodiments above. As shown in fig. 19, fig. 19 is a schematic structural view of a display panel according to an embodiment of the present invention, which includes, but is not limited to, an LED display panel, a liquid crystal display panel, and the like. Optionally, the display panel includes a display area BA including a main body area AA provided with a driving layer including a pixel driving circuit and the like as described above, and a non-display area SA including a light emitting device, and further provided with a display layer laminated with the driving layer, the non-display area including a frame area NA of the array substrate. In the display panel, the gate driving circuit generally has a spare setting space in the length direction of the frame region, and a narrow frame requirement exists in the width direction, so that the adoption of the semiconductor device is beneficial to further realizing the narrow frame and ensuring the driving requirement.
As an optional implementation of the disclosure, an embodiment of the present invention further discloses a display device, where the display device includes a display panel as disclosed in any one of the foregoing embodiments. The display device includes, but is not limited to, a smart phone, a tablet computer, a digital camera, and the like.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.

Claims (10)

1. A semiconductor device comprising an active layer, a gate insulating layer, and at least one gate electrode, which are stacked;
the active layer comprises at least one channel region, a source region and a drain region, and the source region and the drain region are oppositely arranged at two sides of the channel region;
the grid electrode and the channel region are oppositely arranged on two sides of the grid electrode insulating layer, the grid electrode comprises a first grid electrode part and a second grid electrode part which are connected, the first grid electrode part extends along a first direction, the second grid electrode part extends along a second direction, and the first direction and the second direction are intersected.
2. The semiconductor device according to claim 1, wherein the at least one gate electrode includes a plurality of gate electrodes electrically connected, the at least one channel region includes a plurality of channel regions disposed in one-to-one correspondence with the plurality of gate electrodes, and both sides of each of the channel regions are respectively provided with the source region and the drain region.
3. The semiconductor device according to claim 2, wherein the plurality of channel regions are arranged along the first direction;
and the two adjacent channel regions comprise a first channel region and a second channel region, wherein the source region corresponding to the first channel region is at least partially multiplexed into the source region corresponding to the second channel region, or the drain region corresponding to the first channel region is at least partially multiplexed into the drain region corresponding to the second channel region.
4. The semiconductor device according to claim 2, wherein two adjacent channel regions include a first channel region and a second channel region, an outer side of the first channel region being surrounded by the second channel region;
the source region corresponding to the first channel region is multiplexed to the source region corresponding to the second channel region, or the drain region corresponding to the first channel region is multiplexed to the drain region corresponding to the second channel region;
preferably, the plurality of channel regions are nested.
5. The semiconductor device according to claim 1, wherein the gate further includes a third gate portion extending in a third direction, the third direction being the same as or intersecting the first direction, the third gate portion being connected to the second gate portion.
6. The semiconductor device of claim 1, wherein the first gate portion is at an acute angle to the second gate portion.
7. An array substrate comprising the semiconductor device according to any one of claims 1 to 6.
8. The array substrate of claim 7, wherein the array substrate comprises a body region and a border region surrounding the body region, the border region comprising the semiconductor device;
optionally, the dimension of the semiconductor device in the first direction is smaller than the dimension of the semiconductor device in the second direction, wherein the first direction is the width direction of the frame region, and the second direction is the length direction of the frame region.
9. A display panel comprising the array substrate of claim 7 or 8;
optionally, the display panel includes a display area and a non-display area, and the non-display area includes a frame area of the array substrate.
10. A display device comprising the display panel of claim 9.
CN202310179675.6A 2023-02-28 2023-02-28 Semiconductor device, array substrate, display panel and display device Pending CN116153988A (en)

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Application Number Priority Date Filing Date Title
CN202310179675.6A CN116153988A (en) 2023-02-28 2023-02-28 Semiconductor device, array substrate, display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310179675.6A CN116153988A (en) 2023-02-28 2023-02-28 Semiconductor device, array substrate, display panel and display device

Publications (1)

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CN116153988A true CN116153988A (en) 2023-05-23

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