CN116153264A - Driving method of display panel, display panel and display device - Google Patents
Driving method of display panel, display panel and display device Download PDFInfo
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- 238000004020 luminiscence type Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
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- 230000004044 response Effects 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0626—Adjustment of display parameters for control of overall brightness
Abstract
The embodiment of the application provides a driving method of a display panel, the display panel and a display device, wherein the display panel comprises a data line and a pixel circuit, the data line is electrically connected with a plurality of pixel circuits, and the plurality of pixel circuits electrically connected with the same data line comprise a first pixel circuit and a second pixel circuit; when the first pixel circuit is in the data voltage writing stage, the number of the corresponding pixel circuits in the bias stage is m 1 The method comprises the steps of carrying out a first treatment on the surface of the When the second pixel circuit is in the data voltage writing stage, the number of the corresponding pixel circuits in the bias stage is m 2 ；m 1 ≠m 2 And m is 2 ≥1，m 1 Not less than 0; wherein the data voltages transmitted by the data lines when the first pixel circuit and the second pixel circuit are in the data voltage writing stage are respectively V 1 、V 2 And V is 1 ≠V 2 . In the embodiment of the application, the display effect of the display panel is improved by compensating the data voltage transmitted by the data line.
Description
[ field of technology ]
The application relates to the technical field of display, in particular to a driving method of a display panel, the display panel and a display device.
[ background Art ]
At present, compared with the traditional liquid crystal display (Liquid Crystal Display, LCD), the Organic Light-Emitting Diode (OLED) display has the advantages of low energy consumption, fast response, high contrast, light weight and the like, and is widely applied to various devices such as smart phones, tablet computers, notebook computers, televisions, calculators and the like.
In the existing organic light-emitting diode display substrate technology, the response time of the display panel is remarkably improved by using multi-pulse driving as a common driving mode, and the problem of threshold drift of a driving transistor in a pixel circuit can be relieved. However, the conventional multi-pulse driving method also causes display unevenness of the display panel, that is, a problem of insufficient display brightness in a partial region of the display panel, for example, a problem of insufficient display brightness in a region near the upper edge of the display panel.
[ invention ]
In view of the foregoing, embodiments of the present application provide a driving method of a display panel, a display panel and a display device, so as to solve the above-mentioned problems.
In a first aspect, an embodiment of the present application provides a driving method of a display panel, where the display panel includes a data line and a pixel circuit, the data line is electrically connected to a plurality of pixel circuits, and a plurality of pixel circuits electrically connected to the same data line include a first pixel circuit and a second pixel circuit. When the display panel displays at least one frame of pure-color picture, the driving method comprises the following steps:
the first pixel circuit and the second pixel circuit electrically connected to the same data line are electrically connected to the data line when the first pixel circuit is in the data voltage writing stageThe number of the pixel circuits connected and in the bias stage is m 1 . When the second pixel circuit is in the data voltage writing stage, the number of the pixel circuits electrically connected with the data line and in the bias stage is m 2 ；m 1 ≠m 2 And m is 2 Is an integer greater than or equal to 1, m 1 Is an integer greater than or equal to 0. Wherein the data voltage transmitted by the data line in the data voltage writing stage of the first pixel circuit is V 1 The data line transmits a data voltage V in the data voltage writing stage of the second pixel circuit 2 And V is 1 ≠V 2 。
In a second aspect, embodiments of the present application provide a display panel including display driving as provided by the driving method of the first aspect.
In a third aspect, embodiments of the present application provide a display device including a display device as provided in the second aspect.
In the embodiment of the application, for the data voltages actually received by a part of pixel circuits in the data voltage writing stage are different, the problem of uneven display of the display panel is solved by adding a voltage compensation to the data voltages transmitted by the data lines when the part of pixel circuits are in the data voltage writing stage.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
fig. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present application;
FIG. 3 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 2;
fig. 4 is a schematic diagram of a data line electrically connected to a plurality of pixel circuits according to an embodiment of the present application;
FIG. 5 is a timing diagram illustrating operation of the pixel circuits of FIG. 4;
FIG. 6 is a timing chart showing the variation of the data voltages transmitted by the data lines corresponding to FIG. 5;
fig. 7 is a schematic diagram of a data line electrically connected to a plurality of pixel circuits according to an embodiment of the present application;
fig. 8 is a schematic diagram of a display device according to an embodiment of the present application.
[ detailed description ] of the invention
For a better understanding of the technical solutions of the present application, embodiments of the present application are described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and examples herein refer to values that are generally agreed upon, rather than exact, within reasonable process operating ranges or tolerances.
It should be understood that although the terms first, second, third, etc. may be used in embodiments of the present application to describe pixel circuits and transistors, etc., these pixel circuits and transistors, etc. should not be limited to these terms. These terms are only used to distinguish pixel circuits and transistors, etc. from each other. For example, a first pixel circuit may also be referred to as a second pixel circuit, similarly a second pixel circuit may also be referred to as a third pixel circuit, a first transistor may also be referred to as a second transistor, and similarly a second transistor may also be referred to as a third transistor, without departing from the scope of embodiments of the present application.
The applicant has provided a solution to the problems existing in the prior art by intensive studies.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application.
The embodiment of the present application provides a driving method of a display panel, wherein, as shown in fig. 1, the display panel 10 includes a data line DL and a pixel circuit PC, the data line DL is electrically connected with the pixel circuit PC, and the data line DL transmits a data voltage to the pixel circuit PC. The display panel 10 includes a plurality of data lines DL arranged along a first direction X and extending along a second direction Y, and the first direction X may be perpendicular to the second direction Y. The plurality of pixel circuits PC arranged along the second direction Y may be electrically connected to the same data line DL, i.e., one data line DL may be electrically connected to the plurality of pixel circuits PC arranged along the second direction Y, and the data line DL provides data voltages for the plurality of pixel circuits PC electrically connected thereto.
The display panel 10 further includes a light emitting device S, and the pixel circuit PC is electrically connected to the light emitting device S and supplies a light emitting driving current or a light emitting driving voltage to the light emitting device S. The light emitting device S may be specifically at least one of an Organic Light Emitting Diode (OLED), a micro-light emitting diode (micro-LED), a sub-millimeter light emitting diode (mini-LED), and the like.
Fig. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present application, and fig. 3 is an operation timing diagram of the pixel circuit shown in fig. 2.
As shown in fig. 2, the pixel circuit PC includes a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a storage capacitor Cst. The control terminal of the first transistor M1 is electrically connected to the control line S4, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the input terminal of the driving transistor M0; the control end of the second transistor M2 is electrically connected with the light emitting control line EM, the first electrode is electrically connected with the power supply voltage line PVDD, and the second electrode is electrically connected with the input end of the driving transistor M0; the control end of the third transistor M3 is electrically connected with the control line S1, the first electrode is electrically connected with the reset line DR, and the second electrode is electrically connected with the grid electrode of the driving transistor M0; the control end of the fourth transistor M4 is electrically connected with the control line S2, the first pole is electrically connected with the output end of the driving transistor M0, and the second pole is electrically connected with the grid electrode of the driving transistor M0; the control end of the fifth transistor M5 is electrically connected with the light-emitting control line EM, the first electrode is electrically connected with the output end of the driving transistor M0, and the second electrode is electrically connected with the light-emitting device S; the control terminal of the sixth transistor M6 is electrically connected to the control line S3, the first electrode is electrically connected to the reset line DR, and the second electrode is electrically connected to the light emitting device S; one plate of the storage capacitor Cst is electrically connected to the power supply voltage line PVDD and the other plate is electrically connected to the control terminal of the driving transistor M0.
Taking the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 included in the pixel circuit PC as P-type transistors as an example, the operation of the pixel circuit PC will be described with reference to fig. 2 and 3, and the operation of the pixel circuit PC includes a reset stage E 0 Stage E of writing data voltage 1 Stage E of luminescence 2 。
In the reset phase E 0 The control line S1 transmits a low level signal, the third transistor M3 is turned on, and the reset voltage transmitted on the reset line DR is written to the first node N1, that is, to the gate of the driving transistor M0.
In the data voltage writing stage E 1 The control line S2 and the control line S4 transmit low level signals, the first transistor M1 and the fourth transistor M4 are turned on to upload the data line DLThe input data voltage is written into the first node N1, i.e., the gate of the driving transistor M0.
In the light-emitting stage E 2 The light emitting control line EM transmits a low level signal, the second transistor M2, the driving transistor M0 and the fifth transistor M5 are turned on, and the second transistor M2 transmits the power voltage V transmitted by the power voltage line PVDD DD Is transmitted to the second node N2, i.e. the input terminal of the driving transistor M0, the driving transistor M0 receives the power supply voltage V DD And then generates a light emission driving current and transmits the light emission driving current to the input terminal of the fifth transistor M5, and the light emission driving current is transmitted to the light emitting device S through the output terminal of the fifth transistor M5.
The driving method of the display panel provided by the embodiment of the application comprises the step that when the display panel displays at least one frame of pure-color picture, at least two pixel circuits simultaneously receive data voltages transmitted by the same data line. And at the same time, at least one pixel circuit is in a data voltage writing stage, and other pixel circuits are in a biasing stage in the at least two pixel circuits which simultaneously receive the data voltage transmitted by the same data line. I.e. during at least part of the duty cycle of the display panel 10, at least part of the pixel circuits PC further comprise a biasing stage E 3 。
In the offset stage E 3 The control line S4 transmits a low level signal, the first transistor M1 is turned on, and the data voltage transmitted on the data line DL is transmitted to the third node N3, i.e., the output terminal of the driving transistor M0. In the offset stage E 3 The fourth transistor M4 is turned off.
It should be noted that the bias stage E of one pixel circuit PC 3 Data voltage writing stage E capable of other pixel circuits PC 1 Simultaneously. When one pixel circuit PC writes data voltage, at least one other pixel circuit PC electrically connected with the same data line DL with the pixel circuit PC can be in the bias stage E 3 。
Fig. 4 is a schematic diagram of a plurality of pixel circuits electrically connected to the same data line, and fig. 5 is a timing chart of operation of the plurality of pixel circuits in fig. 4. The inventive concept of the present application will be described below with reference to the operation of a plurality of pixel circuits electrically connected to the same data line DL.
Referring to fig. 4 and 5, the same data line DL is electrically connected to n pixel circuits PC, n is a positive integer greater than or equal to 3, and the n pixel circuits PC sequentially enter a data voltage writing stage E along a second direction Y 1 。
The control lines S4 electrically connected to the 1 st to nth pixel circuits PC are labeled: s41, … …, S4i, … …, S4j, … …, S4n.
Wherein at least one pixel circuit PC is in the data voltage writing stage E 1 While other circuits are in the bias stage E 3 . I.e. at least some of the n pixel circuits PC are respectively in the data voltage writing stage E 1 When the partial pixel circuits PC in the n pixel circuits are in the bias stage E 3 。
For example, as shown in fig. 5, in the process of displaying the first frame of the solid-color picture P1 on the display panel 10, when the ith pixel circuit PCi is in the data voltage writing stage E 1 At this time, the 1 st pixel circuit PC1 is in the bias stage E 3 The method comprises the steps of carrying out a first treatment on the surface of the When the jth pixel circuit PCj is in the data voltage writing stage E 1 At this time, the 1 st pixel circuit PC1 and the i-th pixel circuit PCi are both in the bias stage E 3 。
The plurality of pixel circuits PC electrically connected to the same data line DL include a first pixel circuit and a second pixel circuit, and the driving method of the display panel 10 includes, when displaying at least one frame of solid-color picture, the first pixel circuit being in the data voltage writing stage E 1 Is electrically connected with the data line DL and is in the bias stage E 3 The number of the pixel circuits PC is m 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 Is electrically connected with the data line DL and is in the bias stage E 3 The number of the pixel circuits PC is m 2 ；m 1 ≠m 2 And m is 2 Is an integer greater than or equal to 1, m 1 Is an integer greater than or equal to 0.
For example, in conjunction with fig. 4 and 5, assume that a first pixel circuit PC1 is a first pixel circuit and the ith pixel circuit PCi is a second pixel circuit, and when the display panel 10 displays the first frame of picture, no pixel circuit PC is in the data voltage writing stage E in the first pixel circuit 1 While in the offset stage E 3 M is then 1 The second pixel circuit is in the data voltage writing stage E 1 While in the offset stage E 3 M is then 2 ＝1。
For example, in fig. 4 and 5, it is assumed that the 1 st pixel circuit PC1 is a first pixel circuit and the j-th pixel circuit PCj is a second pixel circuit, and when the display panel 10 displays the first frame, no pixel circuit PC is in the data voltage writing stage E during the first pixel circuit 1 While in the offset stage E 3 M is then 1 =0; the 2 pixel circuits PC are in the data voltage writing stage E 1 While in the offset stage E 3 M is then 2 ＝2。
For example, in fig. 4 and 5, it is assumed that the ith pixel circuit PCi is a first pixel circuit and the jth pixel circuit PCj is a second pixel circuit, and when the display panel 10 displays the first frame, the 1 pixel circuit PC is in the data voltage writing stage E in the first pixel circuit 1 While in the offset stage E 3 M is then 1 =1; 2 pixel circuits are in the data voltage writing stage E 1 While in the offset stage E 3 M is then 2 ＝2。
In one frame of picture, determine m 1 、m 2 The main factors of the values include the pulse interval of the control line S4 in one frame.
The light-emitting brightness of the light-emitting device S is proportional to the light-emitting period E of the pixel circuit PC 2 The generated luminous current I d And I d ∝V DD -V data Wherein V is DD A power supply voltage V for transmitting to the pixel circuit PC for a power supply voltage line PVDD data In the data voltage writing stage E for the gate of the driving transistor M0 in the pixel circuit PC 1 The data voltage actually received. It can be seen that the light emitting device S emits light with brightness and the pixel circuit PC generates lightThe flow is inversely proportional to V data 。
In the prior art, when displaying a frame of solid-color picture, the data lines DL provide the same data voltages to the pixel circuits PC in the same-color sub-pixels. But in the data voltage writing stage E respectively in the different pixel circuits PC 1 While correspondingly being in the bias phase E 3 The number of the pixel circuits PC is different, so that the data voltages transmitted by the data lines DL are the same, but the gates of the driving transistors M0 in at least part of the pixel circuits PC are in the respective data voltage writing stage E 1 Actually received data voltage V data Different. I.e. when a frame of solid-color picture is displayed, when m 1 ≠m 2 In this case, the gates of the driving transistors M0 in the first and second pixel circuits are in the respective data voltage writing stage E 1 Received data voltage V data Are not identical; the first pixel circuit is in the data voltage writing stage E 1 Received data voltage V data Marked as V data1 The second pixel circuit is in the data voltage writing stage E 1 Received data voltage V data Marked as V data2 V is then data1 ≠V data2 . Accordingly, when the light emitting devices S electrically connected to the first pixel circuit and the second pixel circuit have different light emitting luminance, the display panel 10 may emit uneven light when displaying a screen.
In the embodiment of the present application, the driving method of the display panel 10 includes that the data line DL is in the data voltage writing stage E of the first pixel circuit when displaying the at least one frame of solid-color picture 1 The transmitted data voltage is V 1 The data line DL is in the data voltage writing stage E of the second pixel circuit 1 The transmitted data voltage is V 2 And V is 1 ≠V 2 . That is, when the display panel displays at least one frame of solid-color picture, the first pixel circuit and the second pixel circuit respectively receive different data voltages transmitted by the data lines. It can be understood that by data voltage compensation, V is made 1 ≠V 2 。
For example, in conjunction with FIGS. 5 and 6, the following is shownWhen the panel 10 displays the first frame of the solid-color picture P1, it is assumed that the 1 st pixel circuit PC1 is a first pixel circuit and the i-th pixel circuit PCi is a second pixel circuit, the first pixel circuit is in the data voltage writing stage E 1 No pixel circuit PC is in the bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 With 1 pixel circuit PC in bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 2 And V is 1 <V 2 。
For example, referring to fig. 5 and 6, when the display panel 10 displays the first frame of the solid-color picture P1, it is assumed that the ith pixel circuit PCi is a first pixel circuit and the jth pixel circuit PCj is a second pixel circuit, and the first pixel circuit is in the data voltage writing stage E 1 With 1 pixel circuit PC in bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 There are 2 pixel circuits PC in the bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 2 And V is 1 <V 2 。
For example, referring to fig. 5 and 6, when the display panel 10 displays the first frame of the solid-color picture P1, it is assumed that the 1 st pixel circuit PC1 is a first pixel circuit and the j-th pixel circuit PCj is a second pixel circuit, and the first pixel circuit is in the data voltage writing stage E 1 No pixel circuit PC is in the bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 There are 2 pixel circuits PC in the bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 2 And V is 1 <V 2 。
For example, referring to fig. 5 and 6, it is assumed that the 1 st pixel circuit PC1 is a first pixel circuit when the display panel 10 displays the first frame of the solid-color picture P1, and that the 1 st pixel circuit PC1 is a second pixel circuit when the display panel 10 displays the second frame of the solid-color picture P2, and the first pixel circuit is at the data voltage writingStage E 1 No pixel circuit PC is in the bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 With 1 pixel circuit PC in bias stage E 3 At this time, the data voltage transmitted by the data line DL is V 2 And V is 1 <V 2 。
The embodiment of the application is implemented in the data voltage writing stage E by compensating the data line DL 1 The transmitted data voltages can enable the different pixel circuits PC to respectively receive the same data writing voltage V when the display panel 10 displays a frame of pure-color picture data Further, the different pixel circuits PC are in the light emitting stage E 2 Generating luminous currents I with the same magnitude d The phenomenon of uneven light emission of the display panel 10 when displaying a picture is eliminated.
It should be noted that, since the data voltages corresponding to the light emitting devices with different colors emit the same brightness are different, the first pixel circuit and the second pixel circuit in the present application may provide driving signals for the light emitting devices with the same color for clear understanding.
In the embodiment of the present application, at least two pixel circuits PC electrically connected to the same data line DL are respectively in the data voltage writing stage E 1 When corresponding in the offset stage E 3 The number of the pixel circuits PC is different, so that the difference between the data voltages transmitted to the at least two pixel circuits PC and the data voltages actually received by the at least two pixel circuits DL is larger in the data voltage writing stage of the at least two pixel circuits PC, respectively. When the data voltage is transmitted to the data line DL, the compensated voltage is transmitted to the data line DL, so that the at least two pixel circuits PC can respectively write the data voltage into the data line DL in the data writing stage E 1 The data voltages required by it are received.
For convenience of explanation, in the embodiment of the present application, when the display panel displays a solid-color picture, the size of the data voltage transmitted from the data line DL to the different pixel circuits PC will be explained, where the solid-color picture refers to a colorA single picture with uniform brightness. In addition, in the actual product, when the display panel displays the non-solid color picture, the data lines DL may be respectively in the data voltage writing stage E of the first pixel circuits electrically connected thereto 1 A data voltage writing stage E of the second pixel circuit electrically connected with the first pixel circuit 1 The data voltages compensated to different extents are transmitted.
When the display panel 10 displays a frame of solid-color image, the data line DL is in the data voltage writing stage E 1 The transmitted data voltage is V, and is in the bias stage E 3 A portion of the data voltage is divided by the pixel circuit PC. Based on the circuit voltage division principle, when one pixel circuit is in the data voltage writing stage, the more the number of the pixel circuits which are electrically connected to the same data line and are in the bias stage, the smaller the data voltage received by the pixel circuit in the data voltage writing stage. Therefore, when one pixel circuit PC is in the data voltage writing stage E1, it is simultaneously in the bias stage E 3 The more the number of the pixel circuits PC is, the more the pixel circuits PC in the data voltage writing stage E1 are in the data writing stage E 1 Actually received data write voltage V data The smaller. Thus, for the first pixel circuit and the second pixel circuit, m 1 、m 2 、V 1 、V 2 The method comprises the following steps: m is m 2 >m 1 And V is 2 >V 1 。
For example, assume that the first pixel circuit is in data voltage writing stage E 1 Correspondingly in the bias phase E 3 The number of pixel circuits PC of (a) is m 1 The data line DL is in the data voltage writing stage E 1 The data voltage transmitted at the time is V 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 Correspondingly in the bias phase E 3 The number of pixel circuits PC of (a) is m 2 The data line DL is in the data voltage writing stage E 1 The data voltage transmitted at the time is V 2 The method comprises the steps of carrying out a first treatment on the surface of the Due to m 2 >m 1 The second pixel circuit is arranged in the data area relative to the first pixel circuitStage E of voltage writing 1 The data voltage actually received is smaller, so that the first pixel circuit and the second pixel circuit are in the data voltage writing stage E 1 The data line DL is required to be in the data voltage writing stage E in the first pixel circuit and the second pixel circuit respectively 1 The data voltage transmitted at the time satisfies V 2 >V 1 。
In the embodiment of the present application, when one pixel circuit PC is in the data voltage writing stage E1, it is simultaneously in the bias stage E 3 The more the number of the pixel circuits PC is, the more the compensation force of the data voltage transmitted to the pixel circuits PC is, and the pixel circuits PC are properly increased in the data writing stage E 1 Actually received data write voltage V data . Therefore, the different pixel circuits PC can be made to perform the data voltage writing stage E 1 The actually received data voltage is closer to the preset data voltage, so that the light-emitting brightness of the light-emitting devices respectively electrically connected with the pixel circuits is closer to the preset value.
When the display panel 10 displays a frame of solid-color picture, the pixel circuit PC is in the data voltage writing stage E 1 Correspondingly in the bias phase E 3 The number of the pixel circuits PC is m, so that the pixel circuits PC are in the light emitting stage E 2 In the light emitting stage E with other pixel circuits PC 2 Generating the same luminous current I d The data line DL is in the data voltage writing stage E in the pixel circuit PC 1 The data voltage transmitted during the time is compensated; the larger the value of m, the larger the data voltage compensated to the data line DL should be. In the embodiment of the present application, the data line DL corresponds to the pixel circuit PC with a larger m value, and the data voltage writing stage E of the pixel circuit PC 1 The greater the data voltage transmitted thereto.
In one embodiment of the present application, the plurality of pixel circuits PC electrically connected to the same data line DL include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first, second and third pixel circuits electrically connected to the same data line DL, when the first pixel circuit is in data voltage writeStage E of entry 1 Is electrically connected with the data line DL and is in the bias stage E 3 The number of pixel circuits PC is m 1 The data voltage transmitted from the data line DL to the first pixel circuit in the data voltage writing stage E1 of the first pixel circuit is V 1 The method comprises the steps of carrying out a first treatment on the surface of the When the second pixel circuit is in the data voltage writing stage E 1 Is electrically connected with the data line DL and is in the bias stage E 3 The number of pixel circuits PC is m 2 The data line DL transmits the data voltage V to the second pixel circuit in the data voltage writing stage E1 of the second pixel circuit 2 The method comprises the steps of carrying out a first treatment on the surface of the When the third pixel circuit is in the data voltage writing stage E 1 Is electrically connected with the data line DL and is in the bias stage E 3 The number of pixel circuits PC is m 3 The data line DL transmits the data voltage V to the third pixel circuit in the data voltage writing stage E1 of the third pixel circuit 3 ；m 3 >m 2 >m 1 V at the time of 3 >V 2 >V 1 . Further, when m 1 =0 and m 3 >m 2 V at the time of 3 >V 2 >V 1 。
Fig. 6 is a timing chart of a change in data voltage transmitted by the data line corresponding to fig. 5.
For example, referring to fig. 6 and 5, when the display panel 10 displays the first frame of the solid-color screen P1, it is assumed that the 1 st pixel circuit PC1 is the first pixel circuit, the i-th pixel circuit PCi is the second pixel circuit, and the j-th pixel circuit PCj is the third pixel circuit; the first pixel circuit is in the data voltage writing stage E 1 When no pixel circuit PC is in the bias stage E 3 I.e. m 1 The data voltage transmitted by the data line DL is v=0 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 At the time, 1 pixel circuit PC is in the bias stage E 3 I.e. m 2 The data voltage transmitted by the data line DL is v=1 2 And V is 2 ≥V 1 The method comprises the steps of carrying out a first treatment on the surface of the The third pixel circuit is in the data voltage writing stage E 1 At the time, 2 pixel circuits PC are in the bias stage E 3 I.e. m 2 The data voltage transmitted by the data line DL is v=2 3 And V is 3 ≥V 2 。
Further, m 1 =0 and m 3 >m 2 ，V 3 >V 2 >V 1 。
When the display panel 10 displays at least two frames of solid-color pictures, the same pixel circuit PC is respectively in the data voltage writing stage E 1 Correspondingly in the offset stage E 3 The number of pixel circuits PC of (a) is different, for example, m 1 Are not equal when the display panel 10 displays the first frame of solid-color picture P1 and the second frame of solid-color picture P2 respectively, and/or m 2 Are not equal when the display panel 10 displays the first frame of solid-color picture P1 and the second frame of solid-color picture P2 respectively, and/or m 3 When the first frame of solid-color picture P1 and the second frame of solid-color picture P2 are displayed on the display panel 10, respectively. This is mainly related to the pulse spacing of the control line S4 and the width of the front and rear lanes.
In the embodiment of the present application, the data line DL is in the data voltage writing stage E when the display panel 10 displays the first frame of the solid-color picture P1 and the second frame of the solid-color picture P2 respectively 1 The data voltages transmitted to at least part of the pixel circuits PC are different.
For example, when the display panel 10 displays the first frame of the solid-color picture P1, the first pixel circuit is in the data voltage writing stage E 1 Corresponding in offset stage E 3 The number of pixel circuits is m 11 At this time, the data voltage transmitted from the data line DL to the first pixel circuit is V 11 The method comprises the steps of carrying out a first treatment on the surface of the When the display panel 10 displays the second frame of the solid-color picture P2, the first pixel circuit is in the data voltage writing stage E 1 Corresponding in offset stage E 3 The number of pixel circuits is m 12 At this time, the data voltage transmitted from the data line DL to the first pixel circuit is V 12 . And m is 11 ≠m 12 ，V 11 ≠V 12 。
Referring to fig. 4 and 5, when the display panel 10 displays the first frame of the solid-color picture P1, the pixel circuit PC1 is in the data voltage writing stage E 1 Correspondingly in the offset stage E 3 The number of pixel circuits is m 11 =0, the data line DL is at the pixelThe circuit PC1 is in the data voltage writing stage E 1 The data voltage transmitted at the time is V 11 The method comprises the steps of carrying out a first treatment on the surface of the When the display panel 10 displays the second frame of the solid-color picture P2, the pixel circuit PC1 is in the data voltage writing stage E 12 Correspondingly in the offset stage E 3 The pixel circuit of (1) is m 12 The data line DL is in the data voltage writing stage E in the pixel circuit PC1 =1 1 The data voltage transmitted at the time is V 12 And V is 12 >V 11 . I.e. m 11 ≠m 12 ，V 11 ≠V 12 。
Fig. 7 is a schematic structural diagram of a plurality of pixel circuits electrically connected to the same data line according to an embodiment of the present application. The inventive concept of the present application will be described by taking the operation of n pixel circuits electrically connected to the same data line DL as an example.
When displaying the same frame of solid-color picture, as shown in fig. 7, it is assumed that the ith pixel circuit PCi is a first pixel circuit, the jth pixel circuit PCj is a second pixel circuit, and the data line DL is in the data voltage writing stage E in the first pixel circuit 1 The data voltage transmitted at the time is V 1 The first pixel circuit is in the data voltage writing stage E 1 Corresponding to being in the offset stage E 3 The number of pixel circuits PC of (a) is m 1 The method comprises the steps of carrying out a first treatment on the surface of the The data line DL is in the data voltage writing stage E in the second pixel circuit 1 The transmitted data voltage is V 2 The second pixel circuit is in the data voltage writing stage E 1 Corresponding to being in the offset stage E 3 The number of pixel circuits PC of (a) is m 2 . When the solid-color picture is displayed, the difference between the data voltages respectively transmitted by the first pixel circuit and the second pixel circuit is as follows: Δv=v 2 -V 1 。
Wherein DeltaV can be combined with capacitor C of data line DL load data Parasitic capacitance C inside pixel circuit PC 1 Parasitic capacitance C 2 To give a representation, C 1 For the load capacitance at node N2, C 2 Is the load capacitance at node N3.
The data lines DL and the electrically connected pixel circuits PC are considered as a numberWhen the display panel displays a frame of picture, the capacitance value of the total capacitance loaded by the same data line circuit is changed. For example, when the first pixel circuit is in the data voltage writing stage E 1 When there is m 1 The individual pixel circuits are in the bias stage E 3 The capacitance value of the total capacitance of the data line circuit where the first pixel circuit is located is (m 1 +1)*(C 1 +C 2 )+C data The method comprises the steps of carrying out a first treatment on the surface of the When the second pixel circuit (e.g., the jth pixel circuit PCj) is in the data voltage writing stage E 1 When there is m 2 The individual pixel circuits are in the bias stage E 3 The capacitance value of the total capacitance of the data line circuit where the second pixel circuit PCj is located is (m 2 +1)*(C 1 +C 2 )+C data 。
The definition of capacitance can give [ (m) 1 +1)*(C 1 +C 2 )+C data ]*V data1 ＝V 1 *C data [ (m) 2 +1)*(C 1 +C 2 )+C data ]*V data2 ＝V 2 *C data ，V data1 For the first pixel circuit in the data voltage writing stage E 1 Actually received data voltage, V data2 In the data voltage writing stage E for the second pixel circuit 1 The data voltage actually received.
In order to make the first pixel circuit and the second pixel circuit respectively in the light emitting stage E 2 Emits light of the same intensity, which is required to satisfy V data1 ＝V data2 The condition is substituted into the above relation and transformed to obtain
Or (b)
When m is 2 >m 1 In the time-course of which the first and second contact surfaces,
or->
When the display panel 10 displays a frame of solid-color image, the first pixel circuit is in the data voltage writing stage E 1 Corresponding to being in the offset stage E 3 The number of pixel circuits PC of (a) is m 1 The data line DL is in the data voltage writing stage E 1 The transmitted data voltage is V 1 The method comprises the steps of carrying out a first treatment on the surface of the The second pixel circuit is in the data voltage writing stage E 1 Corresponding to being in the offset stage E 3 The number of pixel circuits PC of (a) is m 2 And m is 2 >m 1 The data line DL is in the data voltage writing stage E in the second pixel circuit 1 The transmitted data voltage is V 2 . In general, the storage capacitor device C on the data line DL data The parameter range satisfies C data Parasitic capacitance device C inside pixel circuit PC is not less than 10pF 1 、C 2 The parameter range satisfies C 1 +C 2 Less than or equal to 50fF, and C data 、C 1 、C 2 Is obtained by substituting the usual parameter ranges of (c) into the above inequality,
or (b)
/>
As shown in fig. 1, an embodiment of the present application provides a display panel 10, and the display panel 10 performs display driving using a driving method including the driving method provided in the above embodiment.
The display panel 10 provided in the embodiment of the present application has greatly improved phenomenon of uneven luminescence.
Fig. 8 is a schematic diagram of a display device according to an embodiment of the present application.
As shown in fig. 8, an embodiment of the present application provides a display device 20, where the display device 20 includes the display panel 10 provided in the above embodiment. The display device 20 may be a mobile phone, and the display device 20 may be an electronic device such as a computer or a television.
The display device 20 provided in the embodiment of the present application has a significantly improved phenomenon of uneven luminescence.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. The driving method of the display panel is characterized in that the display panel comprises a data line and a pixel circuit, wherein the data line is electrically connected with a plurality of pixel circuits, and the plurality of pixel circuits electrically connected with the same data line comprise a first pixel circuit and a second pixel circuit; when the display panel displays at least one frame of pure-color picture, the driving method comprises the following steps:
at least two pixel circuits simultaneously receive the data voltage transmitted by the same data line, and when at least one pixel circuit in the at least two pixel circuits is in a data voltage writing stage, the other pixel circuits are in a biasing stage;
in the first pixel circuit and the second pixel circuit electrically connected to the same data line, when the first pixel circuit is in the data voltage writing stage, the number of the pixel circuits electrically connected to the data line and in the bias stage is m 1 The method comprises the steps of carrying out a first treatment on the surface of the When the second pixel circuit is in the data voltage writing stage, the number of the pixel circuits electrically connected with the data line and in the bias stage is m 2 ；m 1 ≠m 2 And m is 2 Is an integer greater than or equal to 1, m 1 Is an integer greater than or equal to 0;
wherein the data voltage transmitted by the data line in the data voltage writing stage of the first pixel circuit is V 1 The data line transmits a data voltage V in the data voltage writing stage of the second pixel circuit 2 And V is 1 ≠V 2 。
2. The driving method according to claim 1Characterized in that m 2 >m 1 And V is 2 >V 1 。
3. The driving method according to claim 1, wherein m 2 >m 1 ，ΔV＝V 2 -V 1 And (2) and
4. the driving method according to claim 1, wherein m 2 >m 1 ，ΔV＝V 2 -V 1 And (2) and
5. the driving method according to claim 1, wherein the pixel circuit includes:
a driving transistor for generating a light emission driving current;
a first transistor having an input terminal electrically connected to the data line and an output terminal electrically connected to the input terminal of the driving transistor, the first transistor being configured to transmit a data voltage on the data line to the output terminal of the driving transistor in the bias phase;
a fourth transistor having an input terminal electrically connected to the output terminal of the driving transistor, the fourth transistor being configured to transmit the data voltage to the gate of the driving transistor in the data voltage writing stage;
wherein m is 2 >m 1 ，ΔV＝V 2 -V 1 And (2) and
C 1 c is parasitic capacitance of the input end of the driving transistor 2 Parasitic electricity for the input of the fourth transistorAnd (3) capacity.
6. The driving method according to claim 1, wherein,
the pixel circuit includes:
a driving transistor for generating a light emission driving current;
a first transistor having an input terminal electrically connected to the data line and an output terminal electrically connected to the input terminal of the driving transistor, the first transistor being configured to transmit a data voltage on the data line to the output terminal of the driving transistor in the bias phase;
a fourth transistor having an input terminal electrically connected to the output terminal of the driving transistor, the fourth transistor being configured to transmit the data voltage to the gate of the driving transistor in the data voltage writing stage;
wherein m is 2 >m 1 ，ΔV＝V 2 -V 1 And (2) and
C 1 c is parasitic capacitance of the input end of the driving transistor 2 Is the parasitic capacitance of the input of the fourth transistor.
7. The driving method according to claim 1, wherein the plurality of pixel circuits electrically connected to the same data line include a first pixel circuit, a second pixel circuit, and a third pixel circuit;
among the first, second and third pixel circuits electrically connected to the same data line, when the third pixel circuit is in the data voltage writing stage, the number of the pixel circuits electrically connected to the data line and in the bias stage is m 3 The method comprises the steps of carrying out a first treatment on the surface of the The data voltage transmitted by the data line to the third pixel circuit in the data voltage writing stage of the third pixel circuit is V 3 The method comprises the steps of carrying out a first treatment on the surface of the Wherein m is 1 ＝0，m 3 >m 2 ，V 3 >V 2 >V 1 。
8. The driving method according to claim 1, wherein m 1 When the display panel displays a first frame of pure-color picture and a second frame of pure-color picture respectively, the first frame of pure-color picture and the second frame of pure-color picture are unequal;
when the display panel displays the first frame solid-color picture and the second frame solid-color picture respectively, the data lines transmit different data voltages to the first pixel circuit in the data voltage writing stage of the first pixel circuit.
9. A display panel, characterized in that display driving is performed by the driving method according to any one of claims 1 to 8.
10. A display device comprising the display panel of claim 9.
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