CN116149591B - Command mode chip data stream transmission time sequence control method and device - Google Patents
Command mode chip data stream transmission time sequence control method and device Download PDFInfo
- Publication number
- CN116149591B CN116149591B CN202310351697.6A CN202310351697A CN116149591B CN 116149591 B CN116149591 B CN 116149591B CN 202310351697 A CN202310351697 A CN 202310351697A CN 116149591 B CN116149591 B CN 116149591B
- Authority
- CN
- China
- Prior art keywords
- image data
- clock frequency
- transmission
- chip
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
Abstract
The embodiment of the application discloses a command mode chip data stream transmission time sequence control method and a device, which are applied to a display chip system, wherein the display chip system comprises an application processor, chips and a display chip, and the method comprises the following steps: acquiring a first duration, a first output resolution, a second output resolution, a first channel number and a first byte number; determining a first transmission duration according to the first duration, the first output resolution, the first channel number and the first byte number, wherein the first transmission duration is the time for an application processor to send single-line image data to a chip; determining a first clock frequency according to the first transmission duration and the second output resolution; and determining a second transmission time length according to the first clock frequency, wherein the second transmission time length is the time for transmitting the single-line image data to the display chip by the chip, and is smaller than the first transmission time length. By adopting the embodiment of the application, the control time sequence of the chip for inputting the image data and outputting the image data in the command mode can be kept balanced.
Description
Technical Field
The present application relates to the field of image data processing technologies, and in particular, to a command mode chip data stream transmission timing control method and apparatus.
Background
When the display chip system of the terminal equipment uses the chips to carry out data transmission, the chips receive image data from the application processor (application processor, AP) and are transmitted to the screen end after being processed, and the screen end displays normally in order to ensure that the input image data and the output image data of the chips are balanced when the chips are transmitted for a long time due to the limited cache space inside the chips.
Disclosure of Invention
The embodiment of the application provides a command mode chip data stream transmission time sequence control method and device, which can keep balance of control time sequences of input image data and output image data of chips in a command mode and ensure normal display of a screen end during long-time transmission.
In a first aspect, an embodiment of the present application provides a command mode chip data stream transmission timing control method, which is applied to a display chip system, where the display chip system includes an application processor, a chip and a display chip, the chip includes an image data receiving module, an image processing module, a video preprocessing module, an image display processing module and an image data transmitting module, the application processor is communicatively connected with the image data receiving module, the image data receiving module is connected with the image processing module, the image processing module is connected with the video preprocessing module, the video preprocessing module is connected with the image display processing module, the image display processing module is connected with the image data transmitting module, and the image data transmitting module is communicatively connected with the display chip; the method comprises the following steps:
Acquiring a first time length, a first output resolution, a second output resolution, a first channel number and a first byte number, wherein the first time length is the time for an application processor to send unit bit image data to a chip, the first output resolution is the output resolution of the application processor, the second output resolution is the output resolution of an image data sending module, the first channel number is the channel number used by the application processor to send the image data to the chip, and the first byte number is the byte number of one image pixel;
determining a first transmission duration according to the first duration, the first output resolution, the first channel number and the first byte number, wherein the first transmission duration is the time for an application processor to send single-line image data to a chip;
determining a first clock frequency according to the first transmission duration and the second output resolution, wherein the first clock frequency is the output clock frequency of the image display processing module;
and determining a second transmission time length according to the first clock frequency, wherein the second transmission time length is the time for the image data transmitting module to transmit the single-line image data to the display chip, and the second transmission time length is smaller than the first transmission time length.
According to the first duration of the application processor sending the unit bit image data, the first output resolution of the application processor, the second output resolution of the image data sending module, the number of channels used by the application processor to send the image data and the first byte number of one image pixel, the first transmission duration of the application processor sending the single-line image data to the chip and the second transmission duration of the image data sending module sending the single-line image data to the display chip are calculated, and according to the first transmission duration and the second transmission duration, the control time sequence of the chip inputting the image data and outputting the image data in a command mode can be kept balanced, and the display of a screen end is ensured to be normal during long-time transmission.
In one possible design, when the value of the first clock frequency is less than or equal to the first threshold value, the value of the second clock frequency is assigned as the value of the first clock frequency, and the second clock frequency is the output clock frequency of the image data transmitting module; determining a third transmission time length according to the value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data transmitting module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data transmitting module is switched from the LP mode to the HS mode; and if the third transmission duration is smaller than the first transmission duration, determining the third transmission duration as the second transmission duration.
When the value of the first clock frequency is smaller than or equal to the first threshold value, the first clock frequency and the second clock frequency use the same clock source, the third transmission duration is determined according to the value of the second clock frequency, the third duration and the fourth duration, the image data sending module uses 4-channel output, the bandwidth is required to meet the requirement, if the third transmission duration is smaller than the first transmission duration, the third transmission duration is determined to be the second transmission duration, and the balance of control time sequences of the input image data and the output image data of the chip in the command mode can be realized.
In another possible design, the third transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a third transmission duration,/->Representing a second duration, +.>Indicating a third duration, ++>And the fourth time length is represented, the second time length is the time when the image data transmitting module transmits a single-row image data packet, the output clock frequency of the image data transmitting module is equal to the value of the first clock frequency, and the second time length is determined according to the value of the first clock frequency.
In another possible design, the initial value of the second clock frequency is obtained when the value of the first clock frequency is greater than a first threshold value; determining a fourth transmission time length according to the initial value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data transmitting module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data transmitting module is switched from the LP mode to the HS mode; and if the fourth transmission duration is smaller than the first transmission duration, determining the fourth transmission duration as the second transmission duration.
When the value of the first clock frequency is larger than the first threshold value, the second clock frequency is required to be independently adapted, the initial value of the second clock frequency is acquired, the fourth transmission duration is determined according to the initial value of the second clock frequency, the third duration and the fourth duration, the image data sending module uses 4-channel output, the bandwidth is required to meet the requirement at the moment, if the fourth transmission duration is smaller than the first transmission duration, the fourth transmission duration is determined to be the second transmission duration, and the balance of control time sequences of the input image data and the output image data of the chip in the command mode can be realized.
In another possible design, if the fourth transmission time period is greater than or equal to the first transmission time period, adding a preset step value to the initial value of the second clock frequency, and determining the value of the increased second clock frequency; determining a fifth transmission time length according to the increased value of the second clock frequency, the third time length and the fourth time length; and when the fifth transmission time period is smaller than the first transmission time period, determining the fifth transmission time period as the second transmission time period.
When the fourth transmission time length is longer than or equal to the first transmission time length, the control time sequence of the input image data and the output image data of the chip in the command mode cannot be kept balanced, the second clock frequency needs to be re-adapted, the preset stepping value is added to the initial value of the second clock frequency, the value of the increased second clock frequency is determined, the fifth transmission time length is determined according to the value of the increased second clock frequency, the third time length and the fourth time length, the image data sending module uses 4-channel output, the bandwidth is required to meet the requirement at the moment, if the fifth transmission time length is smaller than the first transmission time length, the fifth transmission time length is determined to be the second transmission time length, and the control time sequence of the input image data and the output image data of the chip in the command mode can be kept balanced.
In another possible design, a first image width is determined based on the first output resolution, the first image width being a width of image data sent to the chips by the application processor; and determining a first transmission duration according to the first duration, the first image width, the first channel number and the first byte number.
The first transmission time consumed by the application processor to send the single-line image data to the chip is calculated and obtained by the time of the application processor to send the unit-bit image data to the chip, the width of the image data output by the application processor, the number of channels used by the application processor to send the image data to the chip and the number of bytes of one image pixel, and is used for subsequently determining the output clock frequency of the image display processing module.
In another possible design, the first transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a first transmission duration,/->Representing the first image width,/>Representing the first byte count,/->Representing the first channel number,/->Representing a first duration.
In another possible design, a second image width is determined according to the second output resolution, where the second image width is a width of the image data sent by the image data sending module to the display chip; a first clock frequency is determined based on the first transmission duration and the second image width.
The first clock frequency of the image display processing module is calculated by the first transmission time consumed by the application processor for transmitting the single-line image data to the chips and the width of the image data transmitted to the display chip by the image data transmitting module, and the first clock frequency is used for realizing the matching of the output clock frequency of the image display processing module and the output clock frequency of the image data transmitting module, so that the balance of the input pixel data and the output pixel data of the data path is ensured.
In another possible design, the first clock frequency satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the first clock frequency, +.>Representing a first transmission duration,/->Representing a second image width.
In a second aspect, an embodiment of the present application provides a command mode chip data stream transmission timing control apparatus, including:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a first duration, a first output resolution, a second output resolution, a first channel number and a first byte number, the first duration is the time for an application processor to send unit bit image data to a chip, the first output resolution is the output resolution of the application processor, the second output resolution is the output resolution of an image data sending module, the first channel number is the channel number used by the application processor to send the image data to the chip, and the first byte number is the byte number of one image pixel;
The processing module is used for determining a first transmission duration according to the first duration, the first output resolution, the first channel number and the first byte number, wherein the first transmission duration is the time for the application processor to send the single-line image data to the code chip;
the processing module is further used for determining a first clock frequency according to the first transmission duration and the second output resolution, wherein the first clock frequency is the output clock frequency of the image display processing module;
the processing module is further used for determining a second transmission duration according to the first clock frequency, wherein the second transmission duration is the time when the image data sending module sends the single-line image data to the display chip, and the second transmission duration is smaller than the first transmission duration.
In one possible design, the processing module is further configured to assign a value of a second clock frequency to the value of the first clock frequency when the value of the first clock frequency is less than or equal to the first threshold value, where the second clock frequency is an output clock frequency of the image data transmitting module; determining a third transmission time length according to the value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data transmitting module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data transmitting module is switched from the LP mode to the HS mode; and if the third transmission duration is smaller than the first transmission duration, determining the third transmission duration as the second transmission duration.
In another possible design, the third transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a third transmission duration,/->Representing a second duration, +.>Indicating a third duration, ++>And the fourth time length is represented, the second time length is the time when the image data transmitting module transmits a single-row image data packet, the output clock frequency of the image data transmitting module is equal to the value of the first clock frequency, and the second time length is determined according to the value of the first clock frequency.
In another possible design, the processing module is further configured to obtain an initial value of the second clock frequency when the value of the first clock frequency is greater than the first threshold value; determining a fourth transmission time length according to the initial value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data transmitting module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data transmitting module is switched from the LP mode to the HS mode; and if the fourth transmission duration is smaller than the first transmission duration, determining the fourth transmission duration as the second transmission duration.
In another possible design, the processing module is further configured to, if the fourth transmission time period is greater than or equal to the first transmission time period, add a preset step value to the initial value of the second clock frequency, and determine the added value of the second clock frequency; determining a fifth transmission time length according to the increased value of the second clock frequency, the third time length and the fourth time length; and when the fifth transmission time period is smaller than the first transmission time period, determining the fifth transmission time period as the second transmission time period.
In another possible design, the processing module is further configured to determine a first image width according to the first output resolution, where the first image width is a width of image data sent to the chip by the application processor; and determining a first transmission duration according to the first duration, the first image width, the first channel number and the first byte number.
In another possible design, the first transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a first transmission duration,/->Representing the first image width,/>Representing the first byte count,/->Representing the first channel number,/->Representing a first duration.
In another possible design, the processing module is further configured to determine a second image width according to the second output resolution, where the second image width is a width of the image data sent by the image data sending module to the display chip; a first clock frequency is determined based on the first transmission duration and the second image width.
In another possible design, the first clock frequency satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the first clock frequency, +.>Representing a first transmission duration,/->Representing a second image width.
In a third aspect, an embodiment of the present application provides a command mode chip data stream transmission timing control system, where the command mode chip data stream transmission timing control system includes a processor, a memory, and a communication bus, where the memory is configured to store computer-executed instructions; the processor is configured to execute computer-executable instructions stored in the memory to cause the speech separation system to perform the method according to any one of the first aspects; the communication bus is used for realizing connection communication between the processor and the memory.
In a fourth aspect, an embodiment of the present application provides a command mode chip data stream transmission timing control system, where the command mode chip data stream transmission timing control system may perform the method described in the first aspect. The function of the command mode chip data stream transmission time sequence control system can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above. The system may be software and/or hardware.
In a fifth aspect, an embodiment of the present application provides a computer readable storage medium for storing a computer program which, when executed, causes the method according to any one of the first aspects to be implemented.
In a sixth aspect, an embodiment of the present application provides a computer program product comprising a computer program which, when executed, causes the method according to any one of the first aspects to be carried out.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
Fig. 1 is a schematic structural diagram of a display chip system according to an embodiment of the present application;
fig. 2 is a schematic diagram of a chip structure in a display chip system according to an embodiment of the present application;
fig. 3 is a flow chart of a command mode chip data stream transmission timing control method according to an embodiment of the present application;
FIG. 4 is a flow chart of a command mode chip flow control method according to an embodiment of the present application;
FIG. 5 is an exemplary diagram of a command mode chip transfer single frame image data according to an embodiment of the present application;
FIG. 6 is a timing diagram of a command mode chip data stream transmission timing control method according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a command mode chip data stream transmission timing control device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a display chip system according to an embodiment of the present application, where the display chip system includes a chip 101, an application processor 102 and a display module 103. The application processor 102 is in communication connection with the chip 101, and the display module 103 is in communication connection with the chip 101. In the display chip system, the application processor 102 processes and outputs the image data, transmits the processed image data to the chip 101 through the communication connection, and the chip 101 receives the processed image data transmitted by the application processor 102 and transmits the processed image data to the display module 103 through the communication connection for display. However, during the actual operation of the display chip system, since the buffer space inside the chip 101 is limited, in order to ensure that the display module 103 displays normally during long-time transmission, the input image data and the output image data of the chip 101 need to be balanced. The command mode chip data stream transmission time sequence control method provided by the embodiment of the application essentially calculates the first transmission time length of the application processor 102 for transmitting the single-line image data to the chip 101 and the first clock frequency of the image display processing module in the chip 101 by means of the first time length of the application processor 102 for transmitting the single-line image data, the first output resolution of the application processor 102, the second output resolution of the image data transmitting module in the chip 101, the number of channels used by the application processor 102 for transmitting the image data and the first byte number of one image pixel, adjusts the second transmission time length of the chip 101 for transmitting the single-line image data to the display module 103 according to the first clock frequency, and can realize that the control time sequence of the input image data and the output image data of the chip in the command mode is balanced according to the first transmission time length and the second transmission time length, so that the display of the screen end is ensured to be normal during long-time transmission.
Alternatively, the display module 103 may be a touch and display driver integrated (touch and display driver integration, TDDI) chip, also called a display chip.
As shown in fig. 2, fig. 2 is a schematic diagram of a chip in a display chip system according to an embodiment of the present application, where the chip includes an image data receiving module 201, an image processing module 202, a video preprocessing module 203, an image display processing module 204, and an image data transmitting module 205. The image data receiving module 201 is connected with the image processing module 202, the image processing module 202 is connected with the video preprocessing module 203, the video preprocessing module 203 is connected with the image display processing module 204, and the image display processing module 204 is connected with the image data transmitting module 205. In addition, the image data receiving module 201 is also in communication with the application processor, and the image data transmitting module 205 is also in communication with the display module. Wherein the video preprocessing module 203 is configured to receive image data from the application processor; the image display processing module 204 is used for data processing and signal control, for example, to obtain image data from a buffer or a first-in first-out (first input first output, FIFO) channel, superimpose and mix them in a certain way, and send the final image to an external liquid crystal display (liquid crystal display, LCD) for display through a display pixel interface (display pixel interface, DPI) and a display serial interface (display serial interface, DSI) while generating necessary LCD control signals.
As shown in fig. 3, fig. 3 is a flow chart of a command mode chip data stream transmission timing control method according to an embodiment of the application, the method includes but is not limited to the following steps:
step S301: a first duration, a first output resolution, a second output resolution, a first number of lanes, and a first number of bytes are obtained.
The first duration is time for the application processor to send unit bit (bit) image data to the chip, the first output resolution is output resolution of the application processor, the second output resolution is output resolution of the image data sending module, the first channel number is the channel number used by the application processor to send the image data to the chip, and the first byte number is the byte number of one image pixel.
Specifically, since the first transmission time length consumed by the application processor to send the single-line image data to the chip cannot be detected from the image data receiving module in the command mode, the first transmission time length needs to be imported by manually configuring the customized parameter first time length, so that the output clock frequency of the image display processing module is matched with the output clock frequency of the image data sending module, the balance of the input pixel data and the output pixel data of a data path in the chip is realized, and the display of a screen end is ensured to be normal during long-time transmission.
In the embodiment of the present application, the first output resolution is determined by the image data sent by the application processor, for example, the application processor sends image data of 1080×2400 (the image width is 1080, i.e. 1080 columns of physical pixels, and the image height is 2400, i.e. 2400 rows of physical pixels) of a single frame to the chip, and then the first output resolution is equal to 1080×2400; the second output resolution is determined by the image data displayed by the display module, for example, the display module can display the image data of 720×2400 frames (the image width is 1080, i.e. 1080 columns of physical pixels, and the image height is 2400, i.e. 2400 rows of physical pixels), and then the first output resolution is equal to 1080×2400. The application processor transmits image data using 4 channels, and the chips in the command mode support transmission of RGB888 image data or 24-bit rgbg image data, and do not support transmission of 16-bit rgbg image data, wherein one pixel of RGB888 image data is equal to 3 bytes and one byte is equal to 8 bits.
Step S302: and determining the first transmission duration according to the first duration, the first output resolution, the first channel number and the first byte number.
Wherein the first transmission duration is a time at which the application processor transmits a single line of image data to the chips.
Specifically, according to the first output resolution, determining a first image width, wherein the first image width is the width of image data sent to a chip by an application processor; and determining a first transmission duration according to the first duration, the first image width, the first channel number and the first byte number. Wherein, the first transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a first transmission duration,/->Representing the first image width,/>Representing the first byte count,/->Representing the first channel number,/->Representing a first duration.
In the embodiment of the present application, the time consumed by the application processor to send the single-line image data to the chip through 4 channels is the first transmission duration, and the specific transmission process includes: first, the application processor transmits single-line image data to the image data receiving module of the chip, the image processing module of the chip receives the single-line image data, and then the image processing module of the chip transmits the single-line image data to the video preprocessing module of the chip. Furthermore, the first time period may be larger.
Alternatively, the first transmission period may be a time consumed by the application processor to transmit the single-line image data to the image data receiving module of the chip.
Step S303: a first clock frequency is determined based on the first transmission duration and the second output resolution.
The first clock frequency is the output clock frequency of the image display processing module.
Specifically, according to the second output resolution, determining a second image width, wherein the second image width is the width of image data sent to the display chip by the image data sending module; a first clock frequency is determined based on the first transmission duration and the second image width. Wherein the first clock frequency satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the first clock frequency, +.>Representing a first transmission duration,/->Representing a second image width.
In the embodiment of the present application, the sixth transmission duration may be determined according to the first transmission duration and the first clock frequency. The sixth transmission duration is the time when the image display processing module in the chip sends the single-line image data to the image data sending module, and the sixth transmission duration meets the following conditions:
；
；
wherein, the liquid crystal display device comprises a liquid crystal display device,indicates a sixth transmission duration,/->Representing the time when the image display processing module transmits the single line image data effective pixels to the image data transmission module,/-for>Representing the time spent coordinating the DPI interface with the DSI interface data stream transport, +.>Representing a first transmission duration,/->Representing the first clock frequency, +.>Is a fixed value of hardware configuration, usually set to 16 +. >。
It should be noted that, the sixth transmission duration is smaller than the first transmission duration, so as to satisfy the data stream transmission balance between the image data receiving module and the image display processing module in the chip.
Step S304: and determining a second transmission duration according to the first clock frequency.
The second transmission duration is the time for the image data transmitting module to transmit the single-line image data to the display chip, wherein the second transmission duration is smaller than the first transmission duration.
Specifically, as shown in fig. 4, fig. 4 is a flow chart of a command mode chip flow control method according to an embodiment of the present application, where the method includes, but is not limited to, the following steps:
step S401: a first clock frequency is acquired.
Step S402: it is determined whether the value of the first clock frequency is greater than a first threshold.
Specifically, when the value of the first clock frequency is equal to or less than the first threshold, step S403 is performed, and when the value of the first clock frequency is greater than the first threshold, step S406 is performed.
In an embodiment of the application, the first threshold is equal to 187MHZ.
Step S403: and assigning the value of the second clock frequency to the value of the first clock frequency, and determining a third transmission duration according to the value of the second clock frequency, the third duration and the fourth duration.
The second clock frequency is the output clock frequency of the image data transmitting module.
Specifically, the third transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a third transmission duration,/->Representing a second duration, +.>Indicating a third duration, ++>And a fourth time period is represented, wherein the third time period is the time when the image data transmitting module is switched from a High Speed (HS) mode to a low power consumption (LP) mode, the fourth time period is the time when the image data transmitting module is switched from the LP mode to the HS mode, the second time period is the time when the image data transmitting module transmits a single-row image data packet, at this time, the output clock frequency of the image data transmitting module is equal to the value of the first clock frequency, and the second time period is determined according to the value of the first clock frequency.
In the embodiment of the application, a low-voltage differential signal is adopted in the HS mode, the power consumption is larger, but the high data rate (the data rate is 80 Mbps-1.5 Gbps) can be transmitted, a single-ended signal is adopted in the LP mode, the data rate is very low (less than 10 Mbps), and the corresponding power consumption is very low. The combination of the two modes ensures that the mobile industry processor interface (mobile industry processor interface, MIPI) bus can transmit at high speeds when large amounts of image data are required to be transmitted, while reducing power consumption when large amounts of data are not required to be transmitted.
Step S404: it is determined whether the third transmission duration is less than the first transmission duration.
Specifically, when the third transmission duration is less than the first transmission duration, step S405 is executed, and when the third transmission duration is greater than or equal to the first transmission duration, step S412 is executed.
Step S405: and determining the third transmission duration as the second transmission duration.
Step S406: acquiring an initial value of the second clock frequency, and determining a fourth transmission duration according to the initial value of the second clock frequency, the third duration and the fourth duration.
Specifically, the fourth transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,indicates a fourth transmission duration,/->Indicating a fifth time period>Indicating a third duration, ++>And the fourth time length is represented, and the fifth time length is the time when the image data transmitting module transmits the single-line image data packet, at this time, the output clock frequency of the image data transmitting module is equal to the initial value of the second clock frequency, and the fifth time length is determined according to the initial value of the second clock frequency.
In an embodiment of the application, the initial value of the second clock frequency is equal to 150MHZ.
Step S407: it is determined whether the fourth transmission duration is less than the first transmission duration.
Specifically, when the fourth transmission duration is less than the first transmission duration, step S408 is performed, and when the fourth transmission duration is greater than or equal to the first transmission duration, step S409 is performed.
Step S408: and determining the fourth transmission duration as the second transmission duration.
Step S409: and adding a preset stepping value to the initial value of the second clock frequency, determining the value of the increased second clock frequency, and determining a fifth transmission duration according to the value of the increased second clock frequency, the third duration and the fourth duration.
Specifically, the fifth transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a fifth transmission duration,/->Indicating a sixth time period>Indicating a third duration, ++>And the fourth time length is represented, and the sixth time length is the time when the image data transmitting module transmits the single-line image data packet, at this time, the output clock frequency of the image data transmitting module is equal to the value of the increased second clock frequency, and the sixth time length is determined according to the value of the increased second clock frequency.
In the embodiment of the application, the preset step value is equal to 7MHZ.
Step S410: it is determined whether the fifth transmission duration is less than the first transmission duration.
Specifically, when the fifth transmission time period is less than the first transmission time period, step S411 is executed, and when the fifth transmission time period is greater than or equal to the first transmission time period, step S412 is executed.
Step S411: the fifth transmission duration is determined as the second transmission duration.
Step S412: the adaptation fails and the first time period needs to be manually corrected.
It should be noted that, when the first clock frequency of the adaptation is less than or equal to 187MHz, the output clock frequency of the image display processing module and the output clock frequency of the image data transmitting module use the same clock source, and when the two clocks are homologous, the image data transmitting module uses 4 channels to output single-line image data, and the bandwidth must meet the requirement at this time, so only the time consumed by the image data transmitting module to transmit the single-line image data to the display module is required to be ensured to be less than the first transmission duration, and the balance between the input pixel data and the output pixel data of the data path in the chip can be realized.
When the adapted first clock frequency is greater than 187MHz, the output clock frequency of the image data transmitting module needs to be adapted independently, and when the output clock frequency of the image display processing module is adapted to high frequency, the image display processing module is kept in the HS state at the first clock frequency, so that the requirement of the output clock frequency of the image data transmitting module can be reduced, and the output clock frequency of the image data transmitting module is 150MHz or more and 187MHz or less, so that the image data transmitting module can search for a suitable second clock frequency in a step increment of 7MHz from an initial value of 150MHz to satisfy the requirement that the time consumed by the image data transmitting module to transmit single-line image data to the display module is less than the first transmission time, and the balance between the input pixel data and the output pixel data of the data path in the chip can be realized.
As shown in fig. 5, fig. 5 is an exemplary diagram of a command mode chip transmission single frame image data according to an embodiment of the present application. Fig. 5 shows an example of transmission timing of image data of a single frame 4×5 (4, i.e., 4 columns of physical pixels in image width and 5, i.e., 5 rows of physical pixels in image height) of a chip transmission. In a command mode, a DSI host of an image data transmitting module in a chip automatically executes a data refreshing process, when the accumulated data amount of a buffer reaches M pixels, a transmitting condition is met, a data packet is transmitted through a long Write command Write_memory_start (WMS) and a long Write_memory_continue (WMC) of a display control command set (display command set, DCS), wherein the WMS transmits a line of data Start packet, the WMC transmits a subsequent data packet, each DCS long Write command transmits an image data packet, each image data packet includes a data ID, WC, an error correction code (error correcting code, ECC), DCS command bytes, payload data, and a checksum, and single-frame 4×5 image data needs to be transmitted in five DCS long Write commands, M is an integer greater than 0.
In the embodiment of the present application, M is generally set as a single-line image pixel amount of single-frame image data transmitted in chips. For example, a chip transfers single frame 4×5 image data, and when the accumulated data amount of the buffer reaches 4 pixels, the transmission configuration condition is satisfied.
As shown in fig. 6, fig. 6 is a timing chart of a command mode chip data stream transmission timing control method according to an embodiment of the application. The first line time sequence diagram represents a control time sequence of the application processor for transmitting the single-line image data to the chips, the second line time sequence diagram represents a control time sequence of the image display processing module of the chips for transmitting the single-line image data to the image data transmitting module of the chips, and the third line time sequence diagram represents a control time sequence of the image data transmitting module of the chips for transmitting the single-line image data to the display module.
Specifically, "WMS one line pixel" in fig. 6 indicates that the application processor transmits the first row of image data pixels to the chip; "WMC one line pixel" means that the application processor sends a subsequent single row of image data pixels to the image data receiving module of the chip; "Valid data of one line" means that the image display processing module of the chip transmits a single line of image data pixels to the image data transmitting module; "Pld _intv" means coordinating DPI interface and DSI interface data flow transmissions; "LP2HS" means that the image data transmission module of the chip is switched from LP mode to HS mode; "HS2LP" means that the image data transmission module of the chip is switched from HS mode to LP mode; the WMS represents that an image data sending module of the chip sends a row of image data initial packets to a display module; "WMC" means that the image data transmitting module of the chip transmits the subsequent single-line image data packet to the display module; "LCDC display buffer data satisfies the transmission condition" means that the image display processing module of the chip detects that the accumulated data amount in the buffer satisfies the transmission condition; the "load FIFO satisfies the setting requirement" means that the image data transmission module detects that the FIFO channel transmission load satisfies the setting requirement.
In the control timing sequence of fig. 6, the application processor sends a first row of image data pixels to the chip at a first time T1, the image data receiving module of the chip receives the first row of image data pixels from the application processor at a second time T2, the image display processing module of the chip detects that the accumulated data amount in the buffer meets the sending condition at a third time T3 and sends a single row of image data pixels to the image data sending module, the image display processing module coordinates the data stream transmission of the DPI interface and the DSI interface at a fourth time T4, the image display processing module completes the coordination process of the data stream transmission of the DPI interface and the DSI interface at a fifth time T5, the image data sending module detects that the FIFO channel transmission load meets the setting requirement and is switched to the HS mode by the LP mode at a sixth time T6, the image data sending module completes the mode switching and sends a row of image data initial packet to the display module at a seventh time T7, the image data sending module completes the sending of the image data initial packet and is switched to the LP mode by the HS mode at an eighth time T8, and the image data sending module completes the mode switching of the mode at a ninth time T9. The control timing of the chip transmission of the subsequent single-line image data is consistent with the control timing described above, and will not be described here again.
The second time T2 is after the first time T1, where the first time T1 is a time node when the application processor sends the first line of image data pixels to the chip, and the interval duration between the second time T2 and the first time T1 is a first transmission duration trx_line; the third time T3 is after the first time T1, the fourth time T4 and the fifth time T5 are after the third time T3, the third time T3 is a time node when the image display processing module of the chip sends a single row of image data pixels to the image data sending module, and the interval duration between the fifth time T5 and the third time T3 is a sixth transmission duration Tdpi_line; the sixth time T6 is after the third time T3, the seventh time T7, the eighth time T8 and the ninth time T9 are after the sixth time T6, the second time T2 is after the ninth time T9, the sixth time T6 is a time node when the image data sending module of the chip is switched from the LP mode to the HS mode, the seventh time T7 is a time node when the image data sending module of the chip sends a line of image data initial packet to the display module, and the interval duration between the ninth time T9 and the sixth time T6 is the second transmission duration Tdsi_line; and the second transmission duration is smaller than the first transmission duration, and the sixth transmission duration is smaller than the first transmission duration.
It should be noted that, the interval duration of the single-line image data pixels sent by the application processor received by the image data receiving module of the chip is substantially equal.
According to the embodiment of the application, according to the first time length of the application processor for sending the unit bit image data, the first output resolution of the application processor, the second output resolution of the image data sending module, the number of channels used by the application processor for sending the image data and the first byte number of one image pixel, the first transmission time length of the application processor for sending the single-line image data to the chip and the second transmission time length of the image data sending module for sending the single-line image data to the display chip are calculated, and according to the first transmission time length and the second transmission time length, the control time sequence of the chip for inputting the image data and outputting the image data in a command mode can be kept balanced, and the display of a screen end is ensured to be normal during long-time transmission.
As shown in fig. 7, fig. 7 is a schematic structural diagram of a command mode chip data stream transmission timing control device according to an embodiment of the present application, where the command mode chip data stream transmission timing control device is applied to a display chip system, and the command mode chip data stream transmission timing control device includes an acquisition module 701 and a processing module 702. Among them, the detailed description of each unit is as follows.
The acquisition module 701: for obtaining a first duration, a first output resolution, a second output resolution, a first number of lanes, and a first number of bytes.
The first duration is the time when the application processor transmits unit bit image data to the code chip, the first output resolution is the output resolution of the application processor, the second output resolution is the output resolution of the image data transmission module, the first channel number is the channel number used by the application processor to transmit the image data to the code chip, and the first byte number is the byte number of one image pixel.
The processing module 702: the method comprises the steps of determining a first transmission duration according to a first duration, a first output resolution, a first channel number and a first byte number, wherein the first transmission duration is the time for an application processor to send single-line image data to a chip.
Specifically, according to the first output resolution, determining a first image width, wherein the first image width is the width of image data sent to a chip by an application processor; and determining a first transmission duration according to the first duration, the first image width, the first channel number and the first byte number.
In another possible design, the first transmission duration satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing a first transmission duration,/- >Representing the first image width,/>Representing the first byte count,/->Representing the first channel number,/->Representing a first duration.
The processing module 702: and the first clock frequency is determined according to the first transmission duration and the second output resolution, and is the output clock frequency of the image display processing module.
Specifically, according to the second output resolution, determining a second image width, wherein the second image width is the width of image data sent to the display chip by the image data sending module; a first clock frequency is determined based on the first transmission duration and the second image width. The first clock frequency satisfies:
；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the first clock frequency, +.>Representing a first transmission duration,/->Representing a second image width.
The processing module 702: and the second transmission time length is determined according to the first clock frequency, and is the time for the image data transmitting module to transmit the single-line image data to the display chip, wherein the second transmission time length is smaller than the first transmission time length.
Specifically, when the value of the first clock frequency is smaller than or equal to a first threshold value, assigning the value of the second clock frequency as the value of the first clock frequency, wherein the second clock frequency is the output clock frequency of the image data sending module; determining a third transmission time length according to the value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data transmitting module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data transmitting module is switched from the LP mode to the HS mode; and if the third transmission duration is smaller than the first transmission duration, determining the third transmission duration as the second transmission duration. The third transmission duration satisfies:
；
Wherein, the liquid crystal display device comprises a liquid crystal display device,representing a third transmission duration,/->Representing a second duration, +.>Indicating a third duration, ++>And the fourth time length is represented, the second time length is the time when the image data transmitting module transmits the single-line image data packet, at this time, the output clock frequency of the image data transmitting module is equal to the value of the first clock frequency, and the second time length is determined according to the value of the first clock frequency.
Optionally, the processing module 702 is further configured to obtain an initial value of the second clock frequency when the value of the first clock frequency is greater than the first threshold value; determining a fourth transmission time length according to the initial value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data transmitting module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data transmitting module is switched from the LP mode to the HS mode; and if the fourth transmission duration is smaller than the first transmission duration, determining the fourth transmission duration as the second transmission duration.
Optionally, the processing module 702 is further configured to, if the fourth transmission time period is greater than or equal to the first transmission time period, add a preset step value to the initial value of the second clock frequency, and determine the value of the increased second clock frequency; determining a fifth transmission time length according to the increased value of the second clock frequency, the third time length and the fourth time length; and when the fifth transmission time period is smaller than the first transmission time period, determining the fifth transmission time period as the second transmission time period.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means from one website, computer, server, or data center. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. The readable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
The term "plurality" as used in the embodiments of the present application means two or more.
The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order division is made, nor is the number of the description objects in the embodiments of the present application particularly limited, and no limitation on the embodiments of the present application should be construed.
In the embodiment of the present application, the symbol "/" may indicate that the associated object is an or relationship. In addition, the symbol "/" may also denote a divisor, i.e. performing a division operation. For example, A/B may represent A divided by B.
The and/or in the embodiment of the application is used for describing the association relation of the association objects, which means that three relations can exist. For example, a and/or B may represent three cases: a alone; both A and B are present; b alone. Wherein A, B can be singular or plural.
The above embodiments are further described in detail with respect to the objects, technical solutions and advantageous effects of the present application. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. The command mode chip data stream transmission time sequence control method is characterized by being applied to a display chip system, wherein the display chip system comprises an application processor, a chip and a display chip, the chip comprises an image data receiving module, an image processing module, a video preprocessing module, an image display processing module and an image data sending module, the application processor is in communication connection with the image data receiving module, the image data receiving module is connected with the image processing module, the image processing module is connected with the video preprocessing module, the video preprocessing module is connected with the image display processing module, the image display processing module is connected with the image data sending module, and the image data sending module is in communication connection with the display chip; the method comprises the following steps:
acquiring a first duration, a first output resolution, a second output resolution, a first channel number and a first byte number, wherein the first duration is the time for the application processor to send unit bit image data to the code chip, the first output resolution is the output resolution of the application processor, the second output resolution is the output resolution of the image data sending module, the first channel number is the channel number used by the application processor to send the image data to the code chip, and the first byte number is the byte number of one image pixel;
Determining a first image width according to the first output resolution, wherein the first image width is the width of image data sent to the chip by the application processor;
determining a first transmission duration according to the first duration, the first image width, the first channel number and the first byte number, wherein the first transmission duration is the time for the application processor to send single-line image data to the code chip;
determining a second image width according to the second output resolution, wherein the second image width is the width of the image data sent to the display chip by the image data sending module;
determining a first clock frequency according to the first transmission duration and the second image width, wherein the first clock frequency is the output clock frequency of the image display processing module;
and determining a second transmission time length according to the first clock frequency, wherein the second transmission time length is the time for the image data transmitting module to transmit the single-line image data to the display chip, and the second transmission time length is smaller than the first transmission time length.
2. The method of claim 1, wherein said determining a second transmission duration based on said first clock frequency comprises:
When the value of the first clock frequency is smaller than or equal to a first threshold value, assigning a value of a second clock frequency as the value of the first clock frequency, wherein the second clock frequency is the output clock frequency of the image data sending module;
determining a third transmission time length according to the value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data sending module is switched from a high-speed HS mode to a low-power-consumption LP mode, and the fourth time length is the time when the image data sending module is switched from the LP mode to the HS mode;
and if the third transmission duration is smaller than the first transmission duration, determining the third transmission duration as the second transmission duration.
3. The method of claim 2, wherein the third transmission duration satisfies:
；
wherein the saidRepresenting said third transmission duration, said ∈>Representing a second time period, saidRepresenting said third duration, said ∈>And the fourth time period is represented, the second time period is the time when the image data transmitting module transmits a single-row image data packet, the output clock frequency of the image data transmitting module is equal to the value of the first clock frequency, and the second time period is determined according to the value of the first clock frequency.
4. The method of claim 1, wherein said determining a second transmission duration based on said first clock frequency comprises:
when the value of the first clock frequency is larger than a first threshold value, acquiring an initial value of a second clock frequency;
determining a fourth transmission time length according to the initial value of the second clock frequency, a third time length and a fourth time length, wherein the third time length is the time when the image data sending module is switched from the HS mode to the LP mode, and the fourth time length is the time when the image data sending module is switched from the LP mode to the HS mode;
and if the fourth transmission duration is smaller than the first transmission duration, determining the fourth transmission duration as the second transmission duration.
5. The method according to claim 4, wherein the method further comprises:
if the fourth transmission time length is greater than or equal to the first transmission time length, adding a preset step value to the initial value of the second clock frequency, and determining the added value of the second clock frequency;
determining a fifth transmission duration according to the increased value of the second clock frequency, the third duration and the fourth duration;
And when the fifth transmission time length is smaller than the first transmission time length, determining the fifth transmission time length as the second transmission time length.
6. The method of claim 1, wherein the first transmission duration satisfies:
；
wherein the saidRepresenting said first transmission duration, said ∈>Representing the first image width, theRepresenting said first number of bytes, said +.>Representing the number of said first channels, said +.>Representing the first duration.
7. The method of claim 1, wherein the first clock frequency satisfies:
；
wherein the saidRepresenting said first clock frequency, said ∈>Representing the first transmission duration, theRepresenting the second image width.
8. The command mode chip data stream transmission time sequence control device is characterized in that the device is applied to a display chip system, the display chip system comprises an application processor, a chip and a display chip, the chip comprises an image data receiving module, an image processing module, a video preprocessing module, an image display processing module and an image data sending module, the application processor is in communication connection with the image data receiving module, the image data receiving module is connected with the image processing module, the image processing module is connected with the video preprocessing module, the video preprocessing module is connected with the image display processing module, the image display processing module is connected with the image data sending module, and the image data sending module is in communication connection with the display chip; the device comprises:
The device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a first duration, a first output resolution, a second output resolution, a first channel number and a first byte number, the first duration is the time for the application processor to send unit bit image data to the code chip, the first output resolution is the output resolution of the application processor, the second output resolution is the output resolution of the image data sending module, the first channel number is the channel number used by the application processor to send the image data to the code chip, and the first byte number is the byte number of one image pixel;
the processing module is used for determining a first image width according to the first output resolution, wherein the first image width is the width of image data sent to the code chip by the application processor;
the processing module is further configured to determine a first transmission duration according to the first duration, the first image width, the first channel number, and the first byte number, where the first transmission duration is a time when the application processor sends single-line image data to the chip;
the processing module is further configured to determine a second image width according to the second output resolution, where the second image width is a width of image data sent by the image data sending module to the display chip;
The processing module is further configured to determine a first clock frequency according to the first transmission duration and the second image width, where the first clock frequency is an output clock frequency of the image display processing module;
the processing module is further configured to determine a second transmission duration according to the first clock frequency, where the second transmission duration is a time when the image data sending module sends the single-line image data to the display chip, and the second transmission duration is less than the first transmission duration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310351697.6A CN116149591B (en) | 2023-04-04 | 2023-04-04 | Command mode chip data stream transmission time sequence control method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310351697.6A CN116149591B (en) | 2023-04-04 | 2023-04-04 | Command mode chip data stream transmission time sequence control method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116149591A CN116149591A (en) | 2023-05-23 |
| CN116149591B true CN116149591B (en) | 2023-08-18 |
Family
ID=86339114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310351697.6A Active CN116149591B (en) | 2023-04-04 | 2023-04-04 | Command mode chip data stream transmission time sequence control method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116149591B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006268809A (en) * | 2005-03-24 | 2006-10-05 | Kaadeikku Corporation:Kk | Image-memory parallel circuit |
| EP2416230A2 (en) * | 2010-08-04 | 2012-02-08 | ASUSTeK Computer Inc. | Computer system with power saving function |
| CN104685893A (en) * | 2012-06-29 | 2015-06-03 | 弗兰霍菲尔运输应用研究公司 | Video data stream concept |
| CN111246211A (en) * | 2020-02-04 | 2020-06-05 | 中国联合网络通信集团有限公司 | Encoding method, decoding method, device, equipment and storage medium |
| CN115831032A (en) * | 2023-02-20 | 2023-03-21 | 深圳曦华科技有限公司 | Chip temperature drift processing method and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114935971A (en) * | 2021-02-05 | 2022-08-23 | 京东方科技集团股份有限公司 | Display driving chip, display device and display driving method |
-
2023
- 2023-04-04 CN CN202310351697.6A patent/CN116149591B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006268809A (en) * | 2005-03-24 | 2006-10-05 | Kaadeikku Corporation:Kk | Image-memory parallel circuit |
| EP2416230A2 (en) * | 2010-08-04 | 2012-02-08 | ASUSTeK Computer Inc. | Computer system with power saving function |
| CN104685893A (en) * | 2012-06-29 | 2015-06-03 | 弗兰霍菲尔运输应用研究公司 | Video data stream concept |
| CN111246211A (en) * | 2020-02-04 | 2020-06-05 | 中国联合网络通信集团有限公司 | Encoding method, decoding method, device, equipment and storage medium |
| CN115831032A (en) * | 2023-02-20 | 2023-03-21 | 深圳曦华科技有限公司 | Chip temperature drift processing method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116149591A (en) | 2023-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8872982B2 (en) | Transmission device and reception device for baseband video data, and transmission/reception system | |
| WO2013042264A1 (en) | Video processing device and video processing method | |
| US10657922B2 (en) | Electronic devices, method of transmitting data block, method of determining contents of transmission signal, and transmission/reception system | |
| EP3340635B1 (en) | Data transfer apparatus and data transfer method | |
| US20120147976A1 (en) | Video Transmission On A Serial Interface | |
| WO2019210022A1 (en) | Low-power states in a multi-protocol tunneling environment | |
| CN108712625B (en) | Multichannel real-time high-definition image transmission system and transmission method | |
| US20150325184A1 (en) | Source driver, driving circuit and display apparatus | |
| US20090300232A1 (en) | Data transmission method between a host device and a display apparatus | |
| CN116149591B (en) | Command mode chip data stream transmission time sequence control method and device | |
| US6948022B2 (en) | Digital image transfer controller | |
| US11115623B2 (en) | Systems and methods for asymmetric image splitter with line mark memory | |
| JPWO2020158589A1 (en) | Transmitter, transmit method, receiver, receiver, and transmitter / receiver | |
| US8793410B2 (en) | Data rate throttling in an internal packet-based interface | |
| CN115037847A (en) | Video data exchange method and system based on data packet exchange | |
| US8356331B2 (en) | Packet structure for a mobile display digital interface | |
| CN113660431A (en) | Multi-screen display method of vehicle-mounted display equipment, vehicle-mounted display equipment and vehicle | |
| CN116030748B (en) | Method and device for dynamically adjusting chip clock frequency | |
| EP2147532B1 (en) | A packet structure for a mobile display digital interface | |
| US20230171374A1 (en) | Screen control system | |
| JP6634586B2 (en) | Signal transceiver | |
| CN107978285B (en) | Apparatus and method for driving display panel in response to display data | |
| US11659136B2 (en) | Data conversion and high definition multimedia interface receiving device | |
| CN215453109U (en) | Car machine display device and car | |
| US20230379434A1 (en) | Data transmission method and apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |