CN116149203A - Control panel and test system - Google Patents
Control panel and test system Download PDFInfo
- Publication number
- CN116149203A CN116149203A CN202310226266.7A CN202310226266A CN116149203A CN 116149203 A CN116149203 A CN 116149203A CN 202310226266 A CN202310226266 A CN 202310226266A CN 116149203 A CN116149203 A CN 116149203A
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- pin
- connector
- dap
- jtag
- electrically connected
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B17/00—Systems involving the use of models or simulators of said systems
- G05B17/02—Systems involving the use of models or simulators of said systems electric
Abstract
The invention provides a control board and a test system. The control board includes: a first debug access port DAP connector; a master control chip electrically connected with pins of the first DAP connector; the target pin of the first DAP connector is electrically connected with the 10-pin DAP simulator in a first welding mode of two resistors; the target pin of the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator in a second welding mode of two resistors. The control board and the test system can realize compatible design of the DAP simulator and the JTAG simulator, meet test requirements of project development, and solve the problem of adapting to different simulator interfaces.
Description
Technical Field
The invention relates to the technical field of simulator testing, in particular to a control board and a testing system.
Background
When designing a circuit board, the control board is usually designed according to the interfaces of different simulators, the control board is matched with the connectors of the simulator ports, and two simulators need to design the control boards of two different simulator ports, so that the cost is high and the test is inflexible.
Disclosure of Invention
The invention aims to solve the technical problems of providing a control board and a test system, realizing compatible design of DAP and JTAG, meeting test requirements of project development and solving the problem of adapting to different simulator interfaces.
In order to solve the technical problems, the technical scheme of the invention is as follows:
an embodiment of the present invention provides a control board including:
a first debug access port DAP connector;
a master control chip electrically connected with pins of the first DAP connector;
the target pin of the first DAP connector is electrically connected with the 10-pin DAP simulator in a first welding mode of two resistors;
the target pin of the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator in a second welding mode of two resistors.
Optionally, a TMS pin is selected for the test mode of the first DAP connector to be electrically connected with the main control chip;
the test clock input signal TCK pin of the first DAP connector is electrically connected with the main control chip;
and a test data output TDO pin of the first DAP connector is electrically connected with the main control chip.
Optionally, a TMS pin is electrically connected to the main control chip and is electrically connected to the power supply through a first pull-up resistor;
the test clock input signal TCK pin of the first DAP connector is electrically connected with the main control chip and grounded through a pull-down resistor;
the test data output TDO pin of the first DAP connector is electrically connected with the main control chip and is electrically connected with a power supply through a second pull-up resistor, and data is output from the DAP connector through the test data output pin TDO.
Optionally, the target pin of the first DAP connector is electrically connected to the 10-pin DAP emulator through a first welding manner of two resistors, including:
and when the 9 pins of the first DAP connector are grounded through the first welding resistor and the second welding resistor is not welded, the first DAP connector is electrically connected with the 10-pin DAP simulator.
Optionally, the target pin of the first DAP connector is electrically connected to the 20-pin joint test workgroup JTAG emulator through a second soldering manner of two resistors, including:
and the 9 pins of the first DAP connector are electrically connected with the main control chip through the second welding resistor, and when the first welding resistor is not welded, the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator through the adapter plate, and the data is input to the 9 pins through the test data input TDI pin of the 20-pin joint test working group JTAG simulator.
Optionally, the VREF pin of the first DAP connector is pulled up to a power source;
the power supply is grounded through a filter capacitor;
the nReset pin and the nTRST pin of the first DAP connector are both reset signal pins.
Optionally, the adapter plate is provided with: a 10-pin second debug access port DAP connector and a 20-pin joint test workgroup JTAG connector, wherein the second DAP connector is connected with a same-name signal pin of the 20-pin JTAG connector.
Optionally, the test mode selection TMS pin of the second DAP connector is connected to the test mode selection TMS pin of the 20-pin JTAG connector;
the test clock input signal TCK pin of the second DAP connector is connected to the test clock input signal TCK pin of the 20pin JTAG connector.
Optionally, the test data input TDI pin of the second DAP connector is connected to the test data input TDI pin of the 20pin JTAG connector;
the test data output TDO pin of the second DAP connector is connected with the test data output TDO pin of the 20-pin JTAG connector.
Optionally, an nTRST pin of the second DAP connector is connected to a TRST pin of the 20-pin JTAG connector;
the reference voltage Vref pin of the second DAP connector is connected with the reference voltage Vtref pin and the power supply pin of the 20-pin JTAG connector;
the RESET pin of the second DAP connector is connected with the RESET pin of the 20-pin JTAG connector;
the ground pins GND of the second DAP connector are respectively connected to the ground pins GND of the 20-pin JTAG connector.
The embodiment of the invention also provides a test system, which comprises: 10-pin DAP emulator, 20-pin joint test workgroup JTAG emulator, and control board as described above.
The scheme of the invention at least comprises the following beneficial effects:
according to the scheme, the DAP connector is used for a first debugging access port; a master control chip electrically connected with pins of the first DAP connector; the target pin of the first DAP connector is electrically connected with the 10-pin DAP simulator in a first welding mode of two resistors; the target pin of the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator in a second welding mode of two resistors; the compatible design of the control board on the DAP and JTAG simulators is realized, the test requirement of project development is met, and the development period and the cost of one control board are reduced; by adopting compatible designs of the two simulators, different simulators can be adapted only by adding an adapter plate of one connector in a control board circuit, so that the convenience of design is improved, and the flexibility of testing is improved.
Drawings
FIG. 1 is a schematic diagram of a control board provided by an embodiment of the present invention;
FIG. 2 is a diagram of JTAG standard pins provided by an embodiment of the present invention;
FIG. 3 is a DAP pin diagram provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of an interposer provided by an embodiment of the present invention;
fig. 5 is a schematic diagram of a control board compatibility scheme provided by an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As shown in fig. 1, an embodiment of the present invention proposes a control board including:
a first debug access port DAP connector;
the main control chip is electrically connected with the pins of the first DAP connector, and can be a micro control unit MCU;
the target pin of the first DAP connector is electrically connected with the 10-pin DAP simulator in a first welding mode of two resistors;
the target pin of the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator in a second welding mode of two resistors.
In the embodiment, a first DAP (Debug Access Port) connector scheme is adopted when the PCB (Printed Circuit Board ) of the control board is arranged, and the pins are 10 pins, so that the arrangement area is greatly reduced; meanwhile, through different welding modes of the first DAP connector and the two resistors, compatible testing of the DAP simulator and the JTAG simulator is achieved.
In an optional embodiment of the present invention, a TMS pin is selected for the test mode of the first DAP connector to be electrically connected to the main control chip;
the test clock input signal TCK pin of the first DAP connector is electrically connected with the main control chip;
and a test data output TDO pin of the first DAP connector is electrically connected with the main control chip.
The TMS pin is electrically connected with the main control chip through a first pull-up resistor R1;
the test clock input signal TCK pin of the first DAP connector is electrically connected with the main control chip and is grounded through a pull-down resistor R5;
the test data output TDO pin of the first DAP connector is electrically connected with the main control chip and is electrically connected with a power supply through a second pull-up resistor R4, and data is output from the DAP connector through the test data output pin TDO.
The target pin of the first DAP connector is electrically connected with the 10-pin DAP emulator through a first welding mode of two resistors, and the target pin comprises:
and when the 9 pins of the first DAP connector are grounded through the first welding resistor R9 and the second welding resistor R7 is not welded, the first DAP connector is electrically connected with the 10-pin DAP simulator.
The target pin of the first DAP connector is electrically connected with the 20-pin joint test workgroup JTAG emulator in a second welding mode of two resistors, and comprises:
and the 9 pins of the first DAP connector are electrically connected with the main control chip through the second welding resistor R7, and when the first welding resistor R9 is not welded, the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator through the adapter plate, and data is input to the 9 pins through the test data input TDI pin of the 20-pin joint test working group JTAG simulator.
In this embodiment of the invention, the first DAP connector has 10 pins, respectively:
1 pin VREF: the power supply input is connected to a VDD power supply through a pull-up resistor R8, and C1 is a filter capacitor of the power supply;
2 foot TMS: the test mode selection signal is used for selecting a test mode from the first pull-up resistor R1 to the MCU chip;
3 foot ground connection;
4-pin TCK: the test clock signal is a test clock input signal through a pull-down resistor R5 to the MCU chip;
6-pin TDO: testing a data output signal, namely outputting data from the DAP connector through a TDO pin by passing through a second pull-up resistor R4 to the MCU;
the 7 pin is grounded;
the 8-pin nTRST and the 10-pin nReset are reset signals;
the 9 PIN can be TDI or GND, and compatible design of DAP and JTAG is achieved through selection of resistors, specifically, compatible design of a control board to a DAP 10PIN simulator and a JTAG20 PIN simulator is achieved through selection of welding modes of two resistors, namely R7 and R9; wherein TDI: for testing data input, data is input to the interface through the TDI pin;
the welding modes of the two resistors R7 and R9 comprise:
the first welding mode comprises the following steps: welding an R9 resistor, wherein the R7 resistor is not welded; at the moment, the 9 PIN is connected to the GND PIN through the R9 resistor, and the scheme can be directly adapted to the 10PIN DAP simulator;
the second welding mode is as follows: and welding an R7 resistor, wherein the R9 resistor is not welded, the 9 pins are connected to the MCU through the R7 resistor, and data is input to the 9 pins through a test data input TDI pin of the 20-pin joint test working group JTAG simulator. The scheme can be externally connected with an adapter plate to adapt to the JTAG simulator. Thereby realizing compatible testing of the DAP simulator and the JTAG simulator.
It should be noted that the interface of the DAP emulator is the same as the interface of the first DAP connector, and all conform to the DAP standard interface.
As shown in FIG. 2, in an alternative embodiment of the present invention, the 20-pin joint test working group JTAG emulator J1 has 20 pins, respectively:
1-pin Vtref: the interface signal level reference voltage is generally directly connected with a power supply;
2 pin VDD: a power supply;
3 pins TRST (Test Reset Input), input pins for test reset, low level active;
the 4 pin is grounded;
5-pin TDI (Test Data Input): for testing data input, data is input to the JTAG interface through the TDI pin;
the 6 feet are grounded;
7-pin TMS (Test Mode Selector ): for setting the JTAG interface in a specific test mode;
the 8 pin is grounded;
9-pin TCK (Test Clock): input for a test clock;
the 10 feet are grounded; 11 NC, unconnected;
the 12 feet are grounded;
13-pin TDO (Test Data Output): for testing data output, data is output from the JTAG interface through a TDO pin;
the 14 feet are grounded;
15 foot RESET: a target system reset signal;
the 16 feet are grounded;
17 and 19 feet NC: unconnected;
the 18 feet are grounded;
the 20 feet are grounded;
GND: a ground pin.
As shown in FIG. 3, the interface pins of the DAP simulator are schematic, and can be externally connected with a debugger such as JTAG; pins of the DAP simulator are respectively:
2 foot TMS: the interface is set in a specific test mode and is the same as a 7-pin TMS pin of JTAG;
4-pin TCK: for test clock input, the same as the 9-pin TCK of JTAG;
6-pin TDO: for testing data output, the data is output from the interface through a TDO pin, and is the same as the 13-pin TDO of JTAG;
8 pins nTRST, which is to test reset, input pins, active low, the same as 3 pins TRST of JTAG;
10pin nRESET is the target system reset signal which is the same as 15 pins of JTAG;
1 foot Vref: the target board reference voltage is the same as the 1-pin Vtref and 2-pin VDD power supplies of JTAG;
the 9 pins can be TDI or GND, and the compatible design of DAP and JTAG is realized through the selection and matching of resistors, and TDI: for testing data input, data is input to the interface through the TDI pin, which is the same as the 5-pin TDI of JTAG;
GND: the ground pin is the same as the GND pin of JTAG.
In an alternative embodiment of the present invention, as shown in fig. 4, the adapter plate is provided with: a 10-pin second debug access port DAP connector and a 20-pin joint test workgroup JTAG connector, wherein the second DAP connector is connected with a same-name signal pin of the 20-pin JTAG connector.
Specifically, the test mode selection TMS pin of the second DAP connector is connected to the test mode selection TMS pin of the 20-pin JTAG connector;
the test clock input signal TCK pin of the second DAP connector is connected to the test clock input signal TCK pin of the 20pin JTAG connector.
The test data input TDI pin of the second DAP connector is connected with the test data input TDI pin of the 20-pin JTAG connector;
the test data output TDO pin of the second DAP connector is connected with the test data output TDO pin of the 20-pin JTAG connector.
The nTRST pin of the second DAP connector is connected with the TRST pin of the 20-pin JTAG connector;
the reference voltage Vref pin of the second DAP connector is connected with the reference voltage Vtref pin and the VDD power supply pin of the 20-pin JTAG connector;
the RESET pin of the second DAP connector is connected with the RESET pin of the 20-pin JTAG connector;
the ground pins GND of the second DAP connector are respectively connected to the ground pins GND of the 20-pin JTAG connector.
As shown in fig. 5, in order to adapt to the JTAG20 PIN emulator, an adapter board needs to be added between the emulator and the control board to perform conversion between the first DAP connector and the JTAG emulator, and a second DAP connector with 10PIN and a JTAG connector with 20PIN are respectively arranged on the adapter board, and signals between the two connectors are connected through PINs with the same name; the two connector pins are connected in a one-to-one correspondence manner, and no additional components and circuits are needed.
According to the embodiment of the invention, the high-density design scheme of the control board is realized by adding the adapter board of the DAP and the JTAG as the interface conversion for adapting the JTAG simulator to the first DAP connector of the control board, and the simulator scheme of the DAP and the JTAG can be flexibly adapted, so that the compatible application of the DAP and the JTAG simulator is realized, the development period and the cost of one control board are reduced, and the flexibility of the test is improved. Meanwhile, by using the DAP connector with small package for the control board and compatible design scheme for DAP pins, the layout density is improved, and the design flexibility is improved.
The embodiment of the invention also provides a test system, which comprises: the 10-pin DAP simulator, the 20-pin joint test working group JTAG simulator and the control board are all applicable to the embodiment, and the same technical effect can be achieved.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (11)
1. A control board, comprising:
a first debug access port DAP connector;
a main control chip electrically connected with the pins of the first DAP connector;
the target pin of the first DAP connector is electrically connected with the 10-pin DAP simulator in a first welding mode of two resistors;
the target pin of the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator in a second welding mode of two resistors.
2. The control board of claim 1, wherein,
the TMS pin is electrically connected with the main control chip in a test mode selection mode of the first DAP connector;
the test clock input signal TCK pin of the first DAP connector is electrically connected with the main control chip;
and a test data output TDO pin of the first DAP connector is electrically connected with the main control chip.
3. The control board of claim 2, wherein,
the TMS pin is electrically connected with the main control chip through a first pull-up resistor (R1);
the test clock input signal TCK pin of the first DAP connector is electrically connected with the main control chip and is grounded through a pull-down resistor (R5);
the test data output TDO pin of the first DAP connector is electrically connected with the main control chip and is electrically connected with a power supply through a second pull-up resistor (R4), and data is output from the DAP connector through the test data output pin TDO.
4. The control board of claim 1, wherein the target pins of the first DAP connector are electrically connected to a 10-pin DAP emulator by a first solder of two resistors, comprising:
and when the 9 pins of the first DAP connector are grounded through a first welding resistor (R9) and the second welding resistor (R7) is not welded, the first DAP connector is electrically connected with the 10-pin DAP simulator.
5. The control board of claim 1, wherein the target pins of the first DAP connector are electrically connected to a 20-pin joint test workgroup JTAG emulator via a second solder of two resistors, comprising:
the 9 pins of the first DAP connector are electrically connected with the main control chip through a second welding resistor (R7), and when the first welding resistor (R9) is not welded, the first DAP connector is electrically connected with the 20-pin joint test working group JTAG simulator through the adapter plate, and data is input to the 9 pins through the test data input TDI pin of the 20-pin joint test working group JTAG simulator.
6. The control board of claim 1, wherein the VREF pin of the first DAP connector is pulled up to a power source;
the power supply is grounded through a filter capacitor (C1);
the nReset pin and the nTRST pin of the first DAP connector are both reset signal pins.
7. The control board according to claim 5, characterized in that the adapter plate is provided with: the 10-pin second debugging access port DAP connector and the 20-pin joint test working group JTAG connector are connected with the same name signal pins of the 20-pin JTAG connector.
8. The control board of claim 7, wherein,
the test mode selection TMS pin of the second DAP connector is connected with the test mode selection TMS pin of the 20-pin JTAG connector;
the test clock input signal TCK pin of the second DAP connector is connected to the test clock input signal TCK pin of the 20pin JTAG connector.
9. The control board of claim 7, wherein,
the test data input TDI pin of the second DAP connector is connected with the test data input TDI pin of the 20-pin JTAG connector;
the test data output TDO pin of the second DAP connector is connected with the test data output TDO pin of the 20-pin JTAG connector.
10. The control board of claim 7, wherein,
the nTRST pin of the second DAP connector is connected with the TRST pin of the 20-pin JTAG connector;
the reference voltage Vref pin of the second DAP connector is connected with the reference voltage Vtref pin and the power supply pin of the 20-pin JTAG connector;
the RESET pin of the second DAP connector is connected with the RESET pin of the 20-pin JTAG connector;
the ground pins GND of the second DAP connector are respectively connected to the ground pins GND of the 20-pin JTAG connector.
11. A test system, comprising: 10-pin DAP emulator, 20-pin joint test workgroup JTAG emulator, and control board according to any of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310226266.7A CN116149203A (en) | 2023-03-03 | 2023-03-03 | Control panel and test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310226266.7A CN116149203A (en) | 2023-03-03 | 2023-03-03 | Control panel and test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116149203A true CN116149203A (en) | 2023-05-23 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310226266.7A Pending CN116149203A (en) | 2023-03-03 | 2023-03-03 | Control panel and test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116149203A (en) |
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2023
- 2023-03-03 CN CN202310226266.7A patent/CN116149203A/en active Pending
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