CN116137535A - Parallel-to-serial conversion circuit and method for generating parallel-to-serial conversion clock signal - Google Patents
Parallel-to-serial conversion circuit and method for generating parallel-to-serial conversion clock signal Download PDFInfo
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- CN116137535A CN116137535A CN202310100042.1A CN202310100042A CN116137535A CN 116137535 A CN116137535 A CN 116137535A CN 202310100042 A CN202310100042 A CN 202310100042A CN 116137535 A CN116137535 A CN 116137535A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L3/00—Starting of generators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a parallel-serial conversion circuit and a generation method of a parallel-serial conversion clock signal, which belong to the technical field of data transmission, wherein the circuit comprises: a parallel-to-serial conversion sub-circuit, a parallel-to-serial conversion clock signal generation sub-circuit, and a reference clock generation sub-circuit; the reference clock generation sub-circuit is used for generating a reference clock signal and respectively transmitting the reference clock signal to the parallel-serial conversion sub-circuit and the parallel-serial conversion clock signal generation sub-circuit, and the parallel-serial conversion clock signal generation sub-circuit is used for generating a parallel-serial conversion clock signal based on the reference clock signal; the parallel-serial conversion sub-circuit comprises a data input unit and a parallel-serial conversion unit electrically connected with the data input unit; the data input unit is used for acquiring parallel data based on the reference clock signal, and the parallel-serial conversion unit is used for converting the parallel data into serial data based on the parallel-serial conversion clock signal, so that the area and the power consumption of the parallel-serial conversion circuit can be reduced on the basis of avoiding parallel-serial conversion errors, and the application range of the parallel-serial conversion circuit is improved.
Description
Technical Field
The present disclosure relates to the field of data transmission technologies, and in particular, to a parallel-to-serial conversion circuit and a method for generating a parallel-to-serial conversion clock signal.
Background
The modern data transmission rate is higher and higher, the timing margin reserved for the digital logic part is smaller and smaller, and the parallel-serial conversion technology can greatly improve IO speed on the basis of sacrificing the smaller timing margin of the digital logic so as to realize high-speed data transmission. However, the conventional parallel-to-serial conversion circuit mainly has two modes, that is, the first mode is composed of a PLL (Phase-Locked Loop), a multiplexer and a trigger, and multiple clocks with different phases are generated by the PLL to control the multiplexer to gate different input paths, so as to realize the parallel-to-serial conversion function; the second type is composed of PLL, FIFO (First In First Out, first-in first-out data buffer) and flip-flop, and the PLL generates multiple frequency multiplication clocks to control FIFO to read and write data, thereby realizing parallel-serial conversion function.
However, the above-mentioned conventional parallel-to-serial conversion circuit increases the area and power consumption of the entire parallel-to-serial conversion circuit due to the large area of the PLL, and further, the PLL is far from the multiplexer or FIFO in a general system-in-chip, which results in a shift of the phase after the multiple clock signals generated by the PLL are input to the multiplexer or FIFO, which causes a change of the duty ratio of data, and thus a parallel-to-serial conversion error. Meanwhile, no PLL is added to some low-cost and low-performance system-on-chip, which results in a reduction in the application range of the conventional parallel-serial conversion circuit.
Disclosure of Invention
The application provides a parallel-to-serial conversion circuit and a generation method of a parallel-to-serial conversion clock signal, so that the area and the power consumption of the parallel-to-serial conversion circuit are reduced on the basis of avoiding parallel-to-serial conversion errors, and the application range of the parallel-to-serial conversion circuit is improved.
The application provides a parallel-to-serial conversion circuit, the circuit includes:
a parallel-to-serial conversion sub-circuit, a parallel-to-serial conversion clock signal generation sub-circuit, and a reference clock generation sub-circuit;
the reference clock generation sub-circuit is used for generating a reference clock signal and respectively transmitting the reference clock signal to the parallel-serial conversion sub-circuit and the parallel-serial conversion clock signal generation sub-circuit, and the parallel-serial conversion clock signal generation sub-circuit is used for generating a parallel-serial conversion clock signal based on the reference clock signal;
the parallel-serial conversion sub-circuit comprises a data input unit and a parallel-serial conversion unit electrically connected with the data input unit; the data input unit is used for acquiring parallel data based on the reference clock signal, and the parallel-serial conversion unit is used for converting the parallel data into serial data based on the parallel-serial conversion clock signal.
According to the parallel-serial conversion circuit provided by the application, the parallel-serial conversion clock signal generation sub-circuit comprises a delay unit, a delay confirmation unit and a delay control unit;
the delay unit is used for carrying out delay operation on the reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal, the delay confirmation unit is used for confirming whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and the delay control unit is used for generating a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeding back the delay correction amount to the delay unit.
According to the parallel-to-serial conversion circuit provided by the application, the delay unit is further used for performing delay operation on the reference clock signal based on the delay correction amount to obtain an updated first parallel-to-serial conversion clock signal.
According to the parallel-to-serial conversion circuit provided by the application, the delay confirmation unit comprises a first signal generation subunit, a second signal generation subunit and a comparison unit;
the first signal generation subunit is configured to generate a first comparison signal based on the reference clock signal and the first parallel-serial conversion clock signal;
the second signal generation subunit is configured to generate a second comparison signal based on the reference clock signal and the first parallel-serial conversion clock signal;
the comparing unit is used for comparing the first comparison signal with the second comparison signal and generating a delay confirmation result.
According to the parallel-to-serial conversion circuit provided by the application, the first signal generation subunit comprises an exclusive-or gate and a first integration circuit, the exclusive-or gate is used for performing exclusive-or operation on the reference clock signal and the first parallel-to-serial conversion clock signal to obtain a second parallel-to-serial conversion clock signal, and the first integration circuit is used for performing integration operation on the second parallel-to-serial conversion clock signal to generate the first comparison signal;
the second signal generation subunit comprises an exclusive-or gate and a second integration circuit, the exclusive-or gate is used for performing exclusive-or operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a third parallel-serial conversion clock signal, and the second integration circuit is used for performing integration operation on the third parallel-serial conversion clock signal to generate the second comparison signal;
the comparing unit includes a comparator for comparing the first comparison signal and the second comparison signal and generating a delayed acknowledgement result.
According to the parallel-to-serial conversion circuit provided by the application, the parallel-to-serial conversion unit is a multiplexer or a FIFO memory;
in the case that the parallel-to-serial conversion unit is a multiplexer, the parallel-to-serial conversion clock signal is the first parallel-to-serial conversion clock signal; in the case that the parallel-to-serial conversion unit is a FIFO memory, the parallel-to-serial conversion clock signal is the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal.
According to the parallel-to-serial conversion circuit provided by the application, the delay control unit is further configured to generate a parallel-to-serial conversion clock signal output instruction based on a delay confirmation result of the delay confirmation unit, where the parallel-to-serial conversion clock signal output instruction is used for controlling the first parallel-to-serial conversion clock signal to be input into the multiplexer or controlling the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal to be input into the FIFO memory.
According to the parallel-serial conversion circuit provided by the application, the data input unit comprises a plurality of D flip-flops, and each D flip-flop is used for acquiring one path of data based on the reference clock signal.
The application also provides a method for generating the parallel-serial conversion clock signal, which is applied to the parallel-serial conversion clock signal generation sub-circuit of the parallel-serial conversion circuit, and comprises the following steps:
step S1, a delay unit delays a reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal;
step S2, a delay confirmation unit performs exclusive-nor operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a second parallel-serial conversion clock signal and a third parallel-serial conversion clock signal, performs integral operation on the second parallel-serial conversion clock signal and the third parallel-serial conversion clock signal to generate a first comparison signal and a second comparison signal, compares the first comparison signal with the second comparison signal to confirm whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and if so, jumps to execute step S4; if not, executing the step S3;
step S3, a delay control unit generates a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeds the delay correction amount back to the delay unit, and step S4 is executed;
step S4, the delay control unit generates a parallel-serial conversion clock signal output instruction to control the delay confirmation unit to input a target parallel-serial conversion clock signal to the parallel-serial conversion unit of the parallel-serial conversion sub-circuit.
According to the method for generating a parallel-to-serial conversion clock signal provided in the present application, the controlling the delay confirmation unit inputs a target parallel-to-serial conversion clock signal to a parallel-to-serial conversion unit of a parallel-to-serial conversion sub-circuit, specifically includes:
controlling the delay confirmation unit to input the first parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit under the condition that the parallel-to-serial conversion unit is a multiplexer;
and controlling the delay confirmation unit to input the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit under the condition that the parallel-to-serial conversion unit is a FIFO memory.
The parallel-serial conversion circuit and the generation method of the parallel-serial conversion clock signal provided by the application comprise the following steps: a parallel-to-serial conversion sub-circuit, a parallel-to-serial conversion clock signal generation sub-circuit, and a reference clock generation sub-circuit; the reference clock generation sub-circuit is used for generating a reference clock signal and respectively transmitting the reference clock signal to the parallel-serial conversion sub-circuit and the parallel-serial conversion clock signal generation sub-circuit, and the parallel-serial conversion clock signal generation sub-circuit is used for generating a parallel-serial conversion clock signal based on the reference clock signal; the parallel-serial conversion sub-circuit comprises a data input unit and a parallel-serial conversion unit electrically connected with the data input unit; the data input unit is used for acquiring parallel data based on the reference clock signal, and the parallel-to-serial conversion unit is used for converting the parallel data into serial data based on the parallel-to-serial conversion clock signal, so that the area and the power consumption of the parallel-to-serial conversion circuit can be reduced on the basis of avoiding parallel-to-serial conversion errors, and the application range of the parallel-to-serial conversion circuit is improved.
Drawings
For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a parallel-serial conversion circuit provided in the present application;
fig. 2 is a schematic structural diagram of a parallel-serial conversion clock signal generating sub-circuit provided in the present application;
fig. 3 is a schematic structural diagram of a delay confirmation unit provided in the present application;
FIG. 4 is a schematic waveform diagram of a clock signal provided herein;
FIG. 5 is a schematic diagram of a parallel-to-serial conversion process provided in the present application;
FIG. 6 is a second schematic diagram of parallel-to-serial conversion process provided in the present application;
fig. 7 is a schematic flow chart of a parallel-serial conversion method provided in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 1 is a schematic structural diagram of a parallel-serial conversion circuit provided in the present application, as shown in fig. 1, where the circuit includes:
a parallel-to-serial conversion sub-circuit, a parallel-to-serial conversion clock signal generation sub-circuit, and a reference clock generation sub-circuit;
the reference clock generation sub-circuit is used for generating a reference clock signal and respectively transmitting the reference clock signal to the parallel-serial conversion sub-circuit and the parallel-serial conversion clock signal generation sub-circuit, and the parallel-serial conversion clock signal generation sub-circuit is used for generating a parallel-serial conversion clock signal based on the reference clock signal;
the parallel-serial conversion sub-circuit comprises a data input unit and a parallel-serial conversion unit electrically connected with the data input unit; the data input unit is used for acquiring parallel data based on the reference clock signal, and the parallel-serial conversion unit is used for converting the parallel data into serial data based on the parallel-serial conversion clock signal.
Specifically, unlike a conventional parallel-to-serial conversion circuit that uses a PLL to generate a clock signal to control parallel-to-serial conversion, the embodiment of the present application generates a parallel-to-serial conversion clock signal by a parallel-to-serial conversion clock signal generation sub-circuit based on a reference clock signal generated by a reference clock generation sub-circuit. The reference clock generating sub-circuit may be an internal clock generating circuit of a system-in-chip or an external clock generating circuit, which is not particularly limited in the implementation of the present application, and the frequency of the reference clock signal may be set according to actual needs, which is not particularly limited in the embodiment of the present application. Based on this, the parallel-serial conversion clock signal generation subcircuit of the embodiment of the application can ensure the accuracy and stability of the phase of the parallel-serial conversion clock signal, avoid parallel-serial conversion errors, and simultaneously can reduce the area and power consumption of the parallel-serial conversion circuit and improve the application range of the parallel-serial conversion circuit because no PLL is adopted in the parallel-serial conversion circuit. Fig. 2 is a schematic structural diagram of a parallel-serial conversion clock signal generation sub-circuit provided in the present application, and as shown in fig. 2, the parallel-serial conversion clock signal generation sub-circuit includes a delay unit, a delay confirmation unit, and a delay control unit;
the delay unit is used for carrying out delay operation on the reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal, the delay confirmation unit is used for confirming whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and the delay control unit is used for generating a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeding back the delay correction amount to the delay unit.
The preset delay amount is preferably a 90-degree phase difference, and of course, the preset delay amount may also be adjusted according to actual needs, which is not specifically limited in the embodiment of the present application. In theory, the first parallel-to-serial conversion clock signal having a phase difference of 90 degrees with the reference clock signal may be obtained after being processed by the delay unit, but the phase difference between the first parallel-to-serial conversion clock signal and the reference clock signal is not necessarily 90 degrees due to the influence of PVT (i.e., process, voltage and temperature), and accordingly, the embodiment of the present application is further based on the delay confirmation unit for confirming whether the actual delay amount of the first parallel-to-serial conversion clock signal is equal to the preset delay amount, and in case that the actual delay amount is not equal to the preset delay amount, the delay control unit generates a delay correction amount based on the delay confirmation result of the delay confirmation unit and feeds back to the delay unit, and correspondingly, the delay unit is further configured to perform a delay operation on the reference clock signal based on the delay correction amount to obtain the updated first parallel-to-serial conversion clock signal. Based on this, the accuracy and stability of the parallel-serial conversion clock signal phase can be ensured.
Fig. 3 is a schematic structural diagram of a delay confirmation unit provided in the present application, and as shown in fig. 3, the delay confirmation unit includes a first signal generation subunit, a second signal generation subunit, and a comparison unit;
the first signal generation subunit is configured to generate a first comparison signal based on the reference clock signal and the first parallel-serial conversion clock signal;
the second signal generation subunit is configured to generate a second comparison signal based on the reference clock signal and the first parallel-serial conversion clock signal;
the comparing unit is used for comparing the first comparison signal with the second comparison signal and generating a delay confirmation result.
More specifically, the first signal generating subunit includes an exclusive-or gate and a first integrating circuit, where the exclusive-or gate is configured to perform an exclusive-or operation on the reference clock signal and the first parallel-to-serial conversion clock signal to obtain a second parallel-to-serial conversion clock signal, and the first integrating circuit is configured to perform an integrating operation on the second parallel-to-serial conversion clock signal to generate the first comparison signal;
the second signal generation subunit comprises an exclusive-or gate and a second integration circuit, the exclusive-or gate is used for performing exclusive-or operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a third parallel-serial conversion clock signal, and the second integration circuit is used for performing integration operation on the third parallel-serial conversion clock signal to generate the second comparison signal;
the comparing unit includes a comparator for comparing the first comparison signal and the second comparison signal and generating a delayed acknowledgement result.
Fig. 4 is a schematic waveform diagram of the clock signal provided in the present application, as shown in fig. 4, if the phase difference between the first parallel-to-serial conversion clock signal and the reference clock signal is 90 degrees, the third parallel-to-serial conversion clock signal is a frequency multiplication clock signal of the reference clock, and the second parallel-to-serial conversion clock signal is an inverted (i.e. opposite phase) signal of the third parallel-to-serial conversion clock signal, so when the actual delay amount of the first parallel-to-serial conversion clock signal is equal to the preset delay amount, the first comparison signal and the second comparison signal should be equal, and conversely, if the actual delay amount of the first parallel-to-serial conversion clock signal is not equal to the preset delay amount, the first comparison signal and the second comparison signal are also not equal. Based on this, the delay control unit may generate an accurate delay correction amount based on the delay confirmation result of the delay confirmation unit, so that the delay unit performs a secondary delay operation on the reference clock signal to obtain an updated first parallel-serial conversion clock signal.
Meanwhile, based on the first to third parallel-to-serial conversion clock signals, the embodiment of the present application may be compatible with a scheme of implementing parallel-to-serial conversion through a multiplexer and a FIFO memory, that is, the parallel-to-serial conversion unit may be a multiplexer or a FIFO memory, and specifically, in the case that the parallel-to-serial conversion unit is a multiplexer, the parallel-to-serial conversion clock signal is the first parallel-to-serial conversion clock signal; in the case that the parallel-to-serial conversion unit is a FIFO memory, the parallel-to-serial conversion clock signal is the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal. Correspondingly, the delay control unit is further configured to generate a parallel-to-serial conversion clock signal output instruction based on a delay confirmation result of the delay confirmation unit, where the parallel-to-serial conversion clock signal output instruction is used to control the first parallel-to-serial conversion clock signal input multiplexer or to control the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal input FIFO memory. The data input unit comprises a plurality of D triggers, and each D trigger is used for acquiring one path of data based on the reference clock signal. Based on this, accurate parallel-to-serial conversion can be achieved regardless of whether the parallel-to-serial conversion unit is a multiplexer or a FIFO memory.
Specifically, fig. 5 is one of the schematic diagrams of the parallel-to-serial conversion process provided in the present application, as shown in fig. 5, where in the case where the parallel-to-serial conversion unit is a multiplexer, the reference clock signal is used to control a plurality of D flip-flops (clock signal rising edge triggering) to obtain parallel data, and the first parallel-to-serial conversion clock signal and the reference clock signal together form a gating control signal of the multiplexer, so as to implement parallel-to-serial conversion. Fig. 6 is a second schematic diagram of a parallel-to-serial conversion process provided in the present application, as shown in fig. 6, where the parallel-to-serial conversion unit is a FIFO memory, the reference clock signal is used to control the plurality of D flip-flops to obtain parallel data, and the reference clock signal and one of the second parallel-to-serial conversion clock signal and the third parallel-to-serial conversion clock signal together form a write operation control signal and a read operation control signal (a rising edge of the clock signal triggers a write operation or a read operation) of the FIFO memory, so as to implement parallel-to-serial conversion. It will be appreciated that D0-D3 in FIGS. 5 and 6 represent multiple paths of parallel data.
It may be further understood that the scheme of the foregoing embodiment is described in terms of a parallel-to-serial conversion process of four paths of parallel data, and in an actual application process, parallel-to-serial conversion of arbitrary power-of-2 paths of parallel data may be implemented by cascading parallel-to-serial conversion clock signal generating sub-circuits, and specific implementation processes of the scheme may refer to the foregoing embodiment, which is not described herein.
The circuit provided by the embodiment of the application comprises: a parallel-to-serial conversion sub-circuit, a parallel-to-serial conversion clock signal generation sub-circuit, and a reference clock generation sub-circuit; the reference clock generation sub-circuit is used for generating a reference clock signal and respectively transmitting the reference clock signal to the parallel-serial conversion sub-circuit and the parallel-serial conversion clock signal generation sub-circuit, and the parallel-serial conversion clock signal generation sub-circuit is used for generating a parallel-serial conversion clock signal based on the reference clock signal; the parallel-serial conversion sub-circuit comprises a data input unit and a parallel-serial conversion unit electrically connected with the data input unit; the data input unit is used for acquiring parallel data based on the reference clock signal, and the parallel-to-serial conversion unit is used for converting the parallel data into serial data based on the parallel-to-serial conversion clock signal, so that the area and the power consumption of the parallel-to-serial conversion circuit can be reduced on the basis of avoiding parallel-to-serial conversion errors, and the application range of the parallel-to-serial conversion circuit is improved.
Based on any of the foregoing embodiments, fig. 7 is a flow chart of a parallel-to-serial conversion method provided in the present application, where the method is applied to a parallel-to-serial conversion clock signal generating sub-circuit of the parallel-to-serial conversion circuit described in the foregoing embodiments, as shown in fig. 7, and the method includes:
step S1, a delay unit delays a reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal;
step S2, a delay confirmation unit performs exclusive-nor operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a second parallel-serial conversion clock signal and a third parallel-serial conversion clock signal, performs integral operation on the second parallel-serial conversion clock signal and the third parallel-serial conversion clock signal to generate a first comparison signal and a second comparison signal, compares the first comparison signal with the second comparison signal to confirm whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and if so, jumps to execute step S4; if not, executing the step S3;
step S3, a delay control unit generates a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeds the delay correction amount back to the delay unit, and step S4 is executed;
step S4, the delay control unit generates a parallel-serial conversion clock signal output instruction to control the delay confirmation unit to input a target parallel-serial conversion clock signal to the parallel-serial conversion unit of the parallel-serial conversion sub-circuit.
Specifically, the controlling the delay confirmation unit to input the target parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit of the parallel-to-serial conversion sub-circuit specifically includes:
controlling the delay confirmation unit to input the first parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit under the condition that the parallel-to-serial conversion unit is a multiplexer;
and controlling the delay confirmation unit to input the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit under the condition that the parallel-to-serial conversion unit is a FIFO memory.
It can be understood that the first parallel-to-serial conversion clock signal input to the multiplexer is the accurate first parallel-to-serial conversion clock signal corresponding to the actual delay amount equal to the preset delay amount, and the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal input to the FIFO memory is the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal generated based on the accurate first parallel-to-serial conversion clock signal. Based on the method, the accuracy of parallel-serial conversion signals can be ensured, and the accuracy of subsequent parallel-serial conversion is further ensured.
The specific implementation principle and effect of the present invention are described in detail in the foregoing embodiments, and are not described in detail herein.
Step S1, a delay unit delays a reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal; step S2, a delay confirmation unit performs exclusive-nor operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a second parallel-serial conversion clock signal and a third parallel-serial conversion clock signal, performs integral operation on the second parallel-serial conversion clock signal and the third parallel-serial conversion clock signal to generate a first comparison signal and a second comparison signal, compares the first comparison signal with the second comparison signal to confirm whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and if so, jumps to execute step S4; if not, executing the step S3; step S3, a delay control unit generates a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeds the delay correction amount back to the delay unit, and step S4 is executed; and S4, the delay control unit generates a parallel-to-serial conversion clock signal output instruction to control the delay confirmation unit to input a target parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit of the parallel-to-serial conversion sub-circuit, so that the phase difference between the parallel-to-serial conversion clock signal and the reference clock signal can be ensured to be constant, and the accuracy of subsequent parallel-to-serial conversion is further ensured.
In another aspect, the present application further provides a computer program product, where the computer program product includes a computer program, where the computer program can be stored on a non-transitory computer readable storage medium, where the computer program when executed by a processor can perform a method for generating a parallel-to-serial conversion clock signal provided by the above methods, where the method includes: step S1, a delay unit delays a reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal; step S2, a delay confirmation unit performs exclusive-nor operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a second parallel-serial conversion clock signal and a third parallel-serial conversion clock signal, performs integral operation on the second parallel-serial conversion clock signal and the third parallel-serial conversion clock signal to generate a first comparison signal and a second comparison signal, compares the first comparison signal with the second comparison signal to confirm whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and if so, jumps to execute step S4; if not, executing the step S3; step S3, a delay control unit generates a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeds the delay correction amount back to the delay unit, and step S4 is executed; step S4, the delay control unit generates a parallel-serial conversion clock signal output instruction to control the delay confirmation unit to input a target parallel-serial conversion clock signal to the parallel-serial conversion unit of the parallel-serial conversion sub-circuit.
In yet another aspect, the present application further provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method for generating a parallel to serial conversion clock signal provided by the above methods, the method comprising: step S1, a delay unit delays a reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal; step S2, a delay confirmation unit performs exclusive-nor operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a second parallel-serial conversion clock signal and a third parallel-serial conversion clock signal, performs integral operation on the second parallel-serial conversion clock signal and the third parallel-serial conversion clock signal to generate a first comparison signal and a second comparison signal, compares the first comparison signal with the second comparison signal to confirm whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and if so, jumps to execute step S4; if not, executing the step S3; step S3, a delay control unit generates a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeds the delay correction amount back to the delay unit, and step S4 is executed; step S4, the delay control unit generates a parallel-serial conversion clock signal output instruction to control the delay confirmation unit to input a target parallel-serial conversion clock signal to the parallel-serial conversion unit of the parallel-serial conversion sub-circuit.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a ROM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (10)
1. A parallel-to-serial conversion circuit, the circuit comprising:
a parallel-to-serial conversion sub-circuit, a parallel-to-serial conversion clock signal generation sub-circuit, and a reference clock generation sub-circuit;
the reference clock generation sub-circuit is used for generating a reference clock signal and respectively transmitting the reference clock signal to the parallel-serial conversion sub-circuit and the parallel-serial conversion clock signal generation sub-circuit, and the parallel-serial conversion clock signal generation sub-circuit is used for generating a parallel-serial conversion clock signal based on the reference clock signal;
the parallel-serial conversion sub-circuit comprises a data input unit and a parallel-serial conversion unit electrically connected with the data input unit; the data input unit is used for acquiring parallel data based on the reference clock signal, and the parallel-serial conversion unit is used for converting the parallel data into serial data based on the parallel-serial conversion clock signal.
2. The parallel-to-serial conversion circuit according to claim 1, wherein the parallel-to-serial conversion clock signal generation sub-circuit includes a delay unit, a delay confirmation unit, and a delay control unit;
the delay unit is used for carrying out delay operation on the reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal, the delay confirmation unit is used for confirming whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and the delay control unit is used for generating a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeding back the delay correction amount to the delay unit.
3. The parallel-to-serial conversion circuit according to claim 2, wherein the delay unit is further configured to perform a delay operation on the reference clock signal based on the delay correction amount to obtain the updated first parallel-to-serial conversion clock signal.
4. The parallel-to-serial conversion circuit according to claim 3, wherein the delay confirmation unit includes a first signal generation subunit, a second signal generation subunit, and a comparison unit;
the first signal generation subunit is configured to generate a first comparison signal based on the reference clock signal and the first parallel-serial conversion clock signal;
the second signal generation subunit is configured to generate a second comparison signal based on the reference clock signal and the first parallel-serial conversion clock signal;
the comparing unit is used for comparing the first comparison signal with the second comparison signal and generating a delay confirmation result.
5. The parallel-to-serial conversion circuit according to claim 4, wherein the first signal generating subunit comprises an exclusive nor gate for exclusive nor operating on the reference clock signal and the first parallel-to-serial conversion clock signal to obtain a second parallel-to-serial conversion clock signal, and a first integrating circuit for integrating the second parallel-to-serial conversion clock signal to generate the first comparison signal;
the second signal generation subunit comprises an exclusive-or gate and a second integration circuit, the exclusive-or gate is used for performing exclusive-or operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a third parallel-serial conversion clock signal, and the second integration circuit is used for performing integration operation on the third parallel-serial conversion clock signal to generate the second comparison signal;
the comparing unit includes a comparator for comparing the first comparison signal and the second comparison signal and generating a delayed acknowledgement result.
6. The parallel-to-serial conversion circuit according to claim 5, wherein the parallel-to-serial conversion unit is a multiplexer or a FIFO memory;
in the case that the parallel-to-serial conversion unit is a multiplexer, the parallel-to-serial conversion clock signal is the first parallel-to-serial conversion clock signal; in the case that the parallel-to-serial conversion unit is a FIFO memory, the parallel-to-serial conversion clock signal is the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal.
7. The parallel-to-serial conversion circuit according to claim 6, wherein the delay control unit is further configured to generate a parallel-to-serial conversion clock signal output instruction for controlling the first parallel-to-serial conversion clock signal input multiplexer or for controlling the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal input FIFO memory based on a delay confirmation result of the delay confirmation unit.
8. The parallel-to-serial conversion circuit according to claim 7, wherein the data input unit includes a plurality of D flip-flops, each D flip-flop being configured to acquire one path of data based on the reference clock signal.
9. A parallel-to-serial conversion clock signal generation method, characterized in that the method is applied to the parallel-to-serial conversion clock signal generation sub-circuit of the parallel-to-serial conversion circuit of claim 8, the method comprising:
step S1, a delay unit delays a reference clock signal based on a preset delay amount to obtain a first parallel-serial conversion clock signal;
step S2, a delay confirmation unit performs exclusive-nor operation on the reference clock signal and the first parallel-serial conversion clock signal to obtain a second parallel-serial conversion clock signal and a third parallel-serial conversion clock signal, performs integral operation on the second parallel-serial conversion clock signal and the third parallel-serial conversion clock signal to generate a first comparison signal and a second comparison signal, compares the first comparison signal with the second comparison signal to confirm whether the actual delay amount of the first parallel-serial conversion clock signal is equal to the preset delay amount, and if so, jumps to execute step S4; if not, executing the step S3;
step S3, a delay control unit generates a delay correction amount based on a delay confirmation result of the delay confirmation unit and feeds the delay correction amount back to the delay unit, and step S4 is executed;
step S4, the delay control unit generates a parallel-serial conversion clock signal output instruction to control the delay confirmation unit to input a target parallel-serial conversion clock signal to the parallel-serial conversion unit of the parallel-serial conversion sub-circuit.
10. The method for generating a parallel-to-serial conversion clock signal according to claim 9, wherein the controlling the delay confirmation unit inputs a target parallel-to-serial conversion clock signal to a parallel-to-serial conversion unit of a parallel-to-serial conversion sub-circuit, specifically comprises:
controlling the delay confirmation unit to input the first parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit under the condition that the parallel-to-serial conversion unit is a multiplexer;
and controlling the delay confirmation unit to input the second parallel-to-serial conversion clock signal or the third parallel-to-serial conversion clock signal to the parallel-to-serial conversion unit under the condition that the parallel-to-serial conversion unit is a FIFO memory.
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| CN116137535B (en) | 2023-08-29 |
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