CN116136970A

CN116136970A - Quantum error correction coding method and related equipment

Info

Publication number: CN116136970A
Application number: CN202111357521.9A
Authority: CN
Inventors: 赵勇杰
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2023-05-19
Anticipated expiration: 2041-11-16
Also published as: CN116136970B

Abstract

The invention discloses a quantum error correction decoding method and related equipment, wherein the method comprises the following steps: obtaining a stable sub-check line, wherein the stable sub-check line comprises data bits, auxiliary bits and accompanying bits, and quantum errors generated on the data bits come from a Gaussian error offset channel; operating the stable sub-check line to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit; upon determining that the data bit is erroneous based on the first output state, determining an erroneous data bit based on a noise parameter of the data bit and the second output state, and error correction decoding the erroneous data bit. By adopting the embodiment of the invention, when the quantum error generated on the data bit comes from the Gaussian error offset channel, the error correction decoding can be carried out on the data bit with error.

Description

Quantum error correction coding method and related equipment

Technical Field

The invention relates to the technical field of quantum computing, in particular to a quantum error correction coding method and related equipment.

Background

The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.

The quantum computing simulation is a simulation computation which simulates and follows the law of quantum mechanics by means of numerical computation and computer science, and is taken as a simulation program, and the high-speed computing capability of a computer is utilized to characterize the space-time evolution of the quantum state according to the basic law of quantum bits of the quantum mechanics. However, in practice, the qubits are very susceptible to noise, which greatly limits the development of quantum computation, so quantum error correction decoding is one of the basic requirements for realizing large-scale quantum computation. How to decode erroneous data bits is a technical problem to be solved when the quantum errors generated on the data bits come from gaussian error offset channels.

Disclosure of Invention

The embodiment of the invention provides a quantum error correction coding method and related equipment, which are used for error correction decoding of data bits with errors when quantum errors generated on the data bits come from a Gaussian error offset channel.

In a first aspect, an embodiment of the present invention provides a quantum error correction decoding method, including:

obtaining a stable sub-check line, wherein the stable sub-check line comprises data bits, auxiliary bits and accompanying bits, and quantum errors generated on the data bits come from a Gaussian error offset channel;

Operating the stable sub-check line to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit;

upon determining that the data bit is erroneous based on the first output state, determining an erroneous data bit based on a noise parameter of the data bit and the second output state, and error correction decoding the erroneous data bit.

Optionally, the determining the erroneous data bit based on the noise parameter of the data bit and the second output state includes:

determining a conditional error probability based on noise parameters of the data bits;

and determining an erroneous data bit based on the conditional error probability and the second output state.

Optionally, the determining the conditional error probability based on the noise parameter of the data bit includes:

determining a probability of an offset based on a noise parameter of the data bits;

a conditional error probability is determined based on the probability of the offset.

Optionally, the determining the erroneous data bits based on the conditional error probability and the second output state includes:

constructing a two-dimensional constrained lattice, wherein the vertexes of the two-dimensional constrained lattice are used for representing the accompanying bits;

Assigning a weight value to an edge in the two-dimensional constrained lattice based on the conditional error probability; determining a target vertex corresponding to the error-reported accompanying bit in the two-dimensional limited lattice based on the second output state;

pairing the target vertexes pairwise based on the edges endowed with the weight values to obtain a plurality of pairing modes;

determining a target pairing mode of the plurality of pairing modes, and determining error data bits based on the target pairing mode.

Optionally, the constructing a two-dimensional constrained lattice includes:

converting the bit arrangement structure of the color code into a pair-wise lattice;

and removing the preset color vertexes in the dual lattice and the edges and faces associated with the preset color vertexes to obtain the two-dimensional limited lattice.

Optionally, the method further comprises:

acquiring a unitary operator, a first error correction operator and a first CNOT gate corresponding to the Gaussian error offset channel;

and sequentially adding a first quantum logic gate corresponding to the unitary operator to the data bit, adding a second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit, and adding the first CNOT gate to the data bit and the accompanying bit to obtain a stable sub-checking line.

Optionally, the first error correction operator includes a second CNOT gate and a second error correction operator, and the adding the second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit includes:

the second CNOT gate is added to the data bits and the auxiliary bits, and the second error correction operator is added to the data bits.

Optionally, if the stable sub-checking circuit is configured to check whether the data bit is bit flipped, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both of a first number;

if the stable sub-checking circuit is used for checking whether the data bit is subjected to phase inversion, the data bit is a controlled bit, the accompanying bit is a control bit, and the data bit and the auxiliary bit are both in second quantity; the first number is not equal to the second number.

In a second aspect, an embodiment of the present invention provides a quantum error correction decoding apparatus, including:

the device comprises an acquisition unit, a correction unit and a correction unit, wherein the acquisition unit is used for acquiring a stable sub-verification line, the stable sub-verification line comprises data bits, auxiliary bits and accompanying bits, and quantum errors generated on the data bits come from a Gaussian error offset channel;

The operation unit is used for operating the stable sub-check line to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit;

and the determining unit is used for determining the error data bit based on the noise parameter of the data bit and the second output state and performing error correction decoding on the error data bit when the error data bit is determined based on the first output state.

Optionally, in the aspect of determining an erroneous data bit based on the noise parameter of the data bit and the second output state, the determining unit is specifically configured to:

Optionally, in the determining the conditional error probability based on the noise parameter of the data bit, the determining unit is specifically configured to:

Optionally, in the aspect of determining erroneous data bits based on the conditional error probability and the second output state, the determining unit is specifically configured to:

Optionally, in the aspect of constructing a two-dimensional constrained lattice, the determining unit is specifically configured to:

Optionally, the acquiring unit is further configured to:

Optionally, the first error correction operator includes a second CNOT gate and a second error correction operator, and the obtaining unit is specifically configured to:

Yet another embodiment of the present invention provides a computer-readable storage medium storing a computer program that is executed by a processor to implement the method of any of the above.

Yet another embodiment of the present invention provides an electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method as set forth in any of the preceding claims.

It can be seen that, in the embodiment of the present invention, when a quantum error generated on a data bit comes from a gaussian error offset channel, a stable sub-check line including the data bit, an auxiliary bit and an accompanying bit is obtained, and the stable sub-check line is operated to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit; when the data bit is determined to be in error based on the first output state, the data bit is determined to be in error based on the noise parameter of the data bit and the second output state, and the data bit in error is decoded in error correction, so that when the quantum error generated on the data bit is from a Gaussian error offset channel, the data bit in error is decoded in error correction.

These and other aspects of the invention will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a hardware block diagram of a computer terminal of a quantum error correction decoding method according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of a quantum error correction decoding method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a stable sub-check circuit for checking whether bit flipping occurs in the data bits according to an embodiment of the present invention;

FIG. 4 is a quantum circuit diagram of the first error correction operator effect corresponding to FIG. 3 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a stable sub-check circuit for checking whether phase inversion occurs in the data bits according to an embodiment of the present invention;

FIG. 6 is a quantum circuit diagram of the first error correction operator effect corresponding to FIG. 5 provided by an embodiment of the present invention;

Fig. 7 is a bit layout diagram of a 8,8,4 color code according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a dual lattice corresponding to the bit map of the color code shown in FIG. 7 according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a two-dimensional constrained lattice provided by an embodiment of the present invention;

FIG. 10 is a schematic diagram of a two-dimensional lattice containing erroneous data bits according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a quantum error correction decoding device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

The following will describe in detail.

The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The embodiment of the invention firstly provides a quantum error correction decoding method which can be applied to electronic equipment such as computer terminals, in particular to common computers, quantum computers and the like.

The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal of a quantum error correction decoding method according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing quantum-wire-based quantum error correction decoding methods, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum error correction decoding method in the embodiment of the present invention, and the processor 102 executes the software programs and modules stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.

It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written by a quantum language such as the qlunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.

In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.

Quantum circuits, which are one embodiment of quantum programs and weigh sub-logic circuits as well, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, and their composition includes qubits, circuits (timelines), and various quantum logic gates, and finally the result often needs to be read out through quantum measurement operations.

Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.

One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.

It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The general function of a quantum logic gate on a quantum state is to calculate through a unitary matrix multiplied by a matrix corresponding to the right vector of the quantum state.

In practice, the qubit is very susceptible to noise, which greatly limits the development of quantum computation, so quantum error correction decoding is one of the basic requirements for realizing large-scale quantum computation. How to decode erroneous data bits is a technical problem to be solved when the quantum errors generated on the data bits come from gaussian error offset channels.

Before introducing quantum error correction decoding, a repetition code of a classical error correction code is first introduced. For a channel transmitting bits, bit errors may occur with a certain probability when transmitting in the channel, such as flipping bit 1 to 0 or flipping bit 0 to 1. In order to improve the reliability of the transmitted information, when 1bit information is transmitted, the information to be transmitted is repeated for a plurality of times and transmitted (channel coding), as shown in the following table, and is repeated for 3 times and transmitted:

information to be transmitted	Bit column for channel
		0	000
1	111

Table 1 classical bit information encoding table

After receiving the information of the channel, the receiver must determine whether the received information is 0 or 1, and only needs to count the times of 0 and 1 in the received information at this time, and adopts a majority method to decode, i.e. the times are more so as not to determine what the information is. For example, if the received information is one of {000,001,010,100}, it is determined as 0; if the received information belongs to {011,101,110,111}, the information is judged to be 1. In this way, the probability of error in the information transmission process can be greatly reduced.

In quantum computation, the quantum state of the qubit is an superposition state, for example |ψ > =α|0> +β|1>, and errors that may occur include bit flip errors and phase flip errors. Bit flip errors are as classical, i.e. one qubit |0> becomes |1> after channel transmission, or one qubit |1> becomes |0> after channel transmission. The phase inversion error, i.e., the information transmitted by the transmitting end is |ψ > =α|0> +β|1>, and is changed to |ψ' > =α|0> - β|1> at the receiving end. Therefore, in quantum computing, it is also necessary to perform error correction decoding on the qubits.

Stabilizer code (StabilizerCode) is one of the commonly used types of quantum error correction codes. Before introducing the stabilizer code, a Pauli (Pauli) group is introduced, and one-dimensional Pauli group is as follows:

G ₁ :＝{±I，±iI，±X，±iX，±Y，±iY，±Z，±iZ}

consists of a unit operator and three Pauli operators. The n-th Pauli group is defined as n tensor products of Pauli:

pauli operators have many very good and intuitive properties, which also results in Pauli clusters having many very good properties. For example, any two elements are either easy or anti-easy, the eigenvalues of the elements are only two, X corresponds to a bit flip error, and Z corresponds to a phase flip error.

When the Hamiltonian of a quantum system is obtained, the limited requirement is to find symmetry, and a complete mechanical quantity set CSCO is obtained. In the stabilizer coding, n-k independent pairwise easy operators g are selected from the Pauli group of the n order ₁ ，…，g _n-k Since they are pairwise easy, they have common eigenstates, and these operators generate a switch group s=in the multiplicative sense<g ₁ ，…，g _n-k >Referred to as a stabilization stator. Taking +1 common eigenstates as code space

That is, all codes must be unchanged by the action of these operators, which is the source of the stabilizer name.

Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum error correction decoding method according to an embodiment of the present invention.

The embodiment provides a quantum error correction decoding method, which comprises the following steps:

step 201: obtaining a stable sub-check line, wherein the stable sub-check line comprises data bits, auxiliary bits and accompanying bits, and quantum errors generated on the data bits come from a Gaussian error offset channel;

wherein the data bits are quantum bits representing data, the auxiliary bits and the accompanying bits are used for assisting in correcting errors of the data bits, and the auxiliary bits and the accompanying bits can carry accompanying information of the errors.

Wherein the number of data bits, auxiliary bits and accompanying bits is determined based on the code distance of the error correction code employed. Error correction code [ n, k, d ] means that the k bits are encoded to obtain n codes, and the code distance d measures the number of bit differences between legal codes. As long as the number of bits in error is less than or equal to d, then the error can be detected and corrected when the number of bits in error is less than d/2.

Where a channel refers to a transmission medium or channel for signals, which serves to transfer a signal carrying information from its input to its output. The gaussian error offset channel refers to a weighted white gaussian noise (AWGN) channel. This noise is assumed to be constant in power spectral density (PDF) over the entire channel bandwidth and to have an amplitude that conforms to a gaussian probability distribution.

Further, the method further comprises:

Specifically, the first error correction operator includes a second CNOT gate and a second error correction operator, and in the aspect of adding the second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit, the method includes:

Wherein N is used for unitary operators corresponding to Gaussian error offset channels (Gaussian offset) on data bits ₁ In this case, since only the quantum error generated in the data bit is derived from the gaussian error offset channel, the unitary operator corresponding to the gaussian error offset channel is not present in the auxiliary bit and the accompanying bit, or the unitary operator corresponding to the gaussian error offset channel is present in the auxiliary bit and the accompanying bit is the unitary operator I.

The quantum error resulting from the gaussian error offset channel N can be expressed as follows:

wherein ρ is the density operator of the quantum state, P _σ (x) The offset x can be the position offset u, the momentum offset v, and sigma are noise parameters of the quantum bit,

the specific forms of the position and momentum operators are as follows:

N ₁ the determination may be based on the expression of N above, only the parameters in the expression need be converted to the relevant parameters of the data bits.

Wherein the first error correction operator is represented by EC and the second error correction operator by U _cor The specific form of the second error correction operator is shown as follows:

wherein p is _out And q _out A first output state for checking if a phase flip of the data bit occurs and a first output state for checking if a bit flip of the data bit occurs, respectively.

Wherein the number of unitary operators, first error correction operators, second error correction operators, first CNOT gates and second CNOT gates is the same as the number of data bits.

If the stable sub-checking circuit is used for checking whether the data bit is bit-flipped, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both of a first number;

The error correction code used in one embodiment of the present invention is an error correction code in which 8,8,4 color codes (color) are concatenated with GKP (gotterman-Kitaev-Preskill) codes, the code distance d is 6 (6 in the figure, which can be extended to any even number in practice), one accompanying bit is connected to four or eight data bits, and each data bit is connected to one auxiliary bit.

As shown in fig. 3, fig. 3 is a stable sub-verification circuit diagram for verifying whether bit flipping occurs in the data bits according to an embodiment of the present invention.

Is the quantum state of the data bit,/>

Quantum state of auxiliary bit corresponding to data bit, < ->

A quantum state of an accompanying bit corresponding to a data bit, wherein one accompanying bit is connected with four data bits, each data bit is connected with an auxiliary bit, i=1, 2, 3, 4. The quantum errors generated on the data bits come from the gaussian error offset channel, and therefore, each data bit is first covered by a unitary operator N corresponding to the gaussian error offset channel ₁ Then each data bit and its corresponding auxiliary bit are acted on by the first error correction operator EC, and finally each data bit and accompanying bit are acted on by the first CNOT gate, wherein the data bit is a control bit in the first CNOT gate, the accompanying bit is a controlled bit in the first CNOT gate, the accompanying bit is measured, and the second measurement state q of the accompanying bit can be obtained _m 。

Fig. 4 is a quantum circuit diagram of the first error correction operator effect corresponding to fig. 3 according to an embodiment of the present invention. The second CNOT gate acts on the data bit and the corresponding auxiliary bit, wherein the data bit is the control bit of the second CNOT gate, the corresponding auxiliary bit is the controlled bit of the second CNOT gate, and then the second error correction operator U _cor Acting on the data bits to measure the auxiliary bits to obtain a first measurement state q of the auxiliary bits _out 。

Fig. 5 is a schematic diagram of a stable sub-verification circuit for verifying whether phase inversion occurs in the data bits according to an embodiment of the present invention.

Is the quantum state of the data bit,/>

The quantum state of the auxiliary bit corresponding to the data bit,

a quantum state of a companion bit corresponding to the data bit, wherein one companion bit is connected to eight data bits, each data bit is connected to one auxiliary bit, i=1, 2, 3, 4, 5, 6, 7, 8. Fig. 6 is a quantum circuit diagram of the first error correction operator effect corresponding to fig. 5 according to an embodiment of the present invention. The quantum logic gates acting on the qubits are similar to those in fig. 3 and 4, wherein the data bits are the controlled bits in the first CNOT gate and the accompanying bits are the control bits in the first CNOT gate, and are not described in detail herein.

It should be noted that fig. 3 to 6 can also be used here

As the quantum state of the companion bit corresponding to the data bit, will +.>

The quantum states of the auxiliary bits corresponding to the data bits, and others are adaptively modified according to the nomenclature. Other circuits obtained by simple conversion naming according to the present embodiment are substantially the same as the present quantum circuit, and are within the scope of the present invention.

Step 202: operating the stable sub-check line to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit;

before the stabilizer checking circuit is operated, all the quantum bits are required to be prepared in an initial state and then operated. The initial states of the data bits are obtained based on whether the stable sub-check line is used for checking whether the data bits are bit flipped or phase flipped or not

Or->

Step 203: upon determining that the data bit is erroneous based on the first output state, determining an erroneous data bit based on a noise parameter of the data bit and the second output state, and error correction decoding the erroneous data bit.

Specifically, determining that the data bit is in error based on the first output state may be determining whether the first output state is a quantum state without error, if not, determining that the data bit is in error, where the quantum state without error may be determined according to a quantum circuit.

Specifically, in the aspect of determining the erroneous data bits based on the noise parameter of the data bits and the second output state, the method includes:

Wherein the noise parameter sigma of the data bit is determined by the quantum system, and different quantum systems can correspond to the noise parameters of different data bits.

More specifically, the determining the conditional error probability based on the noise parameter of the data bit includes:

Wherein the probability P of the offset x _σ (x) Following a gaussian distribution function, determining the probability of an offset based on the noise parameters of the data bits,

specifically, the determination can be based on the following formula:

The offset x may be a position offset u or a momentum offset v.

Wherein the conditional error probability may be a logical bubble

Conditional error probability +.>

Logic bubble sharp operator is also possible>

Conditional error probability +.>

If it is logic bubble sharp operator->

Conditional error probability +.>

The corresponding stable sub-check line is used for checking whether the data bit is turned over or not; if it is logic bubble sharp operator->

Conditional error probability +.>

Its corresponding stable sub-check line is used to check whether the data bit is phase flipped.

The conditional error probability is given below

For the conditional error probability +.>

Can be referred to in a specific manner>

The specific determination manner of (a) is determined, and a detailed description is omitted here.

Wherein, the liquid crystal display device comprises a liquid crystal display device,

the specific determination mode of (2) is as follows:

more specifically, in terms of said determining erroneous data bits based on said conditional error probability and said second output state, comprising:

Wherein assigning a weight value to an edge in the two-dimensional constrained lattice based on the conditional error probability comprises: the conditional error probability of each data bit is directly taken as the weight value of the corresponding edge in the two-dimensional limited lattice.

The target pairing mode is a pairing mode with the minimum weight calculated by the plurality of pairing modes; then pairing the target vertices two by two based on the edges given with the weight values to obtain multiple pairing modes, and determining the target pairing mode of the multiple pairing modes can be implemented by adopting a Minimum Weight Perfect Matching (MWPM) algorithm and a shortest path (Dijkstra) algorithm.

Further, in said building a two-dimensional constrained lattice, comprising:

The color code (color) may be a 8,8,4 color code, which is composed of red, green, and blue octagons. The 8,8,4 dual lattice parameter may be [72,4,6].

For example, as shown in fig. 7, fig. 7 is a bit layout diagram of a 8,8,4 color code according to an embodiment of the present invention. Solid black dots represent data bits, open squares, broken-line octagons, and solid-line octagons represent companion bits.

Converting the bit arrangement structure of the color code into the dual lattice, as shown in fig. 8, fig. 8 is a schematic diagram of the dual lattice corresponding to the bit arrangement diagram of the color code shown in fig. 7 according to the embodiment of the present invention. In fig. 8, the faces of the triangle are data bits and the vertices are companion bits.

The solid gray dots (blank dots) and their associated sides and faces in fig. 8 are removed to give the two-dimensional constrained lattice of fig. 9.

Assigning weight values to edges in the two-dimensional constrained lattice based on the conditional error probability, and determining target vertices corresponding to error-reported accompanying bits in the two-dimensional constrained lattice based on the second output state, namely enlarged blank dots and solid dots in fig. 10;

Pairing the target vertexes in pairs based on the edges given with the weight values to obtain a plurality of pairing modes, wherein a plurality of connection modes exist between any two points, namely the pairing modes, and the connection modes are not shown in fig. 10;

determining a target pairing mode in a plurality of pairing modes, namely a thickened black solid line in fig. 10; and determining erroneous data bits, i.e. gray triangles in fig. 10, based on the target pairing scheme.

Referring to fig. 11, fig. 11 is a schematic structural diagram of a quantum error correction decoding apparatus according to an embodiment of the present invention, corresponding to the method flow described in fig. 2, where the apparatus includes:

An obtaining unit 1101, configured to obtain a stable sub-verification line, where the stable sub-verification line includes a data bit, an auxiliary bit, and an accompanying bit, and a quantum error generated on the data bit is from a gaussian error offset channel;

an operation unit 1102, configured to operate the stable sub-check line to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit;

a determining unit 1103 is configured to determine, when determining that the data bit is erroneous based on the first output state, an erroneous data bit based on the noise parameter of the data bit and the second output state, and error correction-decode the erroneous data bit.

Optionally, in the aspect of determining an erroneous data bit based on the noise parameter of the data bit and the second output state, the determining unit 1103 is specifically configured to:

Optionally, in the aspect of determining the conditional error probability based on the noise parameter of the data bit, the determining unit 1103 is specifically configured to:

Optionally, in the aspect of determining an erroneous data bit based on the conditional error probability and the second output state, the determining unit 1103 is specifically configured to:

Optionally, in the aspect of building a two-dimensional limited lattice, the determining unit 1103 is specifically configured to:

Optionally, the obtaining unit 1101 is further configured to:

Optionally, the first error correction operator includes a second CNOT gate and a second error correction operator, where the second quantum logic gate corresponding to the first error correction operator is added to the data bit and the auxiliary bit, and the obtaining unit 1101 is specifically configured to:

Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:

Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

Specifically, the electronic device may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.

Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A quantum error correction decoding method, comprising:

2. The method of claim 1, wherein said determining erroneous data bits based on the noise parameters of said data bits and said second output state comprises:

3. The method of claim 2, wherein said determining a conditional error probability based on a noise parameter of the data bits comprises:

4. A method according to claim 2 or 3, wherein said determining erroneous data bits based on said conditional error probability and said second output state comprises:

5. The method of claim 4, wherein said constructing a two-dimensional constrained lattice comprises:

6. The method according to claim 1, wherein the method further comprises:

7. The method of claim 6, wherein the first error correction operator comprises a second CNOT gate and a second error correction operator, the adding a second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit comprising:

8. The method of claim 6 or 7, wherein if the stable sub-check line is used to check whether a bit flip occurs in the data bit, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both a first number;

9. A quantum error correction decoding apparatus, comprising:

10. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-8.

11. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program, which is executed by a processor to implement the method of any one of claims 1-8.