CN116136971B

CN116136971B - Quantum error correction decoding method and related equipment

Info

Publication number: CN116136971B
Application number: CN202111357531.2A
Authority: CN
Inventors: 赵勇杰
Original assignee: Benyuan Quantum Computing Technology Hefei Co ltd
Current assignee: Benyuan Quantum Computing Technology Hefei Co ltd
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2024-06-14
Anticipated expiration: 2041-11-16
Also published as: CN116136971A

Abstract

The invention discloses a quantum error correction decoding method and related equipment, wherein the method comprises the following steps: firstly, determining the quantum bit of the generated quantum error from the Gaussian error offset channel, then constructing a stable sub-checking line based on the quantum bit, finally determining the error data bit based on the operation result of the stable sub-checking line, and performing error correction decoding on the error data bit, thereby realizing error correction decoding on the error data bit when the quantum error generated on the quantum bit comes from the Gaussian error offset channel.

Description

Quantum error correction decoding method and related equipment

Technical Field

The invention relates to the technical field of quantum computing, in particular to a quantum error correction decoding method and related equipment.

Background

The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.

The quantum computing simulation is a simulation computation which simulates and follows the law of quantum mechanics by means of numerical computation and computer science, and is taken as a simulation program, and the high-speed computing capability of a computer is utilized to characterize the space-time evolution of the quantum state according to the basic law of quantum bits of the quantum mechanics. However, in practice, the qubits are very susceptible to noise, which greatly limits the development of quantum computation, so quantum error correction decoding is one of the basic requirements for realizing large-scale quantum computation. When the quantum error generated on the quantum bit comes from the Gaussian error offset channel, how to decode the error data bit error correction is a technical problem to be solved.

Disclosure of Invention

The embodiment of the invention provides a quantum error correction decoding method and related equipment, which are used for carrying out error correction decoding on data bits with errors when quantum errors generated on quantum bits come from a Gaussian error offset channel.

In a first aspect, an embodiment of the present invention provides a quantum error correction decoding method, including:

determining the quantum bits from the gaussian error offset channel for the generated quantum errors;

Constructing a stable sub-verification line based on the qubits;

and determining error data bits based on the operation result of the stable sub-check line, and performing error correction decoding on the error data bits.

Optionally, if the qubit is a data bit, the constructing a stable sub-verification line based on the qubit includes:

Acquiring the data bits, the auxiliary bits and the accompanying bits, and acquiring unitary operators, first error correction operators and first CNOT gates corresponding to the Gaussian error offset channels;

And sequentially adding a first quantum logic gate corresponding to the unitary operator to the data bit, adding a second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit, and adding the first CNOT gate to the data bit and the accompanying bit to obtain a stable sub-checking line.

Optionally, the first error correction operator includes a second CNOT gate and a second error correction operator, and the adding the second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit includes:

the second CNOT gate is added to the data bits and the auxiliary bits, and the second error correction operator is added to the data bits.

Optionally, the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit, and the determining the erroneous data bit based on the operation result of the stable sub-check line includes:

Determining a conditional error probability based on noise parameters of the data bits when determining that the data bits are erroneous based on the first output state;

and determining an erroneous data bit based on the conditional error probability and the second output state.

Optionally, the determining the conditional error probability based on the noise parameter of the data bit includes:

determining a probability of an offset based on a noise parameter of the data bits;

A conditional error probability is determined based on the probability of the offset.

Optionally, the determining the erroneous data bits based on the conditional error probability and the second output state includes:

Constructing a two-dimensional constrained lattice, wherein the vertexes of the two-dimensional constrained lattice are used for representing the accompanying bits;

Assigning a weight value to an edge in the two-dimensional constrained lattice based on the conditional error probability; determining a target vertex corresponding to the error-reported accompanying bit in the two-dimensional limited lattice based on the second output state;

pairing the target vertexes pairwise based on the edges endowed with the weight values to obtain a plurality of pairing modes;

determining a target pairing mode of the plurality of pairing modes, and determining error data bits based on the target pairing mode.

Optionally, the constructing a two-dimensional constrained lattice includes:

Converting the bit arrangement structure of the color code into a pair-wise lattice;

and removing the preset color vertexes in the dual lattice and the edges and faces associated with the preset color vertexes to obtain the two-dimensional limited lattice.

Optionally, if the qubit is a data bit, an auxiliary bit, and an accompanying bit, the constructing a stable sub-verification line based on the qubit includes:

Acquiring a first unitary operator and a second unitary operator corresponding to the Gaussian error offset channel, and acquiring a first error correction operator and a first CNOT gate;

And sequentially adding a first quantum logic gate corresponding to the first unitary operator to the data bit, adding a second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit, adding the first CNOT gate to the data bit and the accompanying bit, and adding a third quantum logic gate corresponding to the second unitary operator to the accompanying bit to obtain a stable sub-check line.

Optionally, the first error correction operator includes a second CNOT gate, a third unitary operator corresponding to the gaussian error offset channel, and a second error correction operator, and the adding the second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit includes:

The second CNOT gate is added to the data bit and the auxiliary bit, the fourth quantum logic gate corresponding to the third unitary operator is added to the auxiliary bit, and the second error correction operator is added to the data bit.

Optionally, the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit after each operation, and determining the erroneous data bit based on the operation result of the stable sub-check line includes:

Determining a first conditional error probability based on a first noise parameter of the data bit and a second noise parameter of the auxiliary bit, and determining the second conditional error probability based on the second noise parameter of the auxiliary bit and a third noise parameter of the accompanying bit when determining that the data bit is erroneous based on the first output state obtained after each run;

the erroneous data bits are determined based on the first conditional error probability, the second conditional error probability, and the second output state.

Optionally, the determining the first conditional error probability based on the first noise parameter of the data bit and the second noise parameter of the auxiliary bit, and the determining the second conditional error probability based on the second noise parameter of the auxiliary bit and the third noise parameter of the accompanying bit includes:

determining a first probability of an offset based on a first noise parameter of the data bit and a second noise parameter of the auxiliary bit, and determining a second probability of the offset based on the second noise parameter of the auxiliary bit and a third noise parameter of the companion bit;

a first conditional error probability is determined based on the first probability, and a second conditional error probability is determined based on the second probability.

Optionally, the determining the erroneous data bit based on the first conditional error probability, the second conditional error probability, and the second output state includes:

Constructing two-dimensional limited lattices, wherein the vertexes of the two-dimensional limited lattices are used for representing the accompanying bits, and each two-dimensional limited lattice correspondingly runs the stable sub-check line once;

determining target vertexes corresponding to error-reported accompanying bits in the two-dimensional limited lattices based on the second output states determined after each operation respectively;

Connecting the corresponding target vertexes in the two-dimensional limited lattices to obtain a three-dimensional limited lattice;

Assigning a weight value to an edge in the three-dimensional constrained lattice based on the first conditional error probability and the second conditional error probability;

Optionally, the constructing two-dimensional constrained lattices includes:

converting the bit arrangement structure of the two color codes into two dual lattices;

and respectively removing the preset color vertexes in the two dual lattices and the edges and the faces associated with the preset color vertexes to obtain two-dimensional limited lattices.

Optionally, if the stable sub-checking circuit is configured to check whether the data bit is bit flipped, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both of a first number; if the stable sub-checking circuit is used for checking whether the data bit is subjected to phase inversion, the data bit is a controlled bit, the accompanying bit is a control bit, and the data bit and the auxiliary bit are both in second quantity; the first number is not equal to the second number.

In a second aspect, an embodiment of the present invention provides a quantum error correction decoding apparatus, including:

a bit determination unit for determining a quantum bit from the gaussian error offset channel for the generated quantum error;

A line construction unit for constructing a stable sub-verification line based on the qubits;

And the error correction decoding unit is used for determining error data bits based on the operation result of the stable sub-check line and performing error correction decoding on the error data bits.

Optionally, if the qubit is a data bit, in the aspect of constructing a stable sub-verification line based on the qubit, the line construction unit is specifically configured to:

Optionally, the first error correction operator includes a second CNOT gate and a second error correction operator, and the line construction unit is specifically configured to:

Optionally, the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit, and the error correction decoding unit is specifically configured to:

Optionally, in the aspect of determining the conditional error probability based on the noise parameter of the data bit, the error correction decoding unit is specifically configured to:

Optionally, the determining an erroneous data bit based on the conditional error probability and the second output state, the error correction decoding unit is specifically configured to:

Optionally, in the aspect of constructing a two-dimensional limited lattice, the error correction decoding unit is specifically configured to:

Optionally, if the qubit is a data bit, an auxiliary bit, and an accompanying bit, the stable sub-verification line is constructed based on the qubit, and the line construction unit is configured to:

Optionally, the first error correction operator includes a second CNOT gate, a third unitary operator corresponding to the gaussian error offset channel, and a second error correction operator, and the line construction unit is configured to:

Optionally, the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit after each operation, and the error correction decoding unit is specifically configured to:

Optionally, in the determining the first conditional error probability based on the first noise parameter of the data bit and the second noise parameter of the auxiliary bit, and determining the second conditional error probability based on the second noise parameter of the auxiliary bit and the third noise parameter of the accompanying bit, the error correction decoding unit is specifically configured to:

Optionally, in the determining the erroneous data bits based on the first conditional error probability, the second conditional error probability and the second output state, the error correction decoding unit is specifically configured to:

Optionally, in the aspect of constructing two-dimensional limited lattices, the error correction decoding unit is specifically configured to:

Yet another embodiment of the present invention provides a computer-readable storage medium storing a computer program that is executed by a processor to implement the method of any of the above.

Yet another embodiment of the present invention provides an electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method as set forth in any of the preceding claims.

It can be seen that in the embodiment of the present invention, firstly, the generated quantum error is determined from the quantum bit of the gaussian error offset channel, then, a stable sub-check line is constructed based on the quantum bit, finally, the erroneous data bit is determined based on the operation result of the stable sub-check line, and the erroneous data bit is error-corrected and decoded, so that error-correction and decoding of the erroneous data bit are realized when the quantum error generated on the quantum bit is from the gaussian error offset channel.

These and other aspects of the invention will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a hardware block diagram of a computer terminal of a quantum error correction decoding method according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of a quantum error correction decoding method according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a stable sub-check circuit for checking whether bit flipping occurs in the data bits according to an embodiment of the present invention;

FIG. 4 is a quantum circuit diagram of the first error correction operator effect corresponding to FIG. 3 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a stable sub-check circuit for checking whether phase inversion occurs in the data bits according to an embodiment of the present invention;

FIG. 6 is a quantum circuit diagram of the first error correction operator effect corresponding to FIG. 5 provided by an embodiment of the present invention;

FIG. 7 is a diagram of a stable sub-check circuit for checking whether bit flipping occurs to the data bits according to an embodiment of the present invention;

FIG. 8 is a quantum circuit diagram of the first error correction operator effect corresponding to FIG. 7 provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of a stable sub-check circuit for checking whether phase inversion occurs in the data bits according to an embodiment of the present invention;

FIG. 10 is a quantum circuit diagram of the first error correction operator effect corresponding to FIG. 9 provided by an embodiment of the present invention;

FIG. 11 is a bit map of 8,8,4 color codes according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a dual lattice corresponding to the bit map of the color code shown in FIG. 11 according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a two-dimensional constrained lattice provided by an embodiment of the present invention;

FIG. 14 is a schematic diagram of a two-dimensional lattice of data bits containing errors according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a three-dimensional constrained lattice provided by an embodiment of the present invention;

fig. 16 is a schematic structural diagram of a quantum error correction decoding device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

The following will describe in detail.

The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The embodiment of the invention firstly provides a quantum error correction decoding method which can be applied to electronic equipment such as computer terminals, in particular to common computers, quantum computers and the like.

The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal of a quantum error correction decoding method according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing quantum-wire-based quantum error correction decoding methods, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum error correction decoding method in the embodiment of the present invention, and the processor 102 executes the software programs and modules stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.

It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written in a quantum language such as QRunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.

In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.

Quantum circuits, which are one embodiment of quantum programs and weigh sub-logic circuits as well, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, and their composition includes qubits, circuits (timelines), and various quantum logic gates, and finally the result often needs to be read out through quantum measurement operations.

Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.

One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.

It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The general function of a quantum logic gate on a quantum state is to calculate through a unitary matrix multiplied by a matrix corresponding to the right vector of the quantum state.

In practice, the qubit is very susceptible to noise, which greatly limits the development of quantum computation, so quantum error correction decoding is one of the basic requirements for realizing large-scale quantum computation. When the quantum error generated on the quantum bit comes from a Gaussian error offset channel, how to decode the error quantum bit is a technical problem to be solved.

Before introducing quantum error correction decoding, a repetition code of a classical error correction code is first introduced. For a channel transmitting bits, bit errors may occur with a certain probability when transmitting in the channel, such as flipping bit 1 to 0 or flipping bit 0 to 1. In order to improve the reliability of the transmitted information, when 1bit information is transmitted, the information to be transmitted is repeated for a plurality of times and transmitted (channel coding), as shown in the following table, and is repeated for 3 times and transmitted:

Information to be transmitted	Bit column for channel
		0	000
1	111

Table 1 classical bit information encoding table

After receiving the information of the channel, the receiver must determine whether the received information is 0 or 1, and only needs to count the times of 0 and 1 in the received information at this time, and adopts a majority method to decode, i.e. the times are more so as not to determine what the information is. For example, if the received information is one of {000,001,010,100}, it is determined as 0; if the received information belongs to {011,101,110,111}, the information is judged to be 1. In this way, the probability of error in the information transmission process can be greatly reduced.

In quantum computation, the quantum state of the qubit is an superposition state, for example |ψ > =α|0> +β|1>, and errors that may occur include bit flip errors and phase flip errors. Bit flip errors are as classical, i.e. one qubit |0> becomes |1> after channel transmission, or one qubit |1> becomes |0> after channel transmission. The phase inversion error, i.e., the information transmitted by the transmitting end is |ψ > =α|0> +β|1>, and is changed to |ψ' > =α|0> - β|1> at the receiving end. Therefore, in quantum computing, it is also necessary to perform error correction decoding on the qubits.

Stabilizer Code (stabilizator Code) is one of the commonly used types of quantum error correction codes. Before introducing the stabilizer code, a Pauli (Pauli) group is introduced, and one-dimensional Pauli group is as follows:

G₁：＝{±I，±iI，±X，±iX，±Y，±iY，±Z，±iZ}

Consists of a unit operator and three Pauli operators. The n-th Pauli group is defined as n tensor products of Pauli:

Pauli operators have many very good and intuitive properties, which also results in Pauli clusters having many very good properties. For example, any two elements are either easy or anti-easy, the eigenvalues of the elements are only two, X corresponds to a bit flip error, and Z corresponds to a phase flip error.

When the Hamiltonian of a quantum system is obtained, the limitation is to find symmetry, and a complete mechanical quantity set CSCO is obtained. In the stabilizer code, n-k independent pairwise easy operators g ₁,…,g_n-k are chosen from the n-order Pauli group, they have common eigenstates because of pairwise easy, and these operators generate a switching group S= < g ₁,…,g_n-k > in the multiplicative sense, called the stabilizer. Taking +1 common eigenstates as code spaceThat is, all codes must be unchanged by the action of these operators, which is the source of the stabilizer name.

Referring to fig. 2, fig. 2 is a schematic flow chart of a quantum error correction decoding method according to an embodiment of the present invention.

The embodiment provides a quantum error correction decoding method, which comprises the following steps:

step 201: determining the quantum bits from the gaussian error offset channel for the generated quantum errors;

The types of the quantum bits comprise data bits, auxiliary bits and auxiliary bits, the data bits are the quantum bits representing data, the auxiliary bits and the auxiliary bits are used for assisting in correcting errors of the data bits, and the auxiliary bits can carry accompanying information of errors.

Where a channel refers to a transmission medium or channel for signals, which serves to transfer a signal carrying information from its input to its output. The gaussian error offset channel refers to a weighted white gaussian noise (AWGN) channel. This noise is assumed to be constant in power spectral density (PDF) over the entire channel bandwidth and to have an amplitude that conforms to a gaussian probability distribution.

Step 202: constructing a stable sub-verification line based on the qubits;

In a first embodiment provided by the present invention:

the quantum bit is a data bit, and the constructing a stable sub-verification line based on the quantum bit includes:

Specifically, the first error correction operator includes a second CNOT gate and a second error correction operator, and the adding the second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit includes:

Wherein the number of data bits, auxiliary bits and accompanying bits is determined based on the code distance of the error correction code employed. Error correction code [ n, k, d ] means that the k bits are encoded to obtain n codes, and the code distance d measures the number of bit differences between legal codes. As long as the number of bits in error is less than or equal to d, then the error can be detected and corrected when the number of bits in error is less than d/2.

The unitary operator corresponding to the Gaussian error offset channel (Gaussian error SHIFT CHANNEL) on the data bit is denoted by N ₁, and since only the quantum error generated on the data bit is from the Gaussian error offset channel, the unitary operator corresponding to the Gaussian error offset channel does not exist on the auxiliary bit and the accompanying bit, or the unitary operator corresponding to the Gaussian error offset channel exists on the auxiliary bit and the accompanying bit is the unit operator I.

The quantum error resulting from the gaussian error offset channel N can be expressed as follows:

Wherein ρ is a density operator of quantum states, P _σ (x) is a gaussian distribution function of the offset x, which may be the position offset u, or the momentum offset v, σ is a noise parameter of the quantum bits, The specific forms of the position and momentum operators are as follows:

N ₁ may be determined based on the expression of N above, only the parameters in the equation need to be replaced with the relevant parameters of the data bits.

Wherein, the first error correction operator is represented by EC, the second error correction operator is represented by U _cor, and the specific form of the second error correction operator is as follows:

Wherein p _out and q _out are a first output state for checking if a phase flip of the data bit occurs and a first output state for checking if a bit flip of the data bit occurs, respectively.

Wherein the number of unitary operators, first error correction operators, second error correction operators, first CNOT gates and second CNOT gates is the same as the number of data bits.

If the stable sub-checking circuit is used for checking whether the data bit is bit-flipped, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both of a first number; if the stable sub-checking circuit is used for checking whether the data bit is subjected to phase inversion, the data bit is a controlled bit, the accompanying bit is a control bit, and the data bit and the auxiliary bit are both in second quantity; the first number is not equal to the second number.

The error correction code used in one embodiment of the present invention is an error correction code in which 8,8,4 color codes (color codes) are concatenated with GKP (gotterman-Kitaev-Preskill) codes, the code distance d is 6 (6 in the figure, which can be extended to any even number in practice), one accompanying bit is connected to four or eight data bits, and each data bit is connected to one auxiliary bit.

As shown in fig. 3, fig. 3 is a stable sub-verification circuit diagram for verifying whether bit flipping occurs in the data bits according to an embodiment of the present invention.Is the quantum state of the data bit,Quantum states of auxiliary bits corresponding to data bits,A quantum state of an accompanying bit corresponding to a data bit, wherein one accompanying bit is connected with four data bits, each data bit is connected with an auxiliary bit, i=1, 2,3, 4. The quantum errors generated on the data bits come from the gaussian error offset channel, so that each data bit is acted on by the unitary operator N ₁ corresponding to the gaussian error offset channel, then each data bit and the corresponding auxiliary bits are acted on by the first error correction operator EC, and finally each data bit and the accompanying bits are acted on by the first CNOT gate, wherein the data bits are control bits in the first CNOT gate, the accompanying bits are controlled bits in the first CNOT gate, and the accompanying bits are measured, so that the second measurement state q _m of the accompanying bits can be obtained.

Fig. 4 is a quantum circuit diagram of the first error correction operator effect corresponding to fig. 3 according to an embodiment of the present invention. The second CNOT gate acts on the data bit and the corresponding auxiliary bit, wherein the data bit is the control bit of the second CNOT gate, the corresponding auxiliary bit is the controlled bit of the second CNOT gate, then the second error correction operator U _cor acts on the data bit, and the auxiliary bit is measured, so that the first measurement state q _out of the auxiliary bit can be obtained.

Fig. 5 is a schematic diagram of a stable sub-verification circuit for verifying whether phase inversion occurs in the data bits according to an embodiment of the present invention.Is the quantum state of the data bit,The quantum state of the auxiliary bit corresponding to the data bit,A quantum state of a companion bit corresponding to the data bit, wherein one companion bit is connected to eight data bits, each data bit is connected to one auxiliary bit, i=1, 2,3, 4,5, 6, 7, 8. Fig. 6 is a quantum circuit diagram of the first error correction operator effect corresponding to fig. 5 according to an embodiment of the present invention. The quantum logic gates acting on the qubits are similar to those in fig. 3 and 4, wherein the data bits are the controlled bits in the first CNOT gate and the accompanying bits are the control bits in the first CNOT gate, and are not described in detail herein.

It should be noted that fig. 3 to 6 can also be used hereThe quantum state of the companion bit corresponding to the data bit willThe quantum states of the auxiliary bits corresponding to the data bits, and others are adaptively modified according to the nomenclature. Other circuits obtained by simple conversion naming according to the present embodiment are substantially the same as the present quantum circuit, and are within the scope of the present invention. /(I)

In a second embodiment provided by the present invention:

the quantum bit is a data bit, an auxiliary bit and an accompanying bit, and the constructing a stable sub-check line based on the quantum bit comprises:

Specifically, the first error correction operator includes a second CNOT gate, a third unitary operator corresponding to the gaussian error offset channel, and a second error correction operator, and the adding the second quantum logic gate corresponding to the first error correction operator to the data bit and the auxiliary bit includes:

Wherein, the first unitary operator corresponding to the Gaussian error offset channel on the data bit is represented by N ₁, the second unitary operator corresponding to the Gaussian error offset channel on the accompanying bit is represented by N _m, and the third unitary operator corresponding to the Gaussian error offset channel on the auxiliary bit is represented by N ₂. The first error correction operator is denoted by EC and the second error correction operator is denoted by U _cor.

The quantum error from the gaussian error offset channel N can be expressed as follows:

n ₁、N₂、N_m may be determined based on the expression of N above, with only the parameters in it being replaced by parameters of the corresponding qubits (data bits, companion bits, auxiliary bits).

Wherein ρ is a density operator of quantum states, P _σ (x) is a gaussian distribution function of the offset x, which may be a momentum offset u, or a position offset v, σ is a noise parameter of the quantum bits,The specific forms of the position and momentum operators are as follows:

Wherein the second error correction operator:

Wherein the number of first, third, first, second, first and second CNOT gates is the same as the number of data bits, and the number of second unitary operators is the same as the number of accompanying bits.

If the stable sub-checking circuit is used for checking whether the data bit is bit-flipped, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both of a first number;

if the stable sub-checking circuit is used for checking whether the data bit is subjected to phase inversion, the data bit is a controlled bit, the accompanying bit is a control bit, and the data bit and the auxiliary bit are both in second quantity; the first number is not equal to the second number.

As shown in fig. 7, fig. 7 is a stable sub-verification circuit diagram for verifying whether bit flipping occurs to the data bits according to an embodiment of the present invention.Is the quantum state of the data bit, Quantum states of auxiliary bits corresponding to data bits,A quantum state of an accompanying bit corresponding to a data bit, wherein one accompanying bit is connected with four data bits, each data bit is connected with an auxiliary bit, i=1, 2,3, 4. The quantum errors generated on the data bits come from the gaussian error offset channel, so that each data bit is acted on by a unitary operator N ₁ corresponding to the gaussian error offset channel, then each data bit and its corresponding auxiliary bit are acted on by a first error correction operator EC, then each data bit and the accompanying bit are acted on by a first CNOT gate, finally the accompanying bit is acted on by a unitary operator N _m corresponding to the gaussian error offset channel, and a second measurement state q _m of the accompanying bit can be obtained by measuring the accompanying bit, wherein the data bit is a control bit in the first CNOT gate, and the accompanying bit is a controlled bit in the first CNOT gate.

Fig. 8 is a quantum circuit diagram of the first error correction operator effect corresponding to fig. 7 according to an embodiment of the present invention. The second CNOT gate acts on the data bit and the corresponding auxiliary bit, wherein the data bit is the control bit of the second CNOT gate, the corresponding auxiliary bit is the controlled bit of the second CNOT gate, then the second error correction operator U _cor acts on the data bit, finally the auxiliary bit is acted by the unitary operator N ₂ corresponding to the Gaussian error offset channel, and the auxiliary bit is measured, so that the first measurement state q _out of the auxiliary bit can be obtained.

Fig. 9 is a schematic diagram of a stable sub-verification circuit for verifying whether phase inversion occurs in the data bits according to an embodiment of the present invention.Is the quantum state of the data bit,Quantum states of auxiliary bits corresponding to data bits,A quantum state of a companion bit corresponding to the data bit, wherein one companion bit is connected to eight data bits, each data bit is connected to one auxiliary bit, i=1, 2, 3, 4, 5, 6, 7, 8. Fig. 10 is a quantum circuit diagram of the first error correction operator effect corresponding to fig. 9 according to an embodiment of the present invention. The quantum logic gate acting on the qubit is similar to that in fig. 7 and 8, and the measurement of the companion bit may result in a second measurement state p _m of the companion bit, where the data bit is the controlled bit in the first CNOT gate and the companion bit is the control bit in the first CNOT gate, and the measurement of the auxiliary bit may result in a first measurement state p _out of the auxiliary bit, which is not described in detail herein.

It should be noted that fig. 7 to 10 can also be used hereThe quantum state of the companion bit corresponding to the data bit willThe quantum states of the auxiliary bits corresponding to the data bits, and others are adaptively modified according to the nomenclature. Other circuits obtained by simple conversion naming according to the present embodiment are substantially the same as the present quantum circuit, and are within the scope of the present invention.

Step 203: and determining error data bits based on the operation result of the stable sub-check line, and performing error correction decoding on the error data bits.

Before the stabilizer checking circuit is operated, all the quantum bits are required to be prepared in an initial state and then operated. The initial states of the data bits are obtained based on whether the stable sub-check line is used for checking whether the data bits are bit flipped or phase flipped or notOr

In a first embodiment provided by the present invention:

the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit, and the determining the error data bit based on the operation result of the stable sub-check line includes:

Specifically, determining that the data bit is in error based on the first output state may be determining whether the first output state is a quantum state without error, if not, determining that the data bit is in error, where the quantum state without error may be determined according to a quantum circuit.

More specifically, the determining the conditional error probability based on the noise parameter of the data bit includes:

Wherein the probability P _σ (x) of the offset x follows a Gaussian distribution function, the probability of the offset is determined based on the noise parameters of the data bits,

Specifically, the determination can be based on the following formula:

The offset x may be a position offset u or a momentum offset v.

Wherein the conditional error probability may be a logical bubbleConditional error probabilityCan also be a logical bubble operatorConditional error probabilityIf it is logical bubble's operatorConditional error probabilityThe corresponding stable sub-check line is used for checking whether the data bit is turned over or not; if it is logical bubble's operatorConditional error probabilityIts corresponding stable sub-check line is used to check whether the data bit is phase flipped.

The conditional error probability is given belowFor a specific way of determining the conditional error probabilitySpecific ways of determining (a) can be referred toThe specific determination manner of (a) is determined, and a detailed description is omitted here.

Wherein,The specific determination mode of (2) is as follows:

More specifically, in terms of said determining erroneous data bits based on said conditional error probability and said second output state, comprising:

Wherein assigning a weight value to an edge in the two-dimensional constrained lattice based on the conditional error probability comprises: the conditional error probability of each data bit is directly taken as the weight value of the corresponding edge in the two-dimensional limited lattice.

The target pairing mode is a pairing mode with the minimum weight calculated by the plurality of pairing modes; then pairing the target vertices two by two based on the edges given with the weight values to obtain a plurality of pairing modes, and determining the target pairing mode of the plurality of pairing modes can be realized by adopting a Minimum Weight Perfect Matching (MWPM) algorithm and a shortest path (Dijkstra) algorithm.

Further, in said building a two-dimensional constrained lattice, comprising:

The color code (color code) may be 8,8,4, which is composed of red quadrangle, green octagon, and blue octagon. The parameters of the 8,8,4 dual lattice may be [72,4,6].

For example, as shown in fig. 11, fig. 11 is a bit layout diagram of 8,8,4 color codes according to an embodiment of the present invention. Solid black dots represent data bits, open squares, broken-line octagons, and solid-line octagons represent companion bits.

Converting the bit arrangement structure of the color code into the dual lattice, as shown in fig. 12, fig. 12 is a schematic diagram of the dual lattice corresponding to the bit arrangement diagram of the color code shown in fig. 11 according to the embodiment of the present invention. In fig. 12, the faces of the triangle are data bits, and the vertices are companion bits.

The solid gray points (blank dots) and their associated sides and faces in fig. 12 are removed to yield fig. 13, a two-dimensional constrained lattice.

Pairing the target vertexes in pairs based on the edges given with the weight values to obtain a plurality of pairing modes, wherein a plurality of connection modes exist between any two points, namely the pairing modes, and the connection modes are not shown in fig. 13;

determining a target pairing mode in a plurality of pairing modes, namely a thickened black solid line in fig. 13; and determining erroneous data bits, gray triangles in fig. 14, based on the target pairing manners.

It can be seen that in the first embodiment provided by the present invention, when a quantum error generated on a data bit comes from a gaussian error offset channel, a stable sub-calibration line including the data bit, an auxiliary bit and an accompanying bit is obtained, and the stable sub-calibration line is operated to obtain a first output state of the auxiliary bit and a second output state of the accompanying bit; when the data bit is determined to be in error based on the first output state, the data bit is determined to be in error based on the noise parameter of the data bit and the second output state, and the data bit in error is decoded in error correction, so that when the quantum error generated on the data bit is from a Gaussian error offset channel, the data bit in error is decoded in error correction.

In a second embodiment provided by the present invention:

The operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit after each operation, and the determining the error data bit based on the operation result of the stable sub-check line includes:

Wherein, the above reference to σ is a noise parameter of the qubit, the noise parameter is determined by the quantum system, and different quantum systems may correspond to different noise parameters of the qubit. Specifically, if the type of the qubit is a data bit, the first noise parameter of the data bit is σ ₁; if the type of the quantum bit is an auxiliary bit, the second noise parameter of the auxiliary bit is sigma ₂; if the type of qubit is a companion bit, then the third noise parameter of the companion bit is σ _m.

Specifically, the determining the first conditional error probability based on the first noise parameter of the data bit and the second noise parameter of the auxiliary bit, and the determining the second conditional error probability based on the second noise parameter of the auxiliary bit and the third noise parameter of the accompanying bit includes:

Wherein the probability P _σ (x) of the offset x follows a gaussian distribution function, the first probability of the offset is determined based on the first noise parameter of the data bit and the second noise parameter of the auxiliary bit, and the second probability of the offset is determined based on the second noise parameter of the auxiliary bit and the third noise parameter of the accompanying bit, in particular based on the following formula:

The first probability is:

if four data bits in the stable sub-check line are connected with one accompanying bit, the second probability is:

If eight data bits in the stable sub-check line are connected with one accompanying bit, the second probability is:

The offset x may be a position offset u or a momentum offset v.

Determining a first conditional error probability based on the first probability, and determining a second conditional error probability based on the second probability, which may be specifically determined based on the following formula:

first conditional error probability:

Second conditional error probability:

specifically, the determining the erroneous data bits based on the first conditional error probability, the second conditional error probability, and the second output state includes:

Specifically, the construction of two-dimensional constrained lattices includes:

Again by way of example with the bit map shown in fig. 11, the bit arrangement of two color codes is converted into two dual lattices, and fig. 12 depicts only the schematic diagram of the dual lattice corresponding to the bit map of one color code, the other being similar thereto.

The solid gray points (blank dots) and their associated sides and faces in fig. 12 are removed to yield fig. 13, a two-dimensional constrained lattice. After the two operations, the two-dimensional limited lattices drawn according to the operation result are connected to obtain the three-dimensional limited lattice shown in fig. 15. The erroneous data bits, i.e. the grey triangles in fig. 14, are determined based on the target pairing scheme, only one plane of which is shown here.

Specifically, a weight value is given to the edge in the three-dimensional restricted lattice based on the first conditional error probability and the second conditional error probability, for example, the first conditional error probability determined after the first operation may be assigned to the edge of the two-dimensional restricted lattice drawn after the first operation, the first conditional error probability determined after the second operation may be assigned to the edge of the two-dimensional restricted lattice drawn after the second operation, and the second conditional error probabilities determined after the first operation and the second operation may be assigned to the edge connected between the two-dimensional restricted lattices.

Specifically, the target pairing mode is a pairing mode with the minimum weight calculated by a plurality of pairing modes; then pairing the target vertices two by two based on the edges given with the weight values to obtain a plurality of pairing modes, and determining the target pairing mode of the plurality of pairing modes can be realized by adopting a Minimum Weight Perfect Matching (MWPM) algorithm and a shortest path (Dijkstra) algorithm.

Specifically, if the stable sub-checking circuit is used for checking whether the data bit is bit flipped, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both of a first number; if the stable sub-checking circuit is used for checking whether the data bit is subjected to phase inversion, the data bit is a controlled bit, the accompanying bit is a control bit, and the data bit and the auxiliary bit are both in second quantity; the first number is not equal to the second number.

It can be seen that, in the embodiment of the present invention, when quantum errors generated on data bits, auxiliary bits and accompanying bits are all from a gaussian error offset channel, a stable sub-check line including the data bits, the auxiliary bits and the accompanying bits is obtained, and the stable sub-check line is operated twice, so as to obtain a first output state of the auxiliary bits and a second output state of the accompanying bits after each operation; when the data bit is determined to be in error based on the first output state obtained after each operation, the data bit which is in error is determined based on the first noise parameter of the data bit, the second noise parameter of the auxiliary bit, the third noise parameter of the accompanying bit and the second output state, and the data bit which is in error is error-corrected and decoded, so that the error data bit is error-corrected and decoded when all quantum errors generated on the data bit, the auxiliary bit and the accompanying bit are from a Gaussian error offset channel.

In summary, it can be seen that in the embodiment of the present invention, firstly, a quantum bit of a generated quantum error from a gaussian error offset channel is determined, then a stable sub-check line is constructed based on the quantum bit, finally, an erroneous data bit is determined based on an operation result of the stable sub-check line, and error correction decoding is performed on the erroneous data bit, so that error correction decoding is performed on the erroneous data bit when the quantum error generated on the quantum bit is from the gaussian error offset channel is realized.

Referring to fig. 16, fig. 16 is a schematic structural diagram of a quantum error correction decoding apparatus according to an embodiment of the present invention, corresponding to the method flow described in fig. 2, where the apparatus includes:

a bit determination unit 1601 for determining a quantum bit from the gaussian error offset channel for the generated quantum error;

a line construction unit 1602 for constructing a stable sub-verification line based on the qubits;

An error correction decoding unit 1603, configured to determine an erroneous data bit based on the operation result of the stable sub-check line, and perform error correction decoding on the erroneous data bit.

Specifically, if the qubit is a data bit, in the aspect of constructing the stabilizer verification line based on the qubit, the line construction unit 1602 is specifically configured to:

Specifically, the first error correction operator includes a second CNOT gate and a second error correction operator, and the line construction unit 1602 is specifically configured to:

Specifically, the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit, and in the aspect of determining the erroneous data bit based on the operation result of the stable sub-check line, the error correction decoding unit 1603 is specifically configured to:

Specifically, in the aspect of determining the conditional error probability based on the noise parameter of the data bit, the error correction decoding unit 1603 is specifically configured to:

Specifically, in terms of the determining erroneous data bits based on the conditional error probability and the second output state, the error correction decoding unit 1603 is specifically configured to:

Specifically, in terms of the building of the two-dimensional constrained lattice, the error correction decoding unit 1603 is specifically configured to:

Specifically, if the qubit is a data bit, an auxiliary bit, and an accompanying bit, in the aspect of constructing the stable sub-verification line based on the qubit, the line construction unit 1602 is specifically configured to:

Specifically, the first error correction operator includes a second CNOT gate, a third unitary operator corresponding to the gaussian error offset channel, and a second error correction operator, and the line construction unit 1602 is specifically configured to:

Specifically, the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit after each operation, and in the aspect of determining the erroneous data bit based on the operation result of the stable sub-check line, the error correction decoding unit 1603 is specifically configured to:

Determining a first conditional error probability based on a first noise parameter of the data bit and a second noise parameter of the auxiliary bit, and determining the second conditional error probability based on a third noise parameter of the accompanying bit when determining that the data bit is erroneous based on the first output state obtained after each operation;

Specifically, in the aspect that the first conditional error probability is determined based on the first noise parameter of the data bit and the second noise parameter of the auxiliary bit, and the second conditional error probability is determined based on the third noise parameter of the accompanying bit, the error correction decoding unit 1603 is specifically configured to:

determining a first probability of an offset based on a first noise parameter of the data bit and a second noise parameter of the auxiliary bit, and determining a second probability of the offset based on a third noise parameter of the companion bit;

Specifically, in the aspect of determining the erroneous data bits based on the first conditional error probability, the second conditional error probability, and the second output state, the error correction decoding unit 1603 is specifically configured to:

Determining target vertexes corresponding to the error-reported accompanying bits in the two-dimensional limited crystal lattice based on the second output states determined after each operation respectively;

Assigning a weight value to edges in the three-dimensional constrained lattice based on the first conditional error probability and the second conditional error probability determined after each run;

Specifically, in terms of the construction of two-dimensional constrained lattices, the error correction decoding unit 1603 is specifically configured to:

Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:

Constructing a stable sub-verification line based on the qubits;

Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

Specifically, the electronic device may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.

Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:

Constructing a stable sub-verification line based on the qubits;

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A quantum error correction decoding method, comprising:

Constructing a stable sub-verification line based on the qubits; if the quantum bit is a data bit, acquiring the data bit, an auxiliary bit and an accompanying bit, and acquiring a unitary operator, a first error correction operator and a first CNOT gate corresponding to the Gaussian error offset channel; the first error correction operator comprises a second CNOT gate and a second error correction operator, the stable sub-checking circuit is obtained by adding a first quantum logic gate corresponding to a unitary operator to each data bit, adding the second CNOT gate to each data bit and auxiliary bits corresponding to each data bit, adding the second error correction operator to each data bit, and adding the first CNOT gate to each data bit and accompanying bits in sequence; wherein one companion bit is connected to a plurality of data bits, each data bit being connected to one auxiliary bit; the data bit is a control bit of the second CNOT gate, and the corresponding auxiliary bit is a controlled bit of the second CNOT gate;

2. The method of claim 1, wherein the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit, wherein the determining the erroneous data bit based on the operation result of the stable sub-check line includes:

Determining a probability of an offset based on a noise parameter of the data bit when the data bit is determined to be in error based on the first output state; determining a conditional error probability based on the probability of the offset;

3. The method of claim 2, wherein said constructing a two-dimensional constrained lattice comprises:

4. The method according to claim 1, wherein the method further comprises: if the quantum bit is a data bit, an auxiliary bit and an accompanying bit, acquiring a first unitary operator and a second unitary operator corresponding to the Gaussian error offset channel, and acquiring a first error correction operator and a first CNOT gate; the first error correction operator comprises a second CNOT gate, a third unitary operator corresponding to the Gaussian error offset channel and a second error correction operator, the stable sub-checking line is obtained by sequentially adding a first quantum logic gate corresponding to the first unitary operator to each data bit, adding the second CNOT gate to each data bit and an auxiliary bit corresponding to each data bit, adding a fourth quantum logic gate corresponding to the third unitary operator to the auxiliary bit, adding the second error correction operator to each data bit, adding a first CNOT gate to each data bit and the accompanying bit, and adding a third quantum logic gate corresponding to the second unitary operator to the accompanying bit; wherein one companion bit is connected to a plurality of data bits, each data bit being connected to one auxiliary bit; the data bit is a control bit of the second CNOT gate, and the corresponding auxiliary bit is a controlled bit of the second CNOT gate.

5. The method of claim 4, wherein the operation result includes a first output state of the auxiliary bit and a second output state of the accompanying bit after each operation, wherein determining the erroneous data bit based on the operation result of the stable sub-check line includes:

Determining a first conditional error probability based on a first noise parameter of the data bit and a second noise parameter of the auxiliary bit, and determining a second conditional error probability based on the second noise parameter of the auxiliary bit and a third noise parameter of the accompanying bit when determining that the data bit is erroneous based on the first output state obtained after each operation;

6. The method of claim 5, wherein the determining a first conditional error probability based on the first noise parameter of the data bit and the second noise parameter of the auxiliary bit, and the determining a second conditional error probability based on the second noise parameter of the auxiliary bit and the third noise parameter of the companion bit comprises:

7. The method of any of claims 1-6, wherein if the stable sub-check line is used to check whether a bit flip occurs in the data bit, the data bit is a control bit, the accompanying bit is a controlled bit, and the data bit and the auxiliary bit are both a first number; if the stable sub-checking circuit is used for checking whether the data bit is subjected to phase inversion, the data bit is a controlled bit, the accompanying bit is a control bit, and the data bit and the auxiliary bit are both in second quantity; the first number is not equal to the second number.

8. A quantum error correction decoding apparatus, comprising:

A line construction unit for constructing a stable sub-verification line based on the qubits; if the quantum bit is a data bit, acquiring the data bit, an auxiliary bit and an accompanying bit, and acquiring a unitary operator, a first error correction operator and a first CNOT gate corresponding to the Gaussian error offset channel; the first error correction operator comprises a second CNOT gate and a second error correction operator, the stable sub-checking circuit is obtained by adding a first quantum logic gate corresponding to a unitary operator to each data bit, adding the second CNOT gate to each data bit and auxiliary bits corresponding to each data bit, adding the second error correction operator to each data bit, and adding the first CNOT gate to each data bit and accompanying bits in sequence; wherein one companion bit is connected to a plurality of data bits, each data bit being connected to one auxiliary bit; the data bit is a control bit of the second CNOT gate, and the corresponding auxiliary bit is a controlled bit of the second CNOT gate;

9. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-7.

10. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program, which is executed by a processor to implement the method of any of claims 1-7.