CN116136663A

CN116136663A - BLVDS bus link and control system

Info

Publication number: CN116136663A
Application number: CN202111369251.3A
Authority: CN
Inventors: 周位强; 陆卫军; 杨振国; 朱腾; 胡志杨
Original assignee: Zhejiang Supcon Technology Co Ltd
Current assignee: Zhejiang Supcon Technology Co Ltd
Priority date: 2021-11-18
Filing date: 2021-11-18
Publication date: 2023-05-19

Abstract

The application provides a BLVDS bus link and a control system, and relates to the technical field of industrial control and the technical field of electronic power. The BLVDS bus link comprises a pedestal, a plurality of first pedestals, and a plurality of cards. Wherein the plurality of first pedestals are sequentially connected on the pedestal through a BLVDS bus; each first base of the plurality of first bases is used for forming a T-shaped topology with two clamping pieces of the plurality of clamping pieces, and the two clamping pieces of the plurality of clamping pieces are branches of the T-shaped topology. By utilizing the technical scheme of the embodiment of the application, the quality of signal transmission is improved, and the reliability of communication at high data rate is ensured.

Description

BLVDS bus link and control system

Technical Field

The present disclosure relates to the field of industrial control technologies, and in particular, to a BLVDS bus link, a control system, and an electronic device.

Background

The bus low voltage differential signal (BUS Low Voltage Differential Signaling, BLVDS) is a bus differential signal developed from a low voltage differential signal and having the characteristics of high speed, low swing, low noise, and multiple loads.

The BLVDS bus communication may be applied in an automation control system, but as the functions of controllers in the automation control system are increased, the functions of single-load cards are more and more complex, so that the requirements of the automation system on the Data Rate (Data Rate) of the BLVDS bus communication are higher and higher.

However, in the practical application of the multi-node bus, a certain Stub length will be generally existed in the load branch, which may cause the problems of too large signal return channel, too high overshoot, too large ringing amplitude, etc., which reduces the transmission quality of the signal, and even causes that the signal cannot be identified normally, that is, the reliability of communication at high data rate cannot be ensured.

Disclosure of Invention

In order to solve the technical problems in the prior art, the application provides a BLVDS bus link and control system, which improves the quality of signal transmission and ensures the reliability of communication at high data rate.

In a first aspect, the present application provides a BLVDS bus link including a pedestal, a plurality of first pedestals, and a plurality of cards. The first pedestals are sequentially connected on the pedestal through a BLVDS bus. Each of the plurality of first bases is configured to form a T-topology with two of the plurality of clips, and the two of the plurality of clips are branches of the T-topology.

By means of the scheme, the first bases and the two clamping pieces are connected to form a T-shaped topology, the two clamping pieces on the bases are symmetrical, so that branching paths are equal in length, mutual cancellation of reflected signals can be effectively achieved, and influence of the reflected signals on signal quality is reduced. By means of the scheme, the signal back channel, overshoot and ringing amplitude are reduced, the signal transmission quality is improved, and the communication reliability at high data rate is guaranteed.

In one possible implementation, the base includes a plurality of base terminals thereon;

each of the plurality of pedestal terminals is used for connecting each of the plurality of first bases in a one-to-one correspondence.

In one possible implementation, a termination resistor corresponding to each of the plurality of clips is disposed on the corresponding connected first base.

In one possible implementation, the BLVDS bus link includes a first transmission line and a second transmission line, the first transmission line and the second transmission line being a set of differential lines. The first end of each first base in the plurality of first bases is connected with a first transmission line, and the second end of each first base in the plurality of first bases is connected with a second transmission line. The first end of each first base in the plurality of first bases is connected with the first ends of the corresponding two clamping pieces respectively after passing through a terminating resistor. The second end of each first base in the plurality of first bases is connected with the second ends of the corresponding two clamping pieces respectively after passing through the other terminating resistor.

In one possible implementation, each of the plurality of clips includes a controller. The first end of the controller is connected with the first end of the clamping piece, and the second end of the controller is connected with the second end of the clamping piece.

In one possible implementation, each clip of the plurality of clips further includes a first resistor and a second resistor. The first end of the controller is connected with the first end of the clamping piece through the first resistor, and the second end of the controller is connected with the second end of the clamping piece through the second resistor.

In one possible implementation, each of the plurality of first pedestals further includes a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. One termination resistor of each of the plurality of first bases is connected with the first end of one clamping piece of the corresponding two clamping pieces after passing through the third resistor, and is connected with the first end of the other clamping piece of the corresponding two clamping pieces after passing through the fourth resistor. The other end resistor of each first base in the plurality of first bases is connected with the second end of one clamping piece in the corresponding two clamping pieces through the fifth resistor and connected with the second end of the other clamping piece in the corresponding two clamping pieces through the sixth resistor.

In one possible implementation, the bus link further comprises at least one second pedestal. The at least one second base and the plurality of first bases are sequentially connected on the base frame through the BLVDS bus, each second base in the at least one second base is used for forming a T-shaped topology with two clamping pieces in the plurality of clamping pieces, each second base in the at least one second base is connected with a hollow Pin (Pin) of one clamping piece in the two clamping pieces, and two clamping pieces in the plurality of clamping pieces are branches of the T-shaped topology.

In a second aspect, the present application provides a control system comprising the BLVDS bus link provided by the above implementation, and further comprising at least one master device and at least one slave device. Wherein the at least one master device is configured to control the at least one slave device over the BLVDS bus link.

By utilizing the control system provided by the application, the signal return channel, overshoot and ringing amplitude are reduced, and the signal transmission quality is improved, so that the communication reliability of the master control equipment and the slave equipment at a high data rate can be ensured.

In one possible implementation, the slave device may be a sensor or a transmitter.

Drawings

FIG. 1 is a schematic diagram of a BLVDS bus link;

FIG. 2 is an equivalent topology corresponding to FIG. 1;

FIG. 3 is an equivalent simplified diagram of the topology corresponding to FIG. 2;

FIG. 4 is a waveform simulation diagram of U8 reception;

FIG. 5 is a waveform diagram of an actual test of a U8 receiving end;

fig. 6 is a schematic topology diagram of a BLVDS bus link according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a BLVDS bus link provided in an embodiment of the application;

FIG. 8 is a schematic diagram of another BLVDS bus link provided in an embodiment of the application;

FIG. 9 is a waveform simulation diagram of the U8 reception corresponding to FIG. 8;

FIG. 10 is a diagram of the detection result of the actual waveform of U8 corresponding to FIG. 8;

FIG. 11 is a schematic diagram of a single-ended topology corresponding to FIG. 3;

FIG. 12 is an exploded view of the single-ended signal of FIG. 11;

FIG. 13 is a schematic diagram I of signal reflection provided in an embodiment of the present application;

FIG. 14 is an exploded view of the topology function corresponding to FIG. 11;

fig. 15A is a schematic view of a driving portion provided in an embodiment of the present application;

fig. 15B is a schematic diagram two of a driving portion provided in an embodiment of the present application;

FIG. 16 is a comparative schematic diagram of topology adjustment provided in an embodiment of the present application;

FIG. 17 is a second schematic diagram of the reflection waveform corresponding to FIG. 16 according to an embodiment of the present disclosure;

FIG. 18 is a second schematic diagram of the reflection waveform corresponding to FIG. 16 according to the embodiment of the present application;

FIG. 19 is a schematic diagram of a pedestal of a conventional BLVDS bus link;

fig. 20 is a schematic diagram of a pedestal of a BLVDS bus link provided in an embodiment of the present application;

FIG. 21 is a schematic diagram of a base of a conventional BLVDS bus link;

fig. 22 is a schematic diagram of a base of a BLVDS bus link provided in an embodiment of the present application;

fig. 23 is a circuit diagram of a BLVDS bus link according to an embodiment of the present application;

fig. 24 is a schematic diagram of a control system according to an embodiment of the present application.

Detailed Description

In order to make the person skilled in the art more clearly understand the application scheme, the application scenario of the application scheme is first described below.

Referring to fig. 1, a schematic diagram of a BLVDS bus link is shown.

The BLVDS bus link includes 12

cards

10, 6

pedestals

20, 1

pedestal

30, and 1 power interface 40.

The BLVDS bus (hereinafter referred to as bus) is distributed on a printed circuit board (Printed Circuit Board, PCB) of the base frame 30, and the card 10 is an Input/Output (IO) card. The base 20 is used for connecting the base frame 30 and the connection terminals on the clamping pieces 10, so that each clamping piece 10 can realize data interaction with a bus on the base frame 30.

Each card 10 includes a controller thereon, which may be an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a programmable logic device (Programmable Logic Device, PLD), a digital signal processor (Digital Signal Processor, DSP), or a combination thereof. The PLD may be a complex programmable logic device (Complex Programmable Logic Device, CPLD), a Field programmable gate array (Field-programmable Gate Array, FPGA), a general-purpose array logic (Generic Array Logic, GAL), or any combination thereof, and embodiments of the present application are not particularly limited.

Referring to fig. 2, the equivalent topology corresponding to fig. 1 is shown.

In fig. 2, the connector has a length of about 1 inch (in).

Referring to fig. 3, this is an equivalent simplified diagram of the topology corresponding to fig. 2.

In fig. 3, the resistances of the base 20 and the traces on the pedestal 30 shown in fig. 2 are combined, the unit of the illustrated resistances is ohm (Ω), the termination resistance is 22Ω, and the resistance of the base 20 is 2.5Ω.

Wherein a 22 omega termination resistance is used to achieve impedance matching. That is, for waveform signals, nonlinear impedance is generated during transmission and use, for example, nonlinear elements such as capacitance or inductance exist in a circuit, and a resistor is added in the circuit to ensure that the impedance of the circuit does not affect the signal, and the resistor is a termination resistor.

Six of the clips, U5 through U10, are shown schematically in FIG. 3.

The inventor finds that after directly inserting U5 to U10, if U7 is used as a driving end and U8 is used as a receiving end, a signal waveform received by U8 will generate a large emission signal, and specifically, see a waveform simulation diagram received by U8 shown in fig. 4. It can be found that the waveform signal received by the U8 is distorted, which can generate a large back hook, so that the signal data cannot be effectively transmitted.

Referring to fig. 5, the waveforms of the actual test of the U8 receiver are shown.

The waveform of the U8 receiving end is actually measured through the oscilloscope, the result is consistent with the simulation waveform, and the echo is very large.

For 12 clamping pieces in fig. 1, after the driving end and the receiving end are changed, various combination modes exist, and the inventor finds that the problems of large back hook and signal waveform distortion exist under various working conditions through multiple times of measurement. This is because in the practical application of the multi-node bus, the load branch generally has a Stub (Stub) length of 4 to 5 cm, which causes problems such as excessive signal return channel, excessive overshoot, excessive ringing amplitude, etc., which reduces the transmission quality of the signal and even causes the signal to be unable to be identified normally. Tests have found that the illustrated BLVDS bus link has failed to ensure reliable communication at a data rate of 128M, and even more so, when the data rate continues to be increased to 500M.

In order to solve the above problems, the present application provides a BLVDS bus link and control system, so that each first base on a base frame and two connected clamping pieces form a T-shaped topology, and two clamping pieces on each base are symmetrical, so that branching paths are equal, mutual cancellation of reflected signals can be effectively realized, and influence of the reflected signals on signal quality is reduced. By means of the scheme, the signal back channel, overshoot and ringing amplitude are reduced, the signal transmission quality is improved, and the communication reliability at high data rate is guaranteed.

In order to make the technical solution more clearly understood by those skilled in the art, the following description will refer to the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application.

The words "first," "second," and the like in the description herein are used for descriptive purposes only and are not to be interpreted as indicating or implying a relative importance or implicitly indicating the number of features indicated

In the present application, unless explicitly specified and limited otherwise, the term "coupled" is to be construed broadly, and for example, "coupled" may be either fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate medium.

The embodiments of the present application provide a specific description below with reference to the accompanying drawings.

Referring to fig. 6, a schematic diagram of a BLVDS bus link according to an embodiment of the present application is shown.

The BLVDS bus link includes a pedestal 30, a plurality of pedestals 20, and a plurality of cards 10.

Each pedestal 20 is connected in turn on the pedestal by a BLVDS bus.

Each base 20 is configured to form a T-topology with two clips 10, and the two clips 10 are branches of the T-topology.

Referring to fig. 7, a schematic diagram of a BLVDS bus link according to an embodiment of the present application is shown.

For the BLVDS bus link provided by the embodiment of the application, the two clamping pieces on each base are symmetrical, so that the branched paths are equal in length, mutual cancellation of the reflected signals can be effectively realized, and the influence of the reflected signals on the signal quality is reduced. By means of the scheme, the signal back channel, overshoot and ringing amplitude are reduced, the signal transmission quality is improved, and the communication reliability at high data rate is guaranteed.

The following description is made in connection with specific implementations.

The scheme of the embodiment of the application achieves the purpose of eliminating the back hook by improving the topology of the BLVDS bus link, and ensures the reliability in the signal transmission process.

Referring to fig. 8, a schematic diagram of another BLVDS bus link according to an embodiment of the present application is shown.

The illustrated BLVDS bus link uses the principle of T-branches to form standing waves by adjusting the topology so that reflected waves cancel each other.

Six of the clips, U5 through U10, are shown schematically in FIG. 8. Wherein, the unit corresponding to each resistance value is ohm.

At this time, the topology is simulated by using U7 as the driving end and U8 as the receiving end, and the waveform simulation diagram of the U8 is shown in fig. 9. The waveform of the U8 receiving end is actually measured by an oscilloscope, and the obtained actual waveform detection result is shown in fig. 10. Comparing with the waveforms shown in fig. 4 and fig. 5, it can be found that by adopting the technical scheme of the application, the problems of back hooking and reflection of the waveforms are remarkably reduced, and the quality of signal transmission is improved.

Because the topology of the BLVDS bus link has certain symmetry, when the U7 in the figure 8 is used as the driving end, the adjacent U5 and U6 are used as one group, the U9 and U10 are used as one group, and the two groups of clamping pieces form a symmetrical and equal-branch structure, so that the influence of waveform reflection on the signal quality can be effectively counteracted, namely, the U8 can simultaneously receive the reflected signals from the U5 to the U10, and the effect of counteracting the reflected waveforms is achieved.

The effect of signal quality on the number of clips is described below.

With continued reference to fig. 8, it can be seen that the presence of U8 is beneficial to cancellation of the reflected waveform, and when the number of the two sides of the pair of U7 and U8 is odd, the cancellation effect of the reflected waveform is poor, and when the number of the two sides of the pair of U7 and U8 is even, the cancellation effect of the reflected waveform is good. Specifically, when the two sides of the pair of clamping pieces U7 and U8 are not connected with the clamping pieces, or the two sides are respectively connected with one clamping piece, or the two sides are respectively connected with the two clamping pieces, the reflection waveform cancellation effect is good.

When one of two sides of the pair of clamping pieces U7 and U8 is not connected with the clamping piece, the other side is connected with one clamping piece; or one side is connected with one clamping piece, and when the other side is connected with two clamping pieces, the reflection waveform counteracts the effect poorly.

Through test analysis, it can be determined that when one of the two sides of the U7 is connected with one clamping piece, the other side is connected with two clamping pieces, and the U8 clamping piece is not inserted, the reflection waveform counteracts the worst effect.

The worst working condition of the clamping piece during splicing can be found by adopting the novel topological structure of the embodiment of the application, so that the waveform quality under all working conditions is ensured.

The following specifically describes the principle of the present application for realizing reflection waveform cancellation.

See also fig. 11 and 12. Fig. 11 is a schematic diagram of a single-ended topology corresponding to fig. 3, and fig. 12 is an exploded schematic diagram of a single-ended signal corresponding to fig. 11.

When the U7 is used as the driving end, the left and right sides of the driving end are respectively in a fly-by topological structure, and meanwhile, the U7 is connected to form a T-shaped topology. This topology has fly-by characteristics and also T-topology characteristics. The fly-by structure has many branches, each branch has impedance discontinuity, and the signal is reflected back and forth between stubs.

Referring to fig. 13, a schematic diagram of signal reflection provided in an embodiment of the present application is shown.

As shown in fig. 13, the solid arrow direction is the current flow direction, and the broken arrow direction is the flow direction of the first reflection current.

The Stub length is required to be enough according to the flyback topology principle, and the load is uniformly distributed to ensure the signal quality.

However, it is difficult to meet the topology requirements for branch length, limited by the manufacturability design (Design for Manufacturing, DFM) of the clip, with a Stub shortest length of about 2.5 in.

Meanwhile, due to the insertion and extraction of the clamping piece, the distance between the rack wiring lines is about 9.7in and 0.28in respectively, and uneven load distribution can be caused. Conventional interconnection approaches fail to meet design requirements and a more suitable topology needs to be sought.

Referring to fig. 14, an exploded view of the corresponding topology of fig. 11 is shown.

In fig. 14, the topology is decomposed into a driving section, a transmission bus section, and a reception function section. The resistance of the transmission bus part includes the resistance of the bus link between the cards, such as the resistance of the bus link between U5 and U6, the resistance of the bus link between U7 and U8, the resistance of the bus link between U9 and U10, and the like, and includes 0.28 ohms on both sides of the bus link edge.

Wherein the function of the driving part is to transmit the signal to the transmission bus to the maximum extent. The closer the 22 ohm resistor is to the junction branch point, the better the signal transmission effect.

See also fig. 15A and 15B. Fig. 15A is a schematic diagram of a first driving portion provided in an embodiment of the present application, and fig. 15B is a schematic diagram of a second driving portion provided in an embodiment of the present application.

15A and 15B differ in the location of the 1 ohm resistance and the 2.5 ohm resistance.

The bus link resistance of 0.28 ohms between each pair of cards was then removed, resulting in a new T-topology.

See also fig. 16 and 17. Fig. 16 is a schematic diagram illustrating topology adjustment according to an embodiment of the present application; fig. 17 is a schematic diagram one of the reflection waveforms corresponding to fig. 16 provided in the embodiment of the present application.

For the T-topology shown in fig. 17, the solid arrow direction is the current flow direction, and the dashed arrow direction is the flow direction of the first reflected current. The T-topology can be found to be effective in creating cancellation of reflected waveforms.

Referring to fig. 18, a second schematic diagram of the reflection waveform corresponding to fig. 16 according to an embodiment of the present application is shown.

The figure shows that the directions of solid arrows on the transmission lines on both sides are the current flows, and the directions of broken arrows are the flows of the first reflected currents, with U7 as the driving end. The reflection signal can be effectively matched, the topology is combined with the T-shaped topology on the fly-by basis, the reflection cancellation function is realized by utilizing the advantages of the T-shaped topology, the restriction of the fly-by topology on stub length is well solved, the fly-by topology is reserved, the advantages of high quality, low noise and simple wiring of the signal are also ensured, the DFM limitation of the clamping piece is also well solved, and the problem that the connector type pin is short is solved, namely, the hardware cost is reduced while the signal quality is improved.

The following describes a base frame implementation manner in the technical scheme of the application with reference to the accompanying drawings.

Referring to fig. 19, a schematic diagram of a pedestal of a conventional BLVDS bus link is shown.

The pedestal 30 of the BLVDS bus link includes 12 pedestal terminals 301, each 2 pedestal terminals 301 being configured to connect to a pedestal, forming 6 sets of pedestal terminals 301, with a spacing of 0.28in between two pedestal terminals 301 of each set.

Referring to fig. 20, a schematic diagram of a pedestal of a BLVDS bus link according to an embodiment of the present application is shown.

After the scheme of the application adopts the T-shaped framework, the two base frame terminals 301 with the internal phase of 0.28in the original group are combined into one base frame terminal, so that only 6 base frame terminals 301 are required to be distributed on the base frame 30, the hardware cost is saved, and the bus length on the base frame 30 is shortened.

The following describes a base implementation manner in the technical scheme of the present application with reference to the accompanying drawings.

Referring to fig. 21, a schematic diagram of a base of a conventional BLVDS bus link is shown.

The original base 20 includes two base terminals 201, and each base terminal 201 is used for connecting with a clamping piece.

Referring to fig. 22, a schematic diagram of a base of a BLVDS bus link according to an embodiment of the present application is shown.

After the scheme of the embodiment of the application adopts a T-shaped structure, the 22 ohm terminating resistor is arranged on the base and is connected in a T-branch mode, namely, one clamping piece is connected after one base terminal 201 is branched, and each clamping piece is connected with one terminating resistor.

Referring to fig. 23, a circuit diagram of a BLVDS bus link is provided in an embodiment of the present application.

The BLVDS bus link includes a first transmission line and a second transmission line, the first transmission line and the second transmission line being a set of differential lines.

The first end of each base 20 is connected to a first transmission line, and the second end of each base 20 is connected to a second transmission line.

The first end of each base 20 is connected to the first ends of the corresponding two clips through a terminating resistor.

The second end of each base 20 is connected to the second ends of the corresponding two clips through the other terminating resistor.

Each clip includes a controller, which may be ASIC, PLD, DSP or a combination thereof. The PLD may be CPLD, FPGA, GAL or any combination thereof, and the embodiments are not specifically limited

The first end of the controller is connected with the first end of the clamping piece, and the second end of the controller is connected with the second end of the clamping piece.

Each clamping piece further comprises a first resistor and a second resistor, the first end of the controller is connected with the first end of the corresponding clamping piece through the first resistor, and the second end of the controller is connected with the second end of the corresponding clamping piece through the second resistor. The first illustrated resistor comprises two resistors connected in series with a resistance of 1 ohm and the second illustrated resistor comprises two resistors connected in series with a resistance of 1 ohm.

The base 20 further includes a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. One termination resistor of each base is connected with the first end of one clamping piece of the corresponding two clamping pieces after passing through the third resistor, and is connected with the first end of the other clamping piece of the corresponding two clamping pieces after passing through the fourth resistor. The other end resistor of each first base is connected with the second end of one clamping piece of the corresponding two clamping pieces through the fifth resistor and connected with the second end of the other clamping piece of the corresponding two clamping pieces through the sixth resistor.

The third resistor, the fourth resistor and the fifth resistor may be a single resistor or may be a resistor network, which is not limited in this embodiment of the present application, for example, the resistors above all adopt a resistor of 1 ohm and a resistor of 0.5 ohm which are connected in series in the figure as an example.

In some embodiments, the load of some bases 20 on the base frame 30, that is, the number of the clips connected to the bases 20 is not two, for example, only one clip is connected to some bases 20, so that the bases 20 still form an equal-branch structure, the bases 20 can be normally connected to one clip, and when the bases 20 are connected to another clip, the bases 20 are connected to the empty Pin of the controller of the other clip, so that the two clips are branches of the T-type topology, and symmetry is maintained.

For the BLVDS bus link shown in fig. 23, branches form a T-type topology, two cards on each base 20 are symmetrical, and a termination resistor is disposed at a position close to a bus link end, so that a connection distance between the bus link and an IO chip on the card is shortened, and design requirements can be met only by a common process and a common plug-in, a processing manner is simple, and hardware cost is reduced. In addition, by adopting the scheme, the waveform quality is improved to a greater extent, the prediction analysis on the worst working condition of the BLVDS bus link is facilitated, and the usability is improved.

Based on the BLVDS bus link provided in the above embodiment, the present embodiment also provides a control system, where the control system applies the above BLVDS bus link, and is described in detail below with reference to the accompanying drawings.

Referring to fig. 24, a schematic diagram of a control system according to an embodiment of the present application is provided.

The control system 240 includes the BLVDS bus link 241 provided by the above implementations, and also includes at least one master device 242 and at least one slave device 243. Wherein at least one master device 242 is used to control at least one slave device 243 over the BLVDS bus link 241.

It should be understood that in this application, "at least one" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. The apparatus embodiments described above are merely illustrative, wherein the units and modules illustrated as separate components may or may not be physically separate. In addition, some or all of the units and modules can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

The foregoing is merely exemplary of the application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the application and are intended to be comprehended within the scope of the application.

Claims

1. A BLVDS bus link, the BLVDS bus link comprising a pedestal, a plurality of first pedestals, and a plurality of cards;

the first pedestals are sequentially connected on the pedestal through a BLVDS bus;

each first base of the plurality of first bases is used for forming a T-shaped topology with two clamping pieces of the plurality of clamping pieces, and the two clamping pieces of the plurality of clamping pieces are branches of the T-shaped topology.

2. The bus link of claim 1, wherein the pedestal includes a plurality of pedestal terminals thereon;

each base frame terminal in the plurality of base frame terminals is used for being connected with each first base seat in the plurality of first base seats in a one-to-one correspondence mode.

3. The bus link of claim 1, wherein a termination resistor for each of the plurality of clips is disposed on the corresponding connected first base.

4. A bus link as claimed in claim 3, wherein the BLVDS bus link comprises a first transmission line and a second transmission line, the first transmission line and the second transmission line being a set of differential lines;

a first end of each first base of the plurality of first bases is connected with the first transmission line, and a second end of each first base of the plurality of first bases is connected with the second transmission line;

the first ends of each first base in the plurality of first bases are respectively connected with the first ends of the corresponding two clamping pieces after passing through one terminating resistor;

the second end of each first base in the plurality of first bases is respectively connected with the second ends of the corresponding two clamping pieces after passing through the other terminating resistor.

5. The bus link of claim 5, wherein each card of the plurality of cards includes a controller;

6. The bus link of claim 6, wherein each of the plurality of clips further comprises a first resistor and a second resistor;

the first end of the controller is connected with the first end of the clamping piece through the first resistor;

the second end of the controller is connected with the second end of the clamping piece through the second resistor.

7. The bus link of claim 4, wherein each of the plurality of first pedestals further comprises a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

one of the termination resistors of each of the plurality of first bases is connected with the first end of one of the corresponding two clamping pieces after passing through the third resistor, and is connected with the first end of the other of the corresponding two clamping pieces after passing through the fourth resistor;

the other terminating resistor of each first base in the plurality of first bases is connected with the second end of one clamping piece in the corresponding two clamping pieces after passing through the fifth resistor, and is connected with the second end of the other clamping piece in the corresponding two clamping pieces after passing through the sixth resistor.

8. The bus link of any one of claims 1-7, further comprising at least one second pedestal;

the at least one second base and the plurality of first bases are sequentially connected on the pedestal through the BLVDS bus;

each second base in the at least one second base is used for forming a T-shaped topology with two clamping pieces in the plurality of clamping pieces, each second base in the at least one second base is connected with a hollow pin of one clamping piece in the two clamping pieces, and the two clamping pieces in the plurality of clamping pieces are branches of the T-shaped topology.

9. A control system comprising the BLVDS bus link of any of claims 1 to 8, further comprising at least one master device and at least one slave device;

the at least one master device is configured to control the at least one slave device through the BLVDS bus link.

10. The control system of claim 9, wherein the at least one slave device is a sensor or a transmitter.