CN116136566A - Chip test system - Google Patents

Chip test system Download PDF

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Publication number
CN116136566A
CN116136566A CN202111357484.1A CN202111357484A CN116136566A CN 116136566 A CN116136566 A CN 116136566A CN 202111357484 A CN202111357484 A CN 202111357484A CN 116136566 A CN116136566 A CN 116136566A
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module
interface
universal bus
bus
universal
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CN202111357484.1A
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司丰炜
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Ziguang Tongxin Microelectronics Co Ltd
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Ziguang Tongxin Microelectronics Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The application provides a chip test system, including: a programmable logic device; the programmable logic device includes: the device comprises a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module, wherein the universal bus conversion module is used for realizing bus conversion between a chip test program loading interface and a universal bus main interface, and the chip test program loading interface is used for loading a chip test program. The universal bus interconnection module is used for realizing interconnection of the universal bus master interface and the plurality of universal bus slave interfaces. The first slave interface of the universal bus is connected with a universal bus decoding module, and the universal bus decoding module is used for connecting various interface bus modules. The at least one universal bus second slave interface is respectively connected with each logic module of the chip to be tested and used for testing each logic module of the chip to be tested. Therefore, interaction between various interface bus modules and logic modules of the chip to be tested can be realized, and switching among different modes is realized, so that the universality is improved, and the requirements of different scenes can be met.

Description

Chip test system
Technical Field
The present disclosure relates to the field of chip testing, and in particular, to a chip testing system.
Background
Logic engineers often need to do some work for verifying feasibility in the early stage of a project, for example, verifying whether a certain analog-to-digital conversion (analog digital convert, ADC) chip meets the requirements of project application, and when verifying, communication between an internal module and an external module of the chip and communication between all modules in the chip are needed, however, different test platforms are needed to be built for different bus interfaces for testing at the present stage, so that the logic engineers have no universality, lower test efficiency and higher cost.
Disclosure of Invention
In view of the above, the present application is directed to a chip testing system, which has versatility and can adapt to the requirements of different scenarios.
In order to achieve the above purpose, the present application has the following technical scheme:
in a first aspect, embodiments of the present application provide a chip test system, including a programmable logic device; the programmable logic device includes: the device comprises a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module;
one end of the universal bus conversion module is connected with the chip test program loading interface, and the other end of the universal bus conversion module is connected with the universal bus main interface and is used for realizing bus conversion between the chip test program loading interface and the universal bus main interface; the chip test program loading interface is used for loading a chip test program;
one end of the universal bus interconnection module is connected with the universal bus master interface, and the other end of the universal bus interconnection module is respectively connected with the universal bus first slave interface and at least one universal bus second slave interface, so that the universal bus master interface is interconnected with a plurality of universal bus slave interfaces;
the first slave interface of the universal bus is connected with the universal bus decoding module; the universal bus decoding module is used for connecting various interface bus modules;
the at least one universal bus second slave interface is respectively connected with each logic module of the chip to be tested and used for testing each logic module of the chip to be tested.
In one possible implementation, the system further includes: input/output buffers of various level formats;
one end of the input/output buffer with the multiple level formats is connected with the programmable logic device; and the other ends of the input and output buffers with the multiple level formats are respectively connected with an electrical interface of external equipment and are used for converting the multiple level formats into the level formats of the programmable logic device.
In one possible implementation, the chip test program includes: tool command language TCL script program.
In one possible implementation, the universal bus conversion module includes:
the joint test workgroup interfaces to the advanced extensible interface JTAG to AXI module, or MicroBlaze soft cores.
In one possible implementation, when the universal bus conversion module is the MicroBlaze soft core, the chip test program is a C program.
In one possible implementation, the programmable logic device includes: the Field Programmable Gate Array (FPGA).
In one possible implementation, the universal bus interconnect module includes: the advanced extensible interface interconnects the AXI Interconnect modules.
In one possible implementation, the universal bus decoding module includes: the advanced extensible interface decodes the AXI decoder module.
In one possible implementation, the plurality of interface bus modules includes: SPI module and internal integrated circuit I 2 At least two of a C module, a general purpose input/output port GPIO module, a universal asynchronous receiver transmitter UART module and a PULSE module.
In one possible implementation, the multiple level format includes: at least two of a 5V transistor logic level TTL, a 3.3V low voltage transistor logic level LVTTL, a 2.5V low voltage transistor logic level LVTTL, a 1.8V low voltage transistor logic level LVTTL, a low voltage differential signal LVDS, and an asynchronous transfer standard interface RS232 standard level.
The embodiment of the application provides a chip testing system, which comprises: a programmable logic device; the programmable logic device includes: the device comprises a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module, wherein the universal bus conversion module is used for realizing bus conversion between a chip test program loading interface and a universal bus main interface, and the chip test program loading interface is used for loading a chip test program. The universal bus interconnection module is used for realizing interconnection of the universal bus master interface and the plurality of universal bus slave interfaces. The first slave interface of the universal bus is connected with a universal bus decoding module, and the universal bus decoding module is used for connecting various interface bus modules. The at least one universal bus second slave interface is respectively connected with each logic module of the chip to be tested and used for testing each logic module of the chip to be tested. Therefore, interaction between various interface bus modules and logic modules of the chip to be tested can be realized, and switching among different modes is realized, so that the universality is improved, and the requirements of different scenes can be met.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a chip testing system according to an embodiment of the present application;
fig. 2 shows a schematic diagram of yet another chip testing system provided in an embodiment of the present application.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background art, a logic engineer often needs to perform some tasks of verifying feasibility in the early stage of a project, for example, verifying whether a certain analog-to-digital conversion (analog digital convert, ADC) chip meets requirements of project application, and when verifying, communication between an internal module and an external module of the chip and communication between all modules in the chip are required, however, different test platforms need to be built for different bus interfaces to perform testing in the present stage, so that the test platform has no universality, lower test efficiency and higher cost.
Specifically, at the present stage, the following three modes of constructing a test platform are mainly adopted:
(1) A bus interface card may be used to implement a corresponding function for a general purpose bus such as an asynchronous transfer standard interface RS232 or a general-purpose input/output (GPIO), but this mode cannot communicate with each logic module of the chip to be tested in the programmable logic device, and at the same time, this mode can only control the interface through an application programming interface (API, application programming interface) function provided by the bus interface card, which is less flexible.
(2) For the need of using serial peripheral interface (SPI, serial peripheral interface), internal integrated circuit (I) 2 C, inter-integrated circuit), the specific chip logic function module to be tested can be written by using hardware description languages such as Verilog or Very High speed integrated circuit hardware description language (VHDL, vera-High-Speed Integrated Circuit Hardware Description Language) so as to realize communication with the outside. The mode has strong flexibility, can realize the data interaction of the logic function module of the chip to be tested in the programmable logic device, but the logic function module realized by the mode can only be applied to a specific scene, has poor universality and has low code reusability; meanwhile, because hardware description languages such as Verilog/VHDL and the like have lower abstraction level, the development efficiency is low, the method is not suitable for application scenes with complex test functions, too much time and energy are occupied for developers to develop the functional modules for debugging, and the development period of projects is prolonged.
(3) The test excitation of external pulse, square wave or high-low level signals can be realized by using a standard signal source, standard signal source equipment generally provides USB or RS232 external interfaces, and the output of the signal source can be controlled through the external interfaces in a programming way so as to realize the automation of the test. But this approach also fails to communicate with the functional module under test inside the programmable logic device; meanwhile, the method has the defects of poor flexibility, high cost and the like.
In order to solve the above technical problems, the present application provides a chip test system, including: a programmable logic device; the programmable logic device includes: the device comprises a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module, wherein the universal bus conversion module is used for realizing bus conversion between a chip test program loading interface and a universal bus main interface, and the chip test program loading interface is used for loading a chip test program. The universal bus interconnection module is used for realizing interconnection of the universal bus master interface and the plurality of universal bus slave interfaces. The first slave interface of the universal bus is connected with a universal bus decoding module, and the universal bus decoding module is used for connecting various interface bus modules. The at least one universal bus second slave interface is respectively connected with each logic module of the chip to be tested and used for testing each logic module of the chip to be tested. Therefore, interaction between various interface bus modules and logic modules of the chip to be tested can be realized, and switching among different modes is realized, so that the universality is improved, and the requirements of different scenes can be met.
For a better understanding of the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a schematic diagram of a chip testing system according to an embodiment of the present application is shown.
In this embodiment, a test program needs to be loaded to test each logic module 17 of the chip to be tested, and the chip test program can be loaded into the programmable logic device 1 through the chip test program loading interface 10 of the programmable logic device 1 for subsequent call.
Specifically, the chip test program loading interface 10 may be connected to a computer, and the chip test program loading interface 10 may be a joint test effort group interface (JTAG, joint Test Action Group), which is an international standard test protocol mainly used for testing inside the chip. The JTAG interface is connected to the computer through the emulator so that the chip test program can be loaded from the computer.
The chip test program can be a tool command language (TCL, tool command language) script program, and the use of the TCL script program can complete a test flow with higher level of abstraction, including completing test excitation, reading the current state of a logic module of a chip to be tested, recording test results and the like, so that the test efficiency and development efficiency can be improved, and meanwhile, the TCL script program can conveniently call library functions mature in other languages, and can conveniently bond different functional modules together as a glue language to complete automatic test, thereby improving the test efficiency.
The programmable logic device 1 provided in the embodiment of the application includes: a universal bus conversion module 11, a universal bus interconnect module 13, and a universal bus decoding module 15.
Since the bus formats of the chip test program loading interface 10 and the universal bus main interface 12 are inconsistent, it is necessary to use the universal bus conversion module 11, one end of which is connected to the chip test program loading interface 10 and the other end of which is connected to the universal bus main interface 12, so that bus conversion between the chip test program loading interface 10 and the universal bus main interface 12 can be realized.
Specifically, the universal bus main interface 12 may be an advanced extensible interface (AXI, advanced extensible interface) main interface, and because the AXI bus is an interface bus with very strong universality, is an on-chip bus facing high performance, high bandwidth and low latency, and can interact with various interface bus modules and various logic modules of a chip to be tested, so the universal bus conversion module 11 may be a joint test workgroup interface to advanced extensible interface (JTAG to AXI, joint Test Action Group to advanced extensible interface) module, and the JTAG to AXI module is a user customizable intellectual property (IP, intellectual property) core, which is a pre-designed circuit function module, capable of performing AXI transmission inside a programmable device, driving AXI signals, and implementing bus conversion from a JTAG interface to an AXI interface.
In an alternative implementation manner, the universal bus conversion module 11 may also be a soft core MicroBlaze of Xilinx, where the chip test program is a C program, and running the C program in the soft core may also complete the same function as the TCL script program, but this has the disadvantage that the software program can only use the C standard library supported by MicroBlaze to complete the corresponding test function, and TCL as a script language may conveniently call a mature library function of multiple languages, which is significantly better than the C language in terms of development efficiency.
After the bus conversion is completed, in order to enable the universal bus to connect more modules, the universal bus interconnect module 13 may be utilized to enable interconnection of the universal bus master interface 12 with a plurality of universal bus slave interfaces, specifically, one end of the universal bus interconnect module 13 may be connected to the universal bus master interface 12, and the other end may be connected to the universal bus first slave interface 14 and at least one universal bus second slave interface 16, respectively, and in one possible implementation, the universal bus second slave interface 16 may include two: the second universal bus slave interface 161 and the second universal bus slave interface 162 are used to connect different chip logic modules 17 to be tested, which may include the chip logic module 171 to be tested, the chip logic module 172 to be tested, and so on according to different functions.
In one possible implementation, the universal bus slave interface may be an advanced extensible interface AXI slave interface, and the universal bus Interconnect module 13 may be an advanced extensible interface Interconnect AXI Interconnect module, which is an Xilinx self-contained IP core, and may implement interconnection between one AXI master interface and multiple AXI slave interfaces.
The universal bus first slave interface 14 may be connected to a universal bus decoding module 15, and the universal bus decoding module 15 is used to connect to various interface bus modules 18, and the interface bus modules 18 may include an interface bus module 181, an interface bus module 182, and so on, according to the types of interfaces.
Alternatively, the universal bus decoding module 15 may be an advanced extensible interface decoding AXI decoder module, which is an IP core of the Xilinx, so as to convert the read-write operation of the AXI into the operation of each interface module, where the module may be implemented by a high level integration (HLS, high level synthesis) tool of the Xilinx, so as to further improve the development efficiency.
Optionally, the plurality of interface bus modules includes: at least two of a serial peripheral interface SPI module, an internal integrated circuit I2C module, a general purpose input/output port GPIO module, a universal asynchronous receiver transmitter (UART, universal asynchronous receiver/transmitter) module, and a PULSE module. The SPI module can realize the read-write operation of an SPI interface, the I2C module can realize the read-write operation of the I2C interface, the GPIO module can realize the input-output operation of a general IO interface, the UART module can realize the read-write operation of a general serial bus and the output of various PULSEs can be realized by the PULSE module, so that the interaction between the bus modules of various interfaces and each logic module of the chip to be tested can be realized, the switching among different modes is realized, the universality is improved, and the requirements of different scenes can be met.
In one possible implementation, referring to fig. 2, the system further includes: an input/output buffer 19 of a plurality of level formats; the input output buffer 19 may include an input output buffer 191, an input output buffer 192, and the like according to the difference in level format.
One end of the input/output buffer 19 with various level formats is connected with the programmable logic device 1; the other ends of the input/output buffers 19 with multiple level formats are respectively connected with an electrical interface of an external device, and are used for converting the multiple level formats into the level formats of the programmable logic device.
Optionally, the plurality of level formats includes: at least two of a 5V transistor logic level (TTL, transistor transistor logic), a 3.3V low voltage transistor logic level (LVTTL, low voltage transistor transistor logic), a 2.5V low voltage transistor logic level LVTTL, a 1.8V low voltage transistor logic level LVTTL, a low voltage differential signal (LVDS, low-voltage differential signaling), and an asynchronous transfer standard interface RS232 standard level. Therefore, the connector can be connected with various level interfaces of external equipment, and the universality in hardware is enhanced.
Optionally, the programmable logic device 1 provided in the embodiment of the present application may be a field programmable gate array (FPGA, field programmable gate Array), and may also be other programmable logic devices, for example, a programmable array logic (PAL, programmable array logic), a generic array logic (GAL, generic array logic), and the like, where the programmable logic device 1 in the embodiment of the present application is an FPGA, and may specifically be XC7K325T of Xilinx.
The embodiment of the application provides a chip testing system, which comprises: a programmable logic device; the programmable logic device includes: the device comprises a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module, wherein the universal bus conversion module is used for realizing bus conversion between a chip test program loading interface and a universal bus main interface, and the chip test program loading interface is used for loading a chip test program. The universal bus interconnection module is used for realizing interconnection of the universal bus master interface and the plurality of universal bus slave interfaces. The first slave interface of the universal bus is connected with a universal bus decoding module, and the universal bus decoding module is used for connecting various interface bus modules. The at least one universal bus second slave interface is respectively connected with each logic module of the chip to be tested and used for testing each logic module of the chip to be tested. Therefore, interaction between various interface bus modules and logic modules of the chip to be tested can be realized, and switching among different modes is realized, so that the universality is improved, and the requirements of different scenes can be met.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for device embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see the section of the method embodiments.
The foregoing is merely a preferred embodiment of the present application, and although the present application has been disclosed in the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art may make many possible variations and modifications to the technical solution of the present application, or modify equivalent embodiments, using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application, which do not depart from the content of the technical solution of the present application, still fall within the scope of the technical solution of the present application.

Claims (10)

1. A chip test system comprising a programmable logic device; the programmable logic device includes: the device comprises a universal bus conversion module, a universal bus interconnection module and a universal bus decoding module;
one end of the universal bus conversion module is connected with the chip test program loading interface, and the other end of the universal bus conversion module is connected with the universal bus main interface and is used for realizing bus conversion between the chip test program loading interface and the universal bus main interface; the chip test program loading interface is used for loading a chip test program;
one end of the universal bus interconnection module is connected with the universal bus master interface, and the other end of the universal bus interconnection module is respectively connected with the universal bus first slave interface and at least one universal bus second slave interface, so that the universal bus master interface is interconnected with a plurality of universal bus slave interfaces;
the first slave interface of the universal bus is connected with the universal bus decoding module; the universal bus decoding module is used for connecting various interface bus modules;
the at least one universal bus second slave interface is respectively connected with each logic module of the chip to be tested and used for testing each logic module of the chip to be tested.
2. The system of claim 1, wherein the system further comprises: input/output buffers of various level formats;
one end of the input/output buffer with the multiple level formats is connected with the programmable logic device; and the other ends of the input and output buffers with the multiple level formats are respectively connected with an electrical interface of external equipment and are used for converting the multiple level formats into the level formats of the programmable logic device.
3. The system of claim 2, wherein the chip test program comprises: tool command language TCL script program.
4. The system of claim 1, wherein the universal bus conversion module comprises:
the joint test workgroup interfaces to the advanced extensible interface JTAG to AXI module, or MicroBlaze soft cores.
5. The system according to claim 4, comprising: when the universal bus conversion module is the MicroBlaze soft core, the chip test program is a C program.
6. The system of any of claims 1-5, wherein the programmable logic device comprises: the Field Programmable Gate Array (FPGA).
7. The system of any of claims 1-5, wherein the universal bus interconnect module comprises: the advanced extensible interface interconnects the AXI Interconnect modules.
8. The system of any of claims 1-5, wherein the universal bus decoding module comprises: the advanced extensible interface decodes the AXI decoder module.
9. The system of any of claims 1-5, wherein the plurality of interface bus modules comprises: SPI module and internal integrated circuit I 2 At least two of a C module, a general purpose input/output port GPIO module, a universal asynchronous receiver transmitter UART module and a PULSE module.
10. The system of any of claims 1-5, wherein the plurality of level formats comprises: at least two of a 5V transistor logic level TTL, a 3.3V low voltage transistor logic level LVTTL, a 2.5V low voltage transistor logic level LVTTL, a 1.8V low voltage transistor logic level LVTTL, a low voltage differential signal LVDS, and an asynchronous transfer standard interface RS232 standard level.
CN202111357484.1A 2021-11-16 2021-11-16 Chip test system Pending CN116136566A (en)

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Application Number Priority Date Filing Date Title
CN202111357484.1A CN116136566A (en) 2021-11-16 2021-11-16 Chip test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111357484.1A CN116136566A (en) 2021-11-16 2021-11-16 Chip test system

Publications (1)

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CN116136566A true CN116136566A (en) 2023-05-19

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