CN100435110C - Debugging device for on-chip system - Google Patents
Debugging device for on-chip system Download PDFInfo
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- CN100435110C CN100435110C CNB2004100845983A CN200410084598A CN100435110C CN 100435110 C CN100435110 C CN 100435110C CN B2004100845983 A CNB2004100845983 A CN B2004100845983A CN 200410084598 A CN200410084598 A CN 200410084598A CN 100435110 C CN100435110 C CN 100435110C
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Abstract
The present invention provides an on-chip debugger suitable for a high-speed video image processing SoC. In the on-chip debugger, a USB1.1 or a USB2.0 is used as an external port and connected with a USB interface of a debugging host, and thereby, the present invention can reach the data transmission speed of 400 M bits per second and satisfy the requirements of the video image processing SoC. The USB circuit part (called a USB core) of the on-chip debugger can be integrated in the SoC and can also be placed outside the SoC.
Description
Technical field
The present invention relates to a kind of sheet debugging device of SOC (system on a chip), relate in particular to a kind of sheet debugging device that uses USB interface.
Background technology
Integrated circuit (IC) chip can be divided into 4 classes: mimic channel sclerosis logical circuit (Hard-wired Logic) and 4 storer (Memory), 3 1) CPU, 2))).In past 20 years, the not only constantly development on each comfortable complicacy and the scale of this 4 class chip, and interpenetrate and combination, so that so-called SOC (system on a chip) (SoC:System-On-Chip) has appearred at the turn of the century.The feature of SoC is exactly that single-chip contains this 4 class circuit of CPU, storer, sclerosis logical circuit and mimic channel, has complete systemic-function.
An embedded type CPU is all arranged in the SoC, and CPU must have the software (instruction by CPU is formed) that moves to work on it, so CPU goes up the exploitation of the software that moves and the indispensable link that debugging is the SoC development and application.For the exploitation and the debugging of the software that carries out the SoC embedded type CPU effectively, SoC has a sheet debugging device (OCD:On-Chip-Debugger).OCD can control the operation of other modules in CPU and the SoC one by one with instructing, and gives an outer debug host of SoC the running status of other modules in CPU and the SoC (as the content of RS) by an external-connected port.OCD also can download to software program compiled on the debug host on the SoC by this external port.
At present the prior art of disclosed OCD all is that parallel port (parallel port) by boundary scan testing normal structure (JTAG:Joint Test Action Group) serial port (serial port), personal computer links to each other with debug host with the such external-connected port of Ethernet (Ethernet) interface.Fig. 1 has shown a kind of last debug system like this that constitutes according to present prior art.Wherein debug host 106 includes debugging software 107 and parallel port 108.And SoC single-chip 101 to be debugged comprises embedded type CPU, sheet debugging device (OCD) 103 and jtag port 104.Debug host 106 and SoC single-chip 101 interconnect by JTAG-parallel port conversion equipment 105.
The technical scheme of debug system and Fig. 1 is similar on the sheet shown in Figure 2.Difference is that the 108 usefulness Ethernet interfaces 208 of the parallel port in the debug host 106 substitute among Fig. 1, and JTAG-parallel port conversion equipment 105 correspondingly replaces to JTAG-Ethernet interface conversion equipment 205.
Comprise with the relevant patent and the product of these prior aries:
1) U.S. Advanced Micro Devices, the Parallel and serial debug port on aprocessor (United States Patent (USP) the 6th, 041, No. 406) of Inc. company.
2) U.S. Advanced Micro Devices, the Debug interface including operatingsystem access of a serial/parallel debug port (United States Patent (USP) the 5th, 978, No. 902) of Inc. company.
3) product Wiggler, Raven, the mpDemon of U.S. Macraigor company.
In the existing OCD technology that adopts the parallel port interface, owing to be subjected to the speed limit of parallel port, make the highest degree that can only reach several megabits of per second of data transmission between SoC chip and the debug host, far away can not the adaptive video image processing with the requirement (per second hundreds of megabit) of SoC chip.Though adopt existing its data rate of OCD technology of Ethernet interface higher than the speed of parallel port, but also can only reach the degree of per second tens megabits, still can not the adaptive video image processing with the requirement of SoC chip, and Ethernet interface, particularly the price of Fast Ethernet interface is very high.
Summary of the invention
At above problem, the present invention proposes a kind of sheet debugging device that on-chip system chip is debugged of being used for, comprise: sheet debugging device nuclear, when the CPU of described chip is operated in debugging mode following time, described debugging device nuclear is controlled the operation of described CPU in instruction ground one by one, and sends the running state data of other modules in described CPU and the described chip; Wherein, described debugging device also comprises: USB nuclear, described USB stone grafting are received the described running state data that described debugging device nuclear is sent, and send described running state data with the usb data form; Two-way FIFO (first-in-first-out) impact damper, described FIFO are used for the data transmission of synchronous described USB nuclear between examining with described debugging device; USB physics transceiver, described physics transceiver are finished conversion, the conversion from USB internal digital signal to the USB external analog signal from the USB external analog signal to USB internal digital signal, and the recovery of USB clock signal; The USB line, the input and output USB simulating signal of described USB physics transceiver is connected with the USB interface of external debug main frame via described USB line.
The invention allows for a kind of be used to contain embedded type CPU and the chip design of other circuit and the debug system of debugging, comprising: the debug host that debugging software and connectivity port are installed; By the chip to be debugged that line is connected with described debug host, wherein, described chip comprises aforesaid debugging device.
Since adopted message transmission rate higher and cheaply USB port carry out data transmission, therefore can satisfy video image and handle, and can reduce the cost of debug system with the needs of SoC chip to high speed data transfers.
Description of drawings
By below in conjunction with the detailed description that accompanying drawing carried out, those of ordinary skills will be more readily apparent from features, objects and advantages of the invention.Wherein, appended diagrammatic sketch comprises:
Fig. 1 is the synoptic diagram of a kind of technical scheme of debug system on the SoC sheet in the prior art;
Fig. 2 is the synoptic diagram of the another kind of technical scheme of debug system on the SoC sheet in the prior art;
Fig. 3 is the synoptic diagram according to a kind of technical scheme of debug system on the SoC sheet of the present invention;
Fig. 4 has shown the shown in Figure 3 SoC sheet debugging device of going up debug system that be applied to according to first embodiment of the invention;
Fig. 5 has shown the shown in Figure 3 SoC sheet debugging device of going up debug system that be applied to according to second embodiment of the invention;
Fig. 6 has shown that a third embodiment in accordance with the invention is applied to the shown in Figure 3 SoC sheet debugging device of going up debug system;
Embodiment
Fig. 3 has shown an embodiment of debug system on the sheet that constitutes according to the present invention.Except replaced parallel port 108 among Fig. 1 and the Ethernet interface 208 among Fig. 2 with usb host (USB host) 308, with the USB nuclear 304 JTAG modules that replaced among Fig. 1 and Fig. 2, the technical scheme of other and Fig. 1 and Fig. 2 is similar.
The sheet debugging device of whole SoC is made up of 5 parts:
1.OCD examine 103;
2. two-way FIFO (first-in-first-out) impact damper 302
3.USB examine 304;
4.USB physics transceiver 303;
5.USB line 305.
Actual needs according to SoC, USB endorses to be placed on SoC inside, also can be placed on the SoC outside, USB physics transceiver can be placed on SoC inside, also can be placed on the SoC outside, USB nuclear, USB physics transceiver and USB line can be the special uses of sheet debugging device, also can except being used for the sheet debugging device, other purposes also be arranged, as SoC and other peripherals are coupled together.
Fig. 4 has shown that further first embodiment of sheet debugging device constitutes calcspar among Fig. 3.
Wherein, when CPU is operated in debugging mode following time, OCD nuclear 103 one by one instruction ground control CPU operation, and the running status of other modules in CPU and the SoC (as the content of RS) passed to USB end points (endpoints).Though only shown two USB end points 402,403 among the figure, but as those of ordinary skills can understand, also can be provided with more than two USB end points, wherein at least one USB end points is input (IN) end points, and at least one USB end points is output (OUT) end points.These USB end points 402, USB end points 403 directly link to each other with a unidirectional fifo buffer 406,407 respectively, and these impact dampers are used for data transmission is cushioned between OCD nuclear 103 and USB Parts Controller 404 (USB devicecontroller) and to data.
USB Parts Controller (USB device controller) 404 is according to the Bulk or the Isochronous pattern of usb protocol, the transmission of control data.The USB Parts Controller needs in strict accordance with the USB modular working, is the module of a standard.
USB information ROM408 (Read-Only-Memory is a ROM (read-only memory)) is used to store the descriptor of this USB device.The descriptor of equipment has write down some general informations of USB device and the configuration information of end points, extracts during for the device request of USB Parts Controller response main frame, gives main frame then, can discern this USB device to guarantee main frame.The descriptor of equipment comprises configuration descriptor, interface descriptor, endpoint descriptor.The endpoint configurations that endpoint descriptor is described is as follows:
| Endpoint number | Transmission mode | Packet size (Byte) | |
| 1 | BULK IN | 4 | The sheet debugging device send data to debug |
| 2 | ISO OUT | 512 | Debug host is sent data to the sheet debugging device |
Table 1
USB transceiver 405 (USB transceiver) has reception and sends two functions:
1) receives USB serial data signal, serial signal is carried out the NRZI Gray code, after going here and there then and changing, become the parallel signal of 8bit, deliver to USB Parts Controller 404 from the outside.
2) parallel signal from the 8bit of USB Parts Controller 404 is converted to serial signal, carry out nrzi encoding again after, send to the outside.
It has certain driving force, can finish the reception and the transmission of usb data under the USB frequency of operation.Sheet debugging device and debug host 106 are connected by USB line 305.Described USB line 305 preferred length are 1-3 rice.Certainly, also can adopt longer or shorter USB line 305 according to practical application.
In one embodiment, all be integrated into SoC inside with upper-part.
Fig. 5 has shown that further second embodiment of sheet debugging device constitutes calcspar among Fig. 3.
For simplicity's sake, below will omit among Fig. 5 description with Fig. 4 same parts.Different is between OCD nuclear 103 and USB end points 402,403, to have increased jtag circuit 502 and JTAG-USB signal form change-over circuit 503 with first embodiment shown in Figure 4.The OCD nuclear 103 here has and the first embodiment identical functions, but it can link to each other with traditional jtag interface.And jtag circuit 502 can be according to the transmission of JTAG agreement control data.503 of JTAG-USB signal form change-over circuits can convert the JTAG data mode to the usb data form, perhaps the usb data formal transformation are become the JTAG data mode.
In one embodiment, above OCD nuclear 103 is integrated into SoC inside with jtag circuit 502 parts, and other parts are then formed an independently unit.
Embodiment 3
Fig. 6 has shown that further the 3rd embodiment of sheet debugging device constitutes calcspar among Fig. 3.
For simplicity's sake, below will omit among Fig. 6 description with Fig. 4 same parts.Different is with first embodiment shown in Figure 4, except have with the first embodiment identical functions, the USB Parts Controller 404 here also is responsible for the USB end points outside the sheet debugging device as USB end points 607, is controlled.And such USB end points 607 is connected with other processing element of waiting to debug in the chip 101 by SoC internal bus 610, as video processor 609 and audio process 608.In the present embodiment, the endpoint configurations that endpoint descriptor is described is as follows:
| Endpoint number | Transmission mode | Packet size (Byte) | |
| 1 | BULK IN | 4 | The sheet debugging device send data to debug |
| 2 | ISO OUT | 512 | Debug host is sent data to the sheet debugging device |
| 3 | ISO IN | 512 | Audio process send data to debug host |
| 4 | ISO OUT | 512 | Debug host is sent data to audio process |
| 5 | ISO IN | 512 | Video processor send data to debug host |
| 6 | ISO OUT | 512 | Debug host is sent data to video processor |
Table 2
In one embodiment, all be integrated into SoC inside with upper-part.USB end points in this embodiment not only plays the effect of high-speed data channel in the sheet debugging device, and the non-debugging of performance for example couples together various devices and the chip of the every other part among the SoC (as video processor, audio process) with the SoC outside with the effect of high speed input and output in this SoC.
Claims (8)
1. one kind is used for sheet debugging device that on-chip system chip is debugged, comprising:
Sheet debugging device nuclear, when the CPU of described chip is operated in debugging mode following time, the described debugging device nuclear operation of the described CPU of instruction ground control one by one, and send the running state data of described CPU;
It is characterized in that described debugging device also comprises:
USB nuclear, described USB stone grafting are received the described running state data that described debugging device nuclear is sent, and send described running state data with the usb data form;
Two-way fifo buffer, described fifo buffer are used for the data transmission of synchronous described USB nuclear between examining with described debugging device;
Be connected to the USB physics transceiver of described USB nuclear, described USB physics transceiver is finished conversion, the conversion from USB internal digital signal to the USB external analog signal from the USB external analog signal to USB internal digital signal, and the recovery of USB clock signal;
The USB line, the input and output USB simulating signal of described USB physics transceiver is connected with the USB interface of external debug main frame via described USB line.
2. a debugging device as claimed in claim 1 is characterized in that, described USB nuclear further comprises:
With described debugging device nuclear phase at least two USB end points even,
At least two unidirectional fifo buffers that are connected with described at least two USB end points respectively, described unidirectional fifo buffer are used for data transmission is cushioned between described debugging device nuclear and described USB end points and to data;
Be connected to the USB Parts Controller of all described USB end points, be used for reportedly being input into row control according to the data transmittal and routing form logarithm of usb protocol;
Be connected to the USB transceiver of described USB Parts Controller, be used under the USB frequency of operation, finish the reception and the transmission of usb data;
Be connected to the USB information ROM of described USB Parts Controller, be used to store the descriptor of USB device.
3. a debugging device as claimed in claim 1 is characterized in that, described USB nuclear further comprises:
Jtag circuit with described debugging device nuclear phase connects is used for the transmission according to JTAG agreement control data;
The JTAG-USB signal form change-over circuit that links to each other with described jtag circuit is used for the JTAG data mode is converted to the usb data form or the usb data formal transformation is become the JTAG data mode;
At least two USB end points that link to each other with described JTAG-USB signal form change-over circuit;
At least two unidirectional fifo buffers that are connected with described at least two USB end points respectively, described unidirectional fifo buffer are used for data transmission is cushioned between described debugging device nuclear and described USB end points and to data;
Be connected to the USB Parts Controller of all described USB end points, be used for reportedly being input into row control according to the data transmittal and routing form logarithm of usb protocol;
Be connected to the USB transceiver of described USB Parts Controller, be used under the USB frequency of operation, finish the reception and the transmission of usb data,
Be connected to the USB information ROM of described USB Parts Controller, be used to store the descriptor of USB device.
4. a debugging device as claimed in claim 2 is characterized in that, described USB Parts Controller is also controlled the outer USB end points of described USB nuclear.
5. as claim 2 or 3 described debugging devices, it is characterized in that described USB information ROM is used to store the descriptor of the USB device that comprises configuration descriptor, interface descriptor, endpoint descriptor.
6. as each described debugging device among the claim 2-4, it is characterized in that described USB Parts Controller reportedly is input into row control according to the Bulk pattern logarithm of usb protocol.
7. as each described debugging device among the claim 2-4, it is characterized in that described USB Parts Controller reportedly is input into row control according to the Isochronous pattern logarithm of usb protocol.
8. debug system that is used to contain the chip design and the debugging of embedded type CPU comprises:
The debug host of debugging software and connectivity port is installed;
The chip to be debugged that is connected with described debug host by line,
It is characterized in that described chip comprises as each described debugging device among the claim 1-4.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100845983A CN100435110C (en) | 2004-11-26 | 2004-11-26 | Debugging device for on-chip system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100845983A CN100435110C (en) | 2004-11-26 | 2004-11-26 | Debugging device for on-chip system |
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| CN100435110C true CN100435110C (en) | 2008-11-19 |
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| CNB2004100845983A Expired - Fee Related CN100435110C (en) | 2004-11-26 | 2004-11-26 | Debugging device for on-chip system |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236067B (en) * | 2010-04-22 | 2015-07-01 | 上海华虹集成电路有限责任公司 | Method for realizing rapid debugging and locating of chip functional fault and debugging circuit used in same |
| CN102411535B (en) * | 2011-08-02 | 2014-04-16 | 上海交通大学 | Navigating-SoC (System On Chip) simulating, verifying and debugging platform |
| CN103226506B (en) * | 2013-04-28 | 2015-04-22 | 杭州士兰微电子股份有限公司 | Chip-embedded USB to JTAG debugging device and debugging method |
| US9684578B2 (en) * | 2014-10-30 | 2017-06-20 | Qualcomm Incorporated | Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems |
| CN105550118B (en) * | 2016-01-27 | 2018-01-30 | 珠海格力电器股份有限公司 | Debugging system and adjustment method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020059542A1 (en) * | 2000-10-18 | 2002-05-16 | Anthony Debling | On-chip emulator communication |
| CN1529249A (en) * | 2003-10-17 | 2004-09-15 | 清华大学 | USB-based multi-parameter data obtaining system |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020059542A1 (en) * | 2000-10-18 | 2002-05-16 | Anthony Debling | On-chip emulator communication |
| CN1529249A (en) * | 2003-10-17 | 2004-09-15 | 清华大学 | USB-based multi-parameter data obtaining system |
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