CN116132266A

CN116132266A - Method, system, storage medium and equipment for keeping BMC network stable

Info

Publication number: CN116132266A
Application number: CN202310183014.0A
Authority: CN
Inventors: 杜洪斌; 刘宝阳
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-02-24
Filing date: 2023-02-24
Publication date: 2023-05-16

Abstract

The invention provides a method, a system, a storage medium and equipment for keeping a BMC network stable, wherein the method comprises the following steps: responding to BMC start, controlling the special network port to be connected with the first PHY chip and the second PHY chip in sequence so as to initialize the first PHY chip and the second PHY chip; responding to the initialization completion, and sending a heartbeat message to a first PHY chip currently connected with the special network port through the BMC so as to judge the running state of the first PHY chip; responding to abnormal operation of the first PHY chip, controlling the private network port to be switched and connected to the second PHY chip through the BMC, and sending a heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip; and responding to the normal operation of the second PHY chip, and transmitting and receiving data by the BMC through the second PHY chip. According to the invention, through the redundant design of the dual PHY chips of the BMC special network port, the stability and the speed of the BMC network can be ensured, and the remote management function of the server is further effectively ensured.

Description

Method, system, storage medium and equipment for keeping BMC network stable

Technical Field

The present invention relates to the field of server technologies, and in particular, to a method, a system, a storage medium, and a device for maintaining stability of a BMC network.

Background

With the rapid development of internet and cloud computing in recent years, the demands for servers are increasing, the number of servers is increasing, and the demands for remote management of servers are also increasing. Remote management, as the name implies, does not require engineers to directly operate the server, but rather performs related server maintenance work through the network, so that the requirement on the stability of the management network is also higher and higher.

The network link of the BMC (Baseboard Management Controller ) system generally includes two network ports: the network interface comprises a special network port and a shared network port, wherein the special network port is a gigabit network port, the shared network port uses NCSI (Network Controller Sideband Interface ), and the protocol is an industry standard of sideband interface network controllers which are defined by a distributed management task group and used for supporting server out-of-band management, and only supports hundred megarates at maximum.

The private network interface link is from a BMC control chip to a PHY (Physical port Physical layer, which is commonly referred to as an OSI model Physical layer) chip, and then to an RJ45 (optical/electrical module interface, which is referred to as a standard 8-bit modularized interface in a computer network).

The shared network port is to send network message through network card of the server host system by NCSI interface, if the PHY chip of the special network port is abnormal, the special network port cannot be used, the shared network port needs to be switched, and the operation of accessing web by using the shared network port has little influence. However, when the BMC network port is operated under a large network pressure, which has a high requirement on the network port rate, an abnormal packet loss problem may occur. For example, a KVM (Keyboard Video Mouse, KVM, which is capable of accessing and controlling a computer by directly connecting to a keyboard, video or mouse port) installation system often used in remote management requires that an image file is firstly installed in a BMC and then the image content is read through a network to perform system installation. Thus, a dedicated portal is still needed to guarantee the rate and stability of the BMC network.

Disclosure of Invention

Therefore, the invention aims to provide a method, a system, a storage medium and equipment for keeping a BMC network stable, which are used for solving the problem that the running abnormality of a PHY chip of a special network port of the BMC in the prior art affects the stability of the BMC network.

Based on the above object, the present invention provides a method for keeping a BMC network stable, comprising the following steps:

responding to BMC start, controlling the special network port to be connected with the first PHY chip and the second PHY chip in sequence so as to initialize the first PHY chip and the second PHY chip;

responding to the initialization completion, and sending a heartbeat message to a first PHY chip currently connected with the special network port through the BMC so as to judge the running state of the first PHY chip;

responding to abnormal operation of the first PHY chip, controlling the private network port to be switched and connected to the second PHY chip through the BMC, and sending a heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip;

and responding to the normal operation of the second PHY chip, and transmitting and receiving data by the BMC through the second PHY chip.

In some embodiments, controlling the dedicated network port to connect with the first PHY chip and the second PHY chip in sequence to initialize the first PHY chip and the second PHY chip includes:

responding to BMC start, initializing a first PHY chip connected with a special network port;

and responding to the completion of the initialization of the first PHY chip, sending a switching command to the CPLD through the BMC so as to enable the special network port to be switched and connected to the second PHY chip, and initializing the second PHY chip.

In some embodiments, sending a switch command to the CPLD by the BMC to cause the dedicated portal to switch connection to the second PHY chip includes:

sending a switching command to the CPLD through the BMC;

and responding to the CPLD receiving the switching command, and connecting the special network port to the second PHY chip by the control logic chip.

In some embodiments, the method further comprises:

connecting the special network port with a first PHY chip through a first logic chip;

and connecting the special network port with the second PHY chip through the second logic chip.

In some embodiments, determining the operational status of the first PHY chip includes:

and judging the running state of the first PHY chip based on the response result of the first PHY chip to the heartbeat message.

In some embodiments, sending, by the BMC, a heartbeat message to a first PHY chip currently connected to the dedicated network port, to determine an operation state of the first PHY chip includes:

sending a heartbeat message to a first PHY chip currently connected with the special network port through the BMC, and waiting for a response message;

repeating the steps of sending the heartbeat message and waiting for the response message in response to the fact that the response message is not received within the preset time length;

and determining that the first PHY chip runs abnormally in response to the fact that the response message is not received after the repetition number reaches a preset threshold.

In some embodiments, determining the operational status of the second PHY chip includes:

and judging the running state of the second PHY chip based on the response result of the second PHY chip to the heartbeat message.

In another aspect of the present invention, there is also provided a system for maintaining stability of a BMC network, including:

the initialization module is configured to respond to BMC starting and control the special network port to be sequentially connected with the first PHY chip and the second PHY chip so as to initialize the first PHY chip and the second PHY chip;

the first judging module is configured to respond to the completion of initialization, and send a heartbeat message to a first PHY chip currently connected with the special network port through the BMC so as to judge the running state of the first PHY chip;

the second judging module is configured to respond to abnormal operation of the first PHY chip, control the private network port to be switched and connected to the second PHY chip through the BMC, and send a heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip; and

and the data transceiving module is configured to respond to the normal operation of the second PHY chip, and the BMC performs data transceiving through the second PHY chip.

In yet another aspect of the present invention, there is also provided a computer readable storage medium storing computer program instructions which, when executed by a processor, implement the above-described method.

In yet another aspect of the present invention, there is also provided a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, performs the above method.

The invention has at least the following beneficial technical effects:

according to the method for keeping the BMC network stable, through the redundant design of the dual PHY chips of the BMC special network port, the first PHY chip and the second PHY chip are used as the main chip and the standby chip respectively, so that the stability of the BMC network can be ensured; the running state of the PHY chip is detected by sending a heartbeat message to the PHY chip, so that whether the PHY chip is normal or not can be simply and accurately judged; the speed of the BMC network is ensured by automatically judging that the connected PHY chip is abnormal and then identifying and switching to another PHY chip; further, the remote management function of the server is effectively guaranteed, and the speed and efficiency of the client remote management server are improved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a method for keeping a BMC network stable according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a method for implementing to keep a BMC network stable according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a system for keeping a BMC network stable according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a computer readable storage medium implementing a method of maintaining BMC network stability according to an embodiment of the present invention;

fig. 5 is a schematic hardware structure diagram of a computer device for executing a method for keeping a BMC network stable according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two non-identical entities with the same name or non-identical parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such as a process, method, system, article, or other step or unit that comprises a list of steps or units.

Based on the above objects, in a first aspect of the embodiments of the present invention, an embodiment of a method for keeping a BMC network stable is provided. Fig. 1 is a schematic diagram of an embodiment of a method for keeping a BMC network stable. As shown in fig. 1, the embodiment of the present invention includes the following steps:

step S10, responding to BMC start, controlling the special network port to be sequentially connected with the first PHY chip and the second PHY chip so as to initialize the first PHY chip and the second PHY chip;

step S20, responding to the completion of initialization, and sending a heartbeat message to a first PHY chip currently connected with the special network port through the BMC so as to judge the running state of the first PHY chip;

step S30, responding to abnormal operation of the first PHY chip, controlling the private network port to be switched and connected to the second PHY chip through the BMC, and sending a heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip;

and step S40, responding to the normal operation of the second PHY chip, and transmitting and receiving data by the BMC through the second PHY chip.

The embodiment of the invention does not limit the number of the spare PHY chips, and can be one or more spare PHY chips. The private network port can also be used for switching and connecting a plurality of standby PHY chips. For each standby PHY chip, the running state is detected by sending a heartbeat message to the standby PHY chip through the BMC.

In some embodiments, controlling the dedicated network port to connect with the first PHY chip and the second PHY chip in sequence to initialize the first PHY chip and the second PHY chip includes: responding to BMC start, initializing a first PHY chip connected with a special network port; and responding to the completion of the initialization of the first PHY chip, sending a switching command to the CPLD through the BMC so as to enable the special network port to be switched and connected to the second PHY chip, and initializing the second PHY chip.

In some embodiments, sending a switch command to the CPLD by the BMC to cause the dedicated portal to switch connection to the second PHY chip includes: sending a switching command to the CPLD through the BMC; and responding to the CPLD receiving the switching command, and connecting the special network port to the second PHY chip by the control logic chip.

In some embodiments, the method further comprises: connecting the special network port with a first PHY chip through a first logic chip; and connecting the special network port with the second PHY chip through the second logic chip.

In some embodiments, determining the operational status of the first PHY chip includes: and judging the running state of the first PHY chip based on the response result of the first PHY chip to the heartbeat message.

In some embodiments, sending, by the BMC, a heartbeat message to a first PHY chip currently connected to the dedicated network port, to determine an operation state of the first PHY chip includes: sending a heartbeat message to a first PHY chip currently connected with the special network port through the BMC, and waiting for a response message; repeating the steps of sending the heartbeat message and waiting for the response message in response to the fact that the response message is not received within the preset time length; and determining that the first PHY chip runs abnormally in response to the fact that the response message is not received after the repetition number reaches a preset threshold.

In some embodiments, determining the operational status of the second PHY chip includes: and judging the running state of the second PHY chip based on the response result of the second PHY chip to the heartbeat message.

Fig. 2 shows a schematic structural diagram of a method for implementing the method for keeping the BMC network stable. As shown in fig. 2, an exemplary embodiment of a method for keeping a BMC network stable according to the present invention is as follows:

the process of maintaining the stability of the BMC network through the dual PHY chip redundancy design of the BMC (Baseboard Management Controller) dedicated network port is mainly divided into 3 parts: the method comprises the steps of firstly initializing a PHY (Physical port Physical layer, which is commonly called as an OSI model Physical layer) chip when the BMC is powered on, secondly judging the running state of the PHY chip through the BMC, and thirdly switching to a standby PHY chip after the PHY chip runs abnormally.

1) The initialization process of PHY chip when BMC is powered on:

when the BMC is powered on and started, an initialization flow is firstly carried out on a connected PHY1 chip (namely a first PHY chip), after initialization is finished, a PHY chip switching command is sent to a CPLD (Complex Programmable Logic Device, a complex programmable logic device), the CPLD controls the logic chip, a BMC special network port is connected with a PHY2 chip (namely a second PHY chip), then the PHY initialization flow is restarted once, after two times of initialization are finished, the PHY1 chip is switched, and after the initialization is finished, the system defaults, the PHY1 chip is used for operation.

The logic chip comprises a logic chip 1 (namely a first logic chip) and a logic chip 2 (namely a second logic chip), wherein the logic chip 1 connects the special network port and the PHY1 chip, and the logic chip 2 connects the special network port and the PHY2 chip.

2) BMC judges PHY chip running state:

and the BMC sends the heartbeat message to the PHY1 chip to acquire the running state, waits for a response signal after sending the heartbeat message, repeatedly sends the heartbeat message if the response message is not acquired after the timeout, and judges that the PHY1 chip runs abnormally after the response message is not received after the timeout is continuously carried out three times.

3) After the PHY chip operates abnormally, switching to a standby PHY chip process:

after judging that the PHY1 chip runs abnormally, the BMC sends a PHY chip switching signal to the CPLD, and after the CPLD receives the signal, the CPLD sends a signal to the BMC after finishing the switching of PHY2 chip connection of the BMC special network port through the control logic chip; and the BMC sends a heartbeat message to confirm the link state of the PHY2 chip, if the BMC receives a response message of the PHY2 chip, the PHY2 chip is determined to be normal, and then data transmission and reception are carried out through the special network port and the PHY2 chip.

Thus, the present embodiment realizes: the special network port double PHY redundancy design of the BMC, the PHY connection fault is automatically judged, and the switching is automatically carried out after the PHY operation is abnormal; therefore, the stability of the BMC network is improved, the remote management function of the server is effectively guaranteed, and the speed and the efficiency of the client remote management server are improved.

In a second aspect of the embodiment of the present invention, a system for maintaining stability of a BMC network is also provided. Fig. 3 is a schematic diagram of an embodiment of a system for keeping a BMC network stable according to the present invention. As shown in fig. 3, a system for keeping a BMC network stable includes: an initialization module 10 configured to control, in response to a BMC start, the dedicated network port to be sequentially connected to the first PHY chip and the second PHY chip, so as to initialize the first PHY chip and the second PHY chip; the first judging module 20 is configured to send a heartbeat message to a first PHY chip currently connected to the private network port through the BMC in response to completion of initialization, so as to judge an operation state of the first PHY chip; the second judging module 30 is configured to respond to abnormal operation of the first PHY chip, control the dedicated network port to switch and connect to the second PHY chip through the BMC, and send a heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip; and a data transceiving module 40 configured to perform data transceiving through the second PHY chip in response to the second PHY chip operating normally.

According to the system for keeping the BMC network stable, disclosed by the embodiment of the invention, through the redundant design of the dual PHY chips of the BMC special network port, the first PHY chip and the second PHY chip are used as the main chip and the standby chip respectively, so that the stability of the BMC network can be ensured; the running state of the PHY chip is detected by sending a heartbeat message to the PHY chip, so that whether the PHY chip is normal or not can be simply and accurately judged; the speed of the BMC network is ensured by automatically judging that the connected PHY chip is abnormal and then identifying and switching to another PHY chip; further, the remote management function of the server is effectively guaranteed, and the speed and efficiency of the client remote management server are improved.

In some embodiments, the initialization module 10 is further configured to initialize a first PHY chip connected to the dedicated network port in response to BMC initiation; and responding to the completion of the initialization of the first PHY chip, sending a switching command to the CPLD through the BMC so as to enable the special network port to be switched and connected to the second PHY chip, and initializing the second PHY chip.

In some embodiments, the initialization module 10 includes a switch module configured to send a switch command to the CPLD via the BMC; and responding to the CPLD receiving the switching command, and connecting the special network port to the second PHY chip by the control logic chip.

In some embodiments, the system further comprises a logic chip connection module configured to connect the dedicated network port with the first PHY chip through the first logic chip; and connecting the special network port with the second PHY chip through the second logic chip.

In some embodiments, the first determining module 20 is further configured to determine an operation state of the first PHY chip based on a response result of the first PHY chip to the heartbeat message.

In some embodiments, the first judging module 20 is further configured to send, through the BMC, a heartbeat message to a first PHY chip currently connected to the dedicated network port, and wait for a response message; repeating the steps of sending the heartbeat message and waiting for the response message in response to the fact that the response message is not received within the preset time length; and determining that the first PHY chip runs abnormally in response to the fact that the response message is not received after the repetition number reaches a preset threshold.

In some embodiments, the second determining module 30 is further configured to determine an operation state of the second PHY chip based on a response result of the second PHY chip to the heartbeat message.

In a third aspect of the embodiments of the present invention, a computer readable storage medium is provided, and fig. 4 is a schematic diagram of a computer readable storage medium for implementing a method for keeping a BMC network stable according to an embodiment of the present invention. As shown in fig. 4, the computer-readable storage medium 3 stores computer program instructions 31. The computer program instructions 31 when executed by a processor implement the steps of:

In some embodiments, the steps further comprise: connecting the special network port with a first PHY chip through a first logic chip; and connecting the special network port with the second PHY chip through the second logic chip.

It should be appreciated that all of the embodiments, features and advantages set forth above for the method of maintaining BMC network stability according to the present invention apply equally to the system and storage medium of maintaining BMC network stability according to the present invention without conflicting with each other.

In a fourth aspect of the embodiment of the present invention, there is also provided a computer device, including a memory 402 and a processor 401 as shown in fig. 5, where the memory 402 stores a computer program, and the computer program is executed by the processor 401 to implement the method of any one of the embodiments above.

Fig. 5 is a schematic hardware structure diagram of an embodiment of a computer device for performing the method for keeping the BMC network stable according to the present invention. Taking the example of a computer device as shown in fig. 5, a processor 401 and a memory 402 are included in the computer device, and may further include: an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 may be connected by a bus or otherwise, for example in fig. 5. The input device 403 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the system that keeps the BMC network stable. The output 404 may include a display device such as a display screen.

The memory 402 is used as a non-volatile computer readable storage medium, and may be used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as program instructions/modules corresponding to the method for keeping the BMC network stable in the embodiments of the present application. Memory 402 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created using a method of keeping the BMC network stable, etc. In addition, memory 402 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory located remotely from processor 401, which may be connected to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The processor 401 executes various functional applications of the server and data processing by running nonvolatile software programs, instructions and modules stored in the memory 402, that is, implements the method for keeping the BMC network stable in the above method embodiment.

Finally, it should be noted that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of example, and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP and/or any other such configuration.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.

Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for maintaining stability of a BMC network, comprising the steps of:

responding to BMC start, controlling a special network port to be sequentially connected with a first PHY chip and a second PHY chip so as to initialize the first PHY chip and the second PHY chip;

responding to the completion of initialization, and sending a heartbeat message to a first PHY chip currently connected with the special network port through the BMC so as to judge the running state of the first PHY chip;

responding to abnormal operation of the first PHY chip, controlling the private network port to be switched and connected to the second PHY chip through the BMC, and sending the heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip;

and responding to the second PHY chip to normally operate, and transmitting and receiving data by the BMC through the second PHY chip.

2. The method of claim 1, wherein controlling the dedicated network port to connect with the first PHY chip and the second PHY chip in sequence to initialize the first PHY chip and the second PHY chip comprises:

and responding to the completion of the initialization of the first PHY chip, sending a switching command to the CPLD through the BMC so as to enable the special network port to be switched and connected to a second PHY chip, and initializing the second PHY chip.

3. The method of claim 2, wherein sending, by the BMC, a switch command to the CPLD to cause the dedicated portal to switch connection to the second PHY chip comprises:

sending a switching command to the CPLD through the BMC;

4. A method according to claim 3, further comprising:

the special network port is connected with the first PHY chip through a first logic chip;

5. The method of claim 1, wherein determining the operational status of the first PHY chip comprises:

6. The method of claim 1, wherein sending, by the BMC, a heartbeat message to a first PHY chip to which the dedicated network port is currently connected, to determine an operational state of the first PHY chip includes:

repeating the steps of sending the heartbeat message and waiting for the response message in response to the fact that the response message is not received within a preset time length;

and determining that the first PHY chip runs abnormally in response to the response message which is not received after the repetition times reach a preset threshold.

7. The method of claim 1, wherein determining the operational status of the second PHY chip comprises:

8. A system for maintaining a stable BMC network, comprising:

the second judging module is configured to respond to abnormal operation of the first PHY chip, control the private network port to be switched and connected to the second PHY chip through the BMC, and send the heartbeat message to the second PHY chip so as to judge the operation state of the second PHY chip; and

and the data receiving and transmitting module is configured to respond to the normal operation of the second PHY chip, and the BMC receives and transmits data through the second PHY chip.

9. A computer readable storage medium, characterized in that computer program instructions are stored, which, when executed by a processor, implement the method of any one of claims 1-7.

10. A computer device comprising a memory and a processor, wherein the memory has stored therein a computer program which, when executed by the processor, performs the method of any of claims 1-7.