CN116131830A

CN116131830A - MOS tube control circuit and LNA single-stage amplifying device

Info

Publication number: CN116131830A
Application number: CN202310402581.0A
Authority: CN
Inventors: 田新城
Original assignee: Core Microelectronics Kunshan Co ltd
Current assignee: Core Microelectronics Kunshan Co ltd
Priority date: 2023-04-17
Filing date: 2023-04-17
Publication date: 2023-05-16
Anticipated expiration: 2043-04-17
Also published as: CN116131830B

Abstract

The embodiment of the application provides a MOS tube control circuit and an LNA single-stage amplifying device. The control circuit includes: the capacitor C is connected with the grid electrode of the main circuit MOS tube, one end of the bias resistor R is connected with the grid electrode of the main circuit MOS tube MN, and the other end of the bias resistor R is connected with bias voltage; the voltage control type switch MP is connected in parallel with the bias resistor R; the level edge detection circuit is connected with the enable signal EN, and the output end of the level edge detection circuit is connected with the control end of the voltage control type switch MP; the level edge detection circuit is used for outputting a control signal to conduct the voltage control type switch MP for a preset time when detecting the preset edge of the enable signal EN, so that the bias resistor R is short-circuited for the preset time, and the potential of the grid electrode of the main circuit MOS tube is changed rapidly. The embodiment of the application solves the technical problem that the traditional charge-discharge structure formed by the capacitor C connected to the grid electrode of the MOS tube and the capacitor and the resistor causes the turn-off and turn-on of the MOS tube to require a long time.

Description

MOS tube control circuit and LNA single-stage amplifying device

Technical Field

The application relates to the technical field of radio frequency components, in particular to a MOS tube control circuit and an LNA single-stage amplifying device.

Background

The radio frequency switch and the LNA (low noise amplifier) are the most commonly used radio frequency components, are used for signal amplification, channel switching and receiving and transmitting state switching in a radio frequency link, and are widely applied to the fields of the Internet of things, communication base stations, small base stations, repeater stations, test instruments, radars, wiFi, RFID and the like. The radio frequency antenna switch is connected between the antenna and the radio frequency processing circuit and used for switching the working state of the antenna, switching the frequency band and receiving and transmitting signals. Through the switch, signals with different frequency bands and different systems can be separated and then output to different systems of the mobile phone for processing, so that mutual interference among different signals is reduced, signal receiving sensitivity is improved, the received signals can be amplified by the radio frequency LNA, influence of noise of a later-stage circuit is reduced, and the receiving sensitivity of the system is improved. The radio frequency switch and the LNA are essential key devices of the radio frequency front end of the mobile phone, and the quality of the performance directly determines the signal quality of the mobile phone terminal. The bias voltage of the switch or the LNA is usually provided through a resistor with a large resistance value to reduce the influence of the bias circuit on the radio frequency performance, but the bias resistor, the parasitic capacitance of the transistor or the blocking capacitance, the filter capacitance and other capacitances form an RC charge-discharge structure, the charge-discharge time is long, and the bias voltage becomes one of the main factors for prolonging the switching time. In some applications of radio frequency systems (such as wifi systems), there is sometimes a high requirement on the switching time of the switch and the LNA, and it is desirable to shorten the switching time of the LNA or the switch as much as possible. Therefore, some measures are required to reduce the switching time and accelerate the switching process of the circuit.

Fig. 1 shows an LNA single-stage amplifying circuit with a common cascode structure, in which the radio frequency amplifying path of the LNA is composed of an input blocking capacitor C1, an amplifying transistor MN2, a cascode transistor MN1, a load inductor L1, and an output matching capacitor C3. The Bias potentials of the MN2 and the MN1 are provided by a Bias circuit (Bias control) through large-resistance resistors R1 and R2, and the large-resistance resistors can reduce the influence of the Bias circuit on a radio frequency channel. The capacitor C2 is a filter capacitor connected to ground, and ensures that the bias potential of the cascode transistor MN1 is stable.

The first bias voltage Vb1 and the second bias voltage Vb2 are controlled by the input enable signal EN, thereby controlling the turning on and off of the LNA. The method comprises the following steps:

when the enable signal EN is at a high level, the first bias voltage Vb1 and the second bias voltage Vb2 will exhibit suitable bias potentials, so that the LNA enters an amplifying mode and is in an operating state.

When the enable signal EN is at a low level, the first bias voltage Vb1 and the second bias voltage Vb2 are normally switched to zero level, thereby turning off the amplified states of MN1 and MN2, bringing them into a cut-off region, so that the LNA is turned off.

When the enable signal EN is switched from a high level to a low level and from a low level to a high level, the first bias voltage Vb1 and the second bias voltage Vb2 are rapidly switched.

However, since the two potentials are provided to the transistor gate through the large resistors R1 and R2, and the transistor gate is connected to the blocking or filtering capacitors (C1 and C2), in the figure, R2 and C2 form a charge-discharge structure, and R1 and C1 form a charge-discharge structure, so that the gate potential of MN2 changes slowly with the charge of the capacitor C1, and the gate potential of the MN1 transistor changes slowly with the charge of the capacitor C2. The operational state of the LNA therefore experiences a longer switching time (relative to the time of the change in potential between Vb1 and Vb 2). The time constant of the handover τ=rc, typically after 3 τ times, is considered to be complete. When the enable signal EN is switched from a low level to a high level, vb1 and Vb2 change quickly, and the switching of the LNA from off to on takes a long time. Similarly, when the enable signal EN is switched from a high level to a low level, vb1 and Vb2 change quickly, and the switching of the LNA from on to off requires a long time. Even when the enable signal EN is switched from a high level to a low level and from a low level to a high level, the switching time of the LNA is long. That is, when the capacitor C is connected to the gate of the MOS transistor, the charge-discharge structure formed by the capacitor and the resistor requires a long time for turning off and on the MOS transistor as the transistor MN1, and further, requires a long time for switching the operation state of the LNA.

If the switching time is to be shortened, the value of the resistor or capacitor needs to be reduced, but this has a certain influence on the radio frequency performance. Reducing the resistance deteriorates the noise figure, and reducing the capacitance affects the noise figure and gain.

Therefore, the conventional charge-discharge structure formed by the capacitor C connected to the gate of the MOS tube and the capacitor and the resistor requires a long time for turning off and on the MOS tube, which is a technical problem that needs to be solved by those skilled in the art.

The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The embodiment of the application provides a MOS tube control circuit and an LNA single-stage amplifying device, which are used for solving the technical problem that a long time is required for turning off and on a MOS tube due to a traditional charge-discharge structure formed by a capacitor C connected to a grid electrode of the MOS tube and a capacitor and a resistor.

The embodiment of the application provides a MOS pipe control circuit, which comprises:

the MOS transistor comprises a main circuit MOS transistor MN, a capacitor C and a bias resistor R, wherein the capacitor C is connected with the grid electrode of the main circuit MOS transistor, one end of the bias resistor R is connected with the grid electrode of the main circuit MOS transistor MN, and the other end of the bias resistor R is connected with bias voltage; the main circuit MOS tube is an MOS tube in the main circuit;

A voltage-controlled switch MP connected in parallel with the bias resistor R;

the level edge detection circuit is connected with an enable signal EN, and the output end of the level edge detection circuit is connected with the control end of the voltage control type switch MP;

the level edge detection circuit is used for outputting a control signal to conduct the voltage control type switch MP for a preset time when detecting the preset edge of the enable signal EN, so that the bias resistor R is short-circuited for the preset time, and the potential of the grid electrode of the MOS tube of the main circuit is changed rapidly.

The embodiment of the application also provides an LNA single-stage amplifying device, which comprises:

the LNA single-stage amplifying circuit with the cascode structure comprises an amplifying transistor MN2 and a cascade transistor MN1 which are connected in series, a first bias resistor R1 for providing bias potential for the amplifying transistor MN2, and a second bias resistor R2 for providing bias potential for the cascade transistor MN 1;

a first switch MN3 and a second switch MP1 controlled by voltage, wherein the first switch MN3 is connected in parallel with a first bias resistor, and the second switch MP1 is connected in parallel with a second bias resistor;

the first output end of the level edge detection circuit is connected with the control end of the first switch MN3, and the second output end of the level edge detection circuit is connected with the control end of the second switch MP 1;

The level edge detection circuit is used for accessing an enable signal EN, and when a preset edge of the enable signal EN is detected, the output control signal turns on the first switch MN3 and the second switch MP1 for a preset time, so that the first bias resistor R1 and the second bias resistor R2 are short-circuited for the preset time.

By adopting the technical scheme, the embodiment of the application has the following technical effects:

the bias voltage is controlled by the inputted enable signal EN, thereby controlling the on and off of the main circuit. The method comprises the following steps:

when the enable signal EN is at a high level, the bias voltage will exhibit a suitable bias potential, so that the main circuit is in an operating state.

When the enable signal EN is switched to a low level, the bias voltage is switched to a zero level, thereby turning off the MOS transistor MN and turning off the main circuit.

More importantly, a voltage control type switch MP and a level edge detection circuit are arranged; the voltage controlled switch MP is connected in parallel with the bias resistor. When the level edge detection circuit detects the preset edge of the enable signal EN, the output control signal turns on the voltage control type switch MP for a preset time, and at the moment, current passes through the voltage control type switch MP without passing through the bias resistor R with larger resistance, namely, the bias resistor is short-circuited for the preset time. The voltage control type switch MP is used for directly charging and discharging the capacitor C, so that the potential of the grid electrode of the MOS tube of the main circuit is rapidly changed, and the switching time of the main circuit is shortened.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

FIG. 1 is a common cascode LNA single stage amplifier circuit;

fig. 2 is a schematic diagram of a MOS transistor control circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an embodiment of an LNA single stage amplifier device with MOS transistor control circuit;

fig. 4 is a schematic diagram of an application of a MOS transistor control circuit in another embodiment of the present application to an LNA single stage amplifying device;

fig. 5 is a schematic diagram of an application of a MOS transistor control circuit in an LNA single-stage amplifying device according to still another embodiment of the present application;

FIG. 6 is a schematic diagram of a low level pulse;

FIG. 7 is a schematic diagram of a high level pulse;

FIG. 8 is a schematic diagram of switching time of an LNA single-stage amplifier circuit of a common cascode configuration in the background art;

FIG. 9 is a schematic diagram of switching times of an LNA single stage amplification device in accordance with an embodiment of the disclosure;

fig. 10 is a schematic diagram of a single stage amplification device with MOS transistor protection circuit of the present application.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.

Example 1

As shown in fig. 2, the MOS transistor control circuit in the embodiment of the present application includes:

a voltage-controlled switch MP connected in parallel with the bias resistor R;

According to the MOS tube control circuit, the bias voltage is controlled by the input enable signal EN, so that the on and off of the main circuit are controlled. The method comprises the following steps:

As an alternative, the level edge detection circuit is specifically configured to:

when the rising edge of the enable signal EN is detected, the output control signal turns on the voltage control switch MP for a preset time, so that the bias resistor R is short-circuited for the preset time, and the potential of the grid electrode of the main circuit MOS tube is changed rapidly;

when the falling edge of the enable signal EN is detected, the output control signal turns on the voltage control switch MP for a preset time, so that the bias resistor R is short-circuited for the preset time, and the main circuit MOS tube is turned off rapidly.

That is, the main circuit MOS transistor is turned on for a preset time only when the rising edge and the falling edge of the enable signal EN are detected. At other times, the main circuit MOS transistor remains off.

Specifically, the level edge detection circuit may employ a level edge detection circuit in a dashed line box in fig. 3. The level edge detection circuit is not limited to the level edge detection circuit in the dashed box in fig. 3, but may have other structures.

As another alternative, the level edge detection circuit is specifically configured to:

when the rising edge of the enable signal EN is detected, the output control signal turns on the voltage control switch MP for a preset time, so that the bias resistor R is short-circuited for the preset time, and the potential of the grid electrode of the main circuit MOS tube is changed rapidly.

That is, the main circuit MOS transistor is turned on for a preset time only when the rising edge of the enable signal EN is detected. At other times, the main circuit MOS transistor remains off.

Specifically, the level edge detection circuit may employ a level edge detection circuit in a dashed line box in fig. 4. The level edge detection circuit is not limited to the level edge detection circuit in the dashed box in fig. 4, but may have other structures.

As a further alternative, the level edge detection circuit is specifically configured to:

When the falling edge of the enable signal EN is detected, the output control signal turns on the voltage control switch MP for a preset time, so that the bias resistor R is short-circuited for the preset time, and the potential of the grid electrode of the main circuit MOS tube is changed rapidly.

That is, the main circuit MOS transistor is turned on for a preset time only when the falling edge of the enable signal EN is detected. At other times, the main circuit MOS transistor remains off.

Specifically, the level edge detection circuit may employ a level edge detection circuit in a dashed line box in fig. 5. The level edge detection circuit is not limited to the level edge detection circuit in the dashed box in fig. 4, but may have other structures.

Example two

As shown in fig. 3, 4 and 5, the LNA single-stage amplifying device according to the embodiment of the present application includes:

the LNA single-stage amplifying circuit with the cascode structure comprises an amplifying transistor MN2 and a cascade transistor MN1 which are connected in series, a first bias resistor R1 for providing bias potential for the amplifying transistor MN2, and a second bias resistor R2 for providing bias potential for the cascade transistor MN 1; an input blocking capacitor C1 for providing an input blocking function, and a filter capacitor C2 for providing a filtering function; namely, the amplifying transistor MN2 and the cascode transistor MN1 correspond to the main circuit MOS transistor in the first embodiment, and the input blocking capacitor C1 and the filter capacitor C2 correspond to the capacitor C in the first embodiment;

A first switch MN3 and a second switch MP1 controlled by voltage, wherein the first switch MN3 is connected in parallel with a first bias resistor, and the second switch MP1 is connected in parallel with a second bias resistor; the first switch MN3 and the second switch MP1 correspond to the voltage control type switch in the first embodiment;

the first output end of the level edge detection circuit is connected with the control end of the first switch MN3, and the second output end of the level edge detection circuit is connected with the control end of the second switch MP1;

The LNA single-stage amplifying device is further provided with a level edge detection circuit, a first switch MN3 and a second switch MP1 on the basis of an LNA single-stage amplifying circuit with a cascode structure; the first switch MN3 is connected in parallel with the first bias resistor, and the second switch MP1 is connected in parallel with the second bias resistor. When the level edge detection circuit detects the preset edge of the enable signal EN, the output control signal turns on the first switch MN3 and the second switch MP1 for a preset time, and at the moment, current passes through the first switch MN3 and the second switch MP1 without passing through the first bias resistor R1 and the second bias resistor R2 with larger resistance values, namely the first bias resistor and the second bias resistor are short-circuited for the preset time. The direct charge and discharge of the input blocking capacitor C1 and the filter capacitor C2 through the first switch MN3 and the second switch MP1 are realized, and the rapid change of the electric potential of the control ends of the amplifying transistor MN2 and the cascade transistor MN1 is realized, so that the switching time of the LNA single-stage amplifying circuit is shortened, and the rapid switching of the LNA is realized.

In practice, as shown in fig. 3, 4 and 5, the LNA single stage amplification circuit includes a radio frequency amplification path; the radio frequency amplification path includes:

a first load inductor L1, the cascade transistor MN1, the amplifying transistor MN2 and a second source ecdysis inductor L2 which are sequentially connected from a power supply end VDD to a ground end;

an input blocking capacitor C1 connected between the radiofrequency input RFIN and the control terminal of the amplifying transistor MN 2;

the filter capacitor C2 is connected between the control end of the cascade transistor MN1 and the ground;

the output matching capacitor C3 is connected between the input end of the cascade transistor MN1 and the radio frequency output end RFOUT;

the first bias resistor R1 is connected between the first bias voltage Vb1 and the control terminal of the amplifying transistor MN 2;

the second bias resistor R2 is connected between the second bias voltage Vb2 and the control terminal of the cascode transistor MN 1.

In implementation, as shown in fig. 3, 4 and 5, the LNA single-stage amplifying circuit further includes a bias circuit, which is connected to the enable signal EN and outputs a first bias voltage Vb1 and a second bias voltage Vb2.

The Bias potential of the amplifying transistor MN2 is provided by a Bias circuit (Bias control) through a first Bias resistor R1 of a large resistance value; the Bias potential of the cascode transistor MN1 is provided by a Bias circuit (Bias control) through a second Bias resistor R2 of a large resistance value. The large-resistance resistor, namely the first bias resistor R1 and the second bias resistor R2, can reduce the influence of the bias circuit on the radio frequency path.

The filter capacitor C2 ensures that the bias potential of the cascode transistor MN1 is stable.

In the LNA single-stage amplifying device according to the embodiment of the present application, the input enable signal EN controls the first bias voltage Vb1 and the second bias voltage Vb2, so as to control the on and off of the LNA. The method comprises the following steps:

When the enable signal EN is switched to a low level, the first bias voltage Vb1 and the second bias voltage Vb2 are normally switched to zero level, thereby turning off the amplified states of MN1 and MN2, bringing them into a cut-off region, so that the LNA is turned off.

More importantly, a level edge detection circuit, a first switch MN3 and a second switch MP1 are arranged; the first switch MN3 is connected in parallel with the first bias resistor, and the second switch MP1 is connected in parallel with the second bias resistor. When the level edge detection circuit detects the preset edge of the enable signal EN, the output control signal turns on the first switch MN3 and the second switch MP1 for a preset time, and at the moment, current passes through the first switch MN3 and the second switch MP1 without passing through the first bias resistor R1 and the second bias resistor R2 with larger resistance values, namely the first bias resistor and the second bias resistor are short-circuited for the preset time. The first switch MN3 and the second switch MP1 are implemented to directly charge and discharge the input blocking capacitor C1 and the filter capacitor C2, so as to shorten the switching time of the LNA single-stage amplifying circuit.

Example III

The dashed line in fig. 3 indicates a level edge detection circuit.

The level edge detection circuit is specifically used for:

when the rising edge of the enable signal EN is detected, the output control signal turns on the first switch MN3 and the second switch MP1 for a preset time so as to shorten the switching time of the LNA single-stage amplifying circuit from off to on;

when the falling edge of the enable signal EN is detected, the output control signal turns on the first switch MN3 and the second switch MP1 for a preset time, so that the switching time from the on to the off of the LNA single-stage amplifying circuit is shortened.

That is, the first switch MN3 and the second switch MP1 are turned on for a preset time only when the rising and falling edges of the enable signal EN are detected. At other times, both the first switch MN3 and the second switch MP1 remain closed.

In practice, when the high level is switched to the low level and the low level is switched to the high level, the switching of the LNA is quickened when both the rising edge and the falling edge of the enable signal EN are detected correspondingly. Correspondingly, the switching of the LNA from on to off and the switching from off to on are both expedited.

In implementation, as shown in fig. 3, the level edge detection circuit includes an inverter one INV1, a capacitor four C4, a NAND gate one NAND1, a NAND gate three NAND3, an inverter four INV4, a control signal output end one CTLP and a control signal output end two CTLN;

The input end of the inverter I INV1 and one input end of the NAND gate I NAND1 are respectively connected with an enabling signal, the output end of the inverter I INV1 is connected with the other input end of the NAND gate I NAND1, and the capacitor IV C4 is connected between the output end of the inverter I INV1 and the ground;

the output end of the NAND gate one NAND1 is connected with one input end of the NAND gate three NAND 3;

the level edge detection circuit further includes:

inverter two INV2, inverter three INV3, capacitor five C5, NAND gate two NAND2;

the input end of the inverter II INV2 is connected with an enabling signal, the output end of the inverter II INV2 is respectively connected with the input end of the inverter III INV3 and one input end of the NAND gate II NAND2, the output end of the inverter III INV3 is connected with the other input end of the NAND gate II NAND2, and the capacitor five C5 is connected between the output end of the inverter III INV3 and the ground;

the output end of the NAND gate III NAND3 is also connected with the input end of the inverter IV INV4, and the output end of the inverter IV INV4 is connected with the control signal output end CTLP;

the output end of the NAND gate three NAND3 is also connected with a control signal output end two CTLN.

The specific implementation mode of the level edge detection circuit is as follows:

when EN is low, vb1 and Vb2 normally output zero level, thereby turning off the amplification state of MN1 and MN2, bringing it into the cut-off region, so that the LNA is turned off. When EN is high, vb1 and Vb2 will show proper bias potential, so that LNA enters amplifying mode to be working state.

When EN is at a low level, as shown in fig. 3, the EN level passes through the inverter INV1 and then enters the NAND gate NAND1, and the other EN level directly enters the NAND gate NAND1, and at this time, the NAND gate NAND1 outputs a high level.

When EN is switched from low level to high level, the output of the inverter INV1 does not immediately become low level, but the inverter INV1 maintains high level for a period of time because the inverter INV1 and the capacitor four C4 form a delay circuit; at this time, NAND gate one NAND1 has two high inputs and outputs a low level for a period of time. When the delay of the NAND gate one INV1 is finished and the output of the inverter one INV1 becomes low, the output of the NAND gate one NAND1 is restored to high level, forming a low level pulse as shown in fig. 6.

When EN is switched from high level to low level, after passing through the inverter two INV2, a delay circuit is formed by the NAND gate three INV3 and the capacitor C5, and the same can be obtained that the NAND gate two NAND2 outputs a low level pulse. The signal that outputs the low level pulse is formed as a high level pulse as shown in fig. 7 after passing through the NAND gate three NAND1 or the NAND gate two NAND2, becomes an output signal of CTLN, and then becomes a low level pulse after passing through the inverter four INV4, and becomes an output signal of CTLP.

A low level pulse as shown in fig. 6 is output at CTLP, so that the second switch MP1 is turned on for a period of time and then turned off, and a high level pulse as shown in fig. 7 is output at CTLN, so that the first switch MN3 is turned on for a period of time and then turned off.

In the LNA single-stage amplifying circuit with the common cascode structure shown in fig. 1, a radio frequency signal with a fixed power is input at the RFIN, and when the EN is used for performing the level switching of high level-low level-high level, the simulation can see that the output signal at the RFOUT also switches along with the switching of the LNA state, as shown in fig. 8. Estimated at 90% of the variation, it can be seen that the switching time when the LNA is on is about 470ns and the switching time when the LNA is off is about 200ns.

In the LNA single stage amplifying device shown in fig. 3, when the enable signal EN performs the level switching of high level-low level-high level, the simulation can see that the output signal at RFOUT also switches with the switching of the LNA state, as shown in fig. 9. Estimated at 90% of the variation, it can be seen that the switching time when the LNA is on is about 280ns and the switching time when the LNA is off is about 80ns. The switching time is significantly faster.

Example IV

In practice, the level edge detection circuit is specifically configured to:

When the rising edge of the enable signal EN is detected, the output control signal turns on the first switch MN3 and the second switch MP1 for a preset time, so as to shorten the switching time of the LNA single-stage amplifying circuit from off to on.

The enable signal EN is switched from a low level to a high level, and at this time, the first bias voltage Vb1 and the second bias voltage Vb2 are rapidly switched to bias potentials. Under the cooperation of the level edge detection circuit, the first switch MN3 and the second switch MP1, the level edge detection circuit detects the rising edge of the enable signal EN, the first switch MN3 and the second switch MP1 are conducted for a preset time, the input blocking capacitor C1 and the filter capacitor C2 are directly charged through the first switch MN3 and the second switch MP1 in the conducting preset time, the quick change of the electric potentials of the control ends of the amplifying transistor MN2 and the cascade transistor MN1 is realized, the switching time of the LNA single-stage amplifying circuit is shortened, and the quick switch of the LNA from off to on is realized.

After the preset time for turning on the first switch MN3 and the second switch MP1 is over, the first bias voltage Vb1 and the second bias voltage Vb2 still maintain bias potentials, and are connected with the gates of the amplifying transistor MN2 and the cascode transistor MN1 through the first bias resistor R1 and the second bias resistor R2 respectively, so that the LNA is kept on, and normal radio frequency performance is maintained.

That is, the first switch MN3 and the second switch MP1 are turned on for a preset time only when the rising edge of the enable signal EN is detected. At other times, both the first switch MN3 and the second switch MP1 remain closed.

Correspondingly, as shown in fig. 4, the level edge detection circuit is used for detecting a rising edge. The level edge detection circuit comprises an inverter I INV1, a capacitor IV C4, a NAND gate I NAND1, an inverter IV INV4, a control signal output end I CTLP and a control signal output end II CTLN;

the output end of the NAND gate one NAND1 is connected with the control signal output end one CTLP,

the output end of the NAND gate one NAND1 is also connected with the input end of the inverter four INV4, and the output end of the inverter four INV4 is connected with the control signal output end two CTLNs.

When the enable signal EN is at a low level, the first bias voltage Vb1 and the second bias voltage Vb2 are normally switched to zero level, thereby turning off the amplified states of MN1 and MN2, bringing them into a cut-off region, so that the LNA is turned off. The specific process is as follows:

as shown in fig. 4, when the enable signal EN is at a low level:

vb1 and Vb2 are zero level, so that the LNA is turned off;

the enable signal EN level passes through the inverter INV1 and then enters the NAND gate NAND1, and meanwhile, the other enable signal EN level directly enters the NAND gate NAND1, and the NAND gate NAND1 outputs a high level. The control signal output end CTLP outputs a high level to the control end of the second switch MP1, controls the second switch MP1 to be closed, and keeps the LNA closed; the control signal output end two CTLNs output low level to the control end of the first switch MN3, the first switch MN3 is controlled to be closed, and the LNA is kept closed.

In summary, when the enable signal EN is at a low level, the second switch MP1 is turned off, the first switch MN3 is turned off, and the corresponding LNA single-stage amplifying device is turned off.

As shown in fig. 4, when the enable signal EN is switched from the low level to the high level, the rising edge of the enable signal EN is correspondingly detected:

vb1 and Vb2 are rapidly switched from zero level to bias potential;

since the inverter INV1 and the capacitor C4 form a delay circuit, the output of the inverter INV1 does not immediately become low level, but maintains high level for a period of time, and the NAND gate NAND1 has two high level inputs and outputs low level for a period of time. When the delay of the inverter one INV1 is finished and the output of the inverter one INV1 becomes low, the output of the NAND gate one NAND1 is restored to high level, forming a low level pulse as shown in fig. 6. I.e. the control signal output terminal CTLP outputs the low-level pulse as shown in fig. 6. Meanwhile, the control signal output terminal two CTLNs output high level pulses as shown in fig. 7.

In this way, when the enable signal EN is switched from low level to high level, a low level pulse is output from a CTLP at the control signal output end after a small delay, and the second switch MP1 is controlled to be turned on for a preset time so that the second bias resistor R2 is short-circuited, and the cascode transistor MN1 is turned on rapidly; meanwhile, the second CTLN at the control signal output end outputs a high-level pulse, and controls the first switch MN3 to be conducted for a preset time to enable the second bias resistor R2 to be short-circuited, and the amplifying transistor MN2 is rapidly started, namely LAN is started. When the first CTLP of the control signal output terminal returns to the high level and the second CTLN of the control signal output terminal returns to the low level, the second switch MP1 and the first switch MN3 are turned off. At this time, vb1 and Vb2 are bias potentials, and are connected to the gates of the amplifying transistor MN2 and the cascode transistor MN1 through the first bias resistor R1 and the second bias resistor R2, respectively, and the LNA remains on and maintains normal radio frequency performance.

The delay from EN switching from low to high to start outputting low pulses at CTLP is determined by inverter INV 1. Compared with the time delay caused by the charge-discharge structure formed by R2 and C2 and the charge-discharge structure formed by R1 and C1 in the background art, the time delay is much shorter. Therefore, an LNA single stage amplification device with a level edge detection circuit, the LNA switches faster from off to on than in the background.

When the enable signal EN is switched from a high level to a low level, the level edge detection circuit does not detect, and therefore, the switching of the LNA from on to off is not accelerated.

Example five

In practice, the level edge detection circuit is specifically configured to:

The enable signal EN is switched from a high level to a low level, and at this time, the first bias voltage Vb1 and the second bias voltage Vb2 are rapidly switched to zero. Under the cooperation of the level edge detection circuit, the first switch MN3 and the second switch MP1, the level edge detection circuit detects the falling edge of the enable signal EN, the first switch MN3 and the second switch MP1 are conducted for a preset time, the input blocking capacitor C1 and the filter capacitor C2 are directly discharged through the first switch MN3 and the second switch MP1 in the conducting preset time, the quick change of the electric potentials of the control ends of the amplifying transistor MN2 and the cascade transistor MN1 is realized, the switching time of the LNA single-stage amplifying circuit is shortened, and the quick switching of the LNA from the switch to the switch is realized.

After the preset time for turning on the first switch MN3 and the second switch MP1 is over, the first bias voltage Vb1 and the second bias voltage Vb2 remain at low levels, and are connected to the gates of MN1 and MN2 through the first bias resistor R1 and the second bias resistor R2, respectively, so that the LNA remains turned off.

That is, the first switch MN3 and the second switch MP1 are turned on for a preset time only when the falling edge of the enable signal EN is detected. At other times, both the first switch MN3 and the second switch MP1 remain closed.

Correspondingly, as shown in fig. 5, the level edge detection circuit includes an inverter two INV2, an inverter one INV1, a capacitor four C4, a NAND gate one NAND1, an inverter four INV4, a control signal output end one CTLP and a control signal output end two CTLN;

the input end of the inverter II INV2 is connected with an enabling signal, the output end of the inverter II INV2 is respectively connected with the input end of the inverter I INV1 and one input end of the NAND gate I NAND1, the output end of the inverter I INV1 is connected with the other input end of the NAND gate I NAND1, and the capacitor IV C4 is connected between the output end of the inverter I INV1 and the ground;

when the enable signal EN is at a high level, the first bias voltage Vb1 and the second bias voltage Vb2 will exhibit suitable bias potentials, so that the LNA enters an amplifying mode and is in an operating state. The specific process is as follows:

as shown in fig. 5, when the enable signal EN is at a high level:

vb1 and Vb2 are bias potentials such that the LNA is turned on;

the enable signal EN level is connected into an inverter I INV1 and an NAND gate I NAND1 after passing through an inverter II INV 2; the signal passing through the inverter one INV1 is also connected to the NAND gate one NAND1, and the NAND gate one NAND1 outputs a high level. The control signal output end CTLP outputs a high level to the control end of the second switch MP1, and controls the second switch MP1 to be closed; the control signal output end two CTLNs output low level to the control end of the first switch MN3, and control the first switch MN3 to be closed.

In summary, when the enable signal EN is at a high level, the second switch MP1 is turned off, the first switch MN3 is turned off, and the LNA single-stage amplifying device is turned on.

As shown in fig. 5, when the enable signal EN is switched from the high level to the low level, the falling edge of the enable signal EN is correspondingly detected:

vb1 and Vb2 switch rapidly from bias potential to zero;

the low level of the enable signal EN is inverted to the high level through the inverter two INV 2. Since the inverter INV1 and the capacitor C4 form a delay circuit, the output of the inverter INV1 does not immediately become low level, but maintains high level for a period of time, and the NAND gate NAND1 has two high level inputs and outputs low level for a period of time. When the delay of the inverter one INV1 is finished and the output of the inverter one INV1 becomes low, the output of the NAND gate one NAND1 is restored to high level, forming a low level pulse as shown in fig. 6. I.e. the control signal output terminal CTLP outputs the low-level pulse as shown in fig. 6. Meanwhile, the control signal output terminal two CTLNs output high level pulses as shown in fig. 7.

Thus, when the enable signal EN is switched from the high level to the low level, a low level pulse is output at a CTLP at the control signal output terminal after a small delay, and then the high level is restored. When a CTLP outputs a low-level pulse at the control signal output end, the second switch MP1 is controlled to be conducted for a preset time to enable the second bias resistor R2 to be short-circuited, the capacitor C2 is rapidly discharged, and the cascade transistor MN1 is rapidly turned off; meanwhile, the second CTLN at the control signal output end outputs a high-level pulse, and controls the first switch MN3 to be conducted for a preset time to enable the second bias resistor R2 to be short-circuited, the capacitor C1 is rapidly discharged, and the amplifying transistor MN2 is turned off, namely the LAN is turned off. The high level is restored at the first CTLP of the control signal output terminal, the second CTLN of the control signal output terminal is restored to the low level, and the second switch MP1 and the first switch MN3 are turned off. At this time, vb1 and Vb2 are zero, and are connected to the gates of MN1 and MN2 through the first bias resistor R1 and the second bias resistor R2, respectively, and the LAN remains closed.

The EN is switched from high to low, and the output of the low pulse starts at CTLP, and the delay time is determined by inverters INV1 and INV 2. Compared with the time delay caused by the charge-discharge structure formed by R2 and C2 and the charge-discharge structure formed by R1 and C1 in the background art, the time delay is much shorter. Therefore, the LNA single stage amplification device with the level falling edge detection circuit switches the LNA faster from on to off than in the background art.

When the enable signal EN is switched from low to high, the edge detection circuit does not detect, and therefore the switching of the LNA from off to on is not expedited.

Example six

The LNA single-stage amplification device according to the embodiment of the present application further includes the following features on the basis of the second to fifth embodiments.

As shown in fig. 10, the LNA single-stage amplifying device according to the embodiment of the present application further includes a MOS transistor protection circuit, where the MOS transistor protection circuit includes a gate-source protection sub-circuit, and the gate-source protection sub-circuit includes:

the anode of the diode D4 is connected with the grid electrode of the MOS tube, and the cathode of the diode D4 is connected with the source electrode of the MOS tube;

when the voltage difference between the grid electrode and the source electrode of the MOS tube is larger than the starting voltage of the diode four D4, the diode four D4 is conducted to reduce the voltage difference between the grid electrode and the source electrode of the MOS tube.

When the voltage difference between the grid electrode and the source electrode of the MOS tube is larger than the starting voltage of the diode D4, the diode D4 is conducted, current from the grid electrode of the MOS tube to the diode D4 to the source electrode of the MOS tube is generated, the voltage difference between the grid electrode and the source electrode of the MOS tube is reduced, and the effect that the grid electrode and the source electrode of the MOS tube are not broken down is achieved.

In the second to fifth embodiments, the cascode transistor MN1 and the amplifying transistor MN2 are both MOS transistors. The amplifying transistor MN2 is connected to the radio frequency signal, and further needs protection. Accordingly, fig. 10 shows a manner of providing the MOS transistor protection circuit for the amplifying transistor MN 2. The MOS tube protection circuit in the LNA single-stage amplifying device can be arranged for each MOS tube to be protected.

As shown in fig. 10, the MOS transistor protection circuit further includes a source gate protection sub-circuit, which includes:

the anode of the diode five D5 is connected with the source electrode of the MOS tube, and the cathode of the diode five D5 is connected with the grid electrode of the MOS tube;

when the voltage difference between the source electrode and the grid electrode of the MOS tube is larger than the starting voltage of the diode five D5, the diode five D5 is conducted to reduce the voltage difference between the source electrode and the grid electrode of the MOS tube.

When the voltage difference between the MOS tube source electrode and the grid electrode is larger than the starting voltage of the diode pentaD 5, the diode pentaD 5 is conducted to generate current from the MOS tube source electrode to the diode pentaD 5 to the MOS tube grid electrode, so that the voltage difference between the MOS tube grid electrode and the source electrode is reduced, and the effect that the MOS tube grid electrode and the source electrode are not broken down is achieved.

As shown in fig. 10, the MOS transistor protection circuit further includes a gate-drain protection sub-circuit, which includes:

the anode of the diode D3 is connected with the grid electrode of the MOS tube, and the cathode of the diode D3 is connected with the drain electrode of the MOS tube;

when the voltage difference between the grid electrode and the drain electrode of the MOS tube is larger than the starting voltage of the diode tri-D3, the diode tri-D3 is conducted to reduce the voltage difference between the grid electrode and the drain electrode of the MOS tube.

When the voltage difference between the MOS tube grid and the drain electrode is larger than the starting voltage of the diode tri-D3, the diode tri-D3 is conducted to generate current from the MOS tube grid to the diode tri-D3 to the MOS tube drain electrode, so that the voltage difference between the MOS tube grid and the drain electrode is reduced, and the effect that the MOS tube grid and the drain electrode are not broken down is achieved.

As shown in fig. 10, the MOS transistor protection circuit further includes a drain-gate protection sub-circuit, which includes:

the diode II D2 and the diode I D1 which are connected in series are connected, and the cathode of the diode II D2 is connected with the anode of the diode I D1;

the anode of the diode D2 is connected with the drain electrode of the MOS tube, and the cathode of the diode D1 is connected with the grid electrode of the MOS tube;

when the voltage difference between the drain electrode and the gate electrode of the MOS transistor is larger than the sum of the turn-on voltages of the diode two D2 and the diode one D1, the diode two D2 and the diode one D1 are conducted to reduce the voltage difference between the drain electrode and the gate electrode of the MOS transistor.

When the voltage difference between the drain electrode and the grid electrode of the MOS tube is larger than the sum of the starting voltages of the diode two D2 and the diode one D1, the diode two D2 and the diode one D1 are conducted to generate current from the drain electrode of the MOS tube to the diode two D2 and the diode one D1 to the grid electrode of the MOS tube, so that the voltage difference between the drain electrode and the grid electrode of the MOS tube is reduced, and the effect that the grid electrode and the drain electrode of the MOS tube are not broken down is achieved.

The drain electrode and the grid electrode of the amplifying transistor MN2 are connected in series by adopting the mode that the diode D2 and the diode D1 are connected in series, and the drain voltage of the amplifying transistor MN2 is higher than the grid voltage under the normal working state of the LNA single-stage amplifying device. In order to ensure that the voltage difference between the gate and the drain of the amplifying transistor MN2 does not break down the amplifying transistor MN2 when the LNA single stage amplifying device is operating normally. Therefore, a series connection of the diode D2 and the diode D1 is required as a protection circuit. The voltage difference in the rest will not cause the diode to conduct and therefore only one diode connection is possible (D3, D4, D5 in the figure).

As shown in fig. 10, the LNA single stage amplification device further includes an ESD protection circuit including:

the diode seven D7 and the diode six D6 are connected, the cathode of the diode seven D7 is connected with the anode of the diode six D6, the anode of the diode seven D7 is connected with the connection part of the input blocking capacitor C1 and the radio frequency input RFIN, and the cathode of the diode six D6 is grounded;

The diode nine D9 and the diode eight D8 are connected, the anode of the diode nine D9 is connected with the cathode of the diode eight D8, the cathode of the diode nine D9 is connected with the junction of the input blocking capacitor C1 and the radio frequency input RFIN, and the anode of the diode eight D8 is grounded.

Diodes D1-D5 are used for MOS transistor protection, and do not need to pass instantaneous large currents as ESD protection, and are much smaller in size than diodes D6-D9 for ESD protection. Therefore, the influence on the radio frequency performance is small, and the radio frequency performance is ensured while the protection effect is played.

The high-power interference simulation of the LNA single-stage amplification device of fig. 10 can obtain the voltage difference swing between the gate and the source of the amplifying transistor MN2, where the voltage positive peak value is about 1.5V and the voltage negative peak value is about 1.8V. The voltage difference swing between the gate and the drain of the amplifying transistor MN2 has a positive voltage peak value of 1.4V and a negative voltage peak value of 2.4V. Compared with the situation that no MOS tube protection circuit is added, the peak voltage is greatly reduced. Assuming that the gate and source voltage bearing capability of the amplifying transistor MN2 is 3V, the amplifying transistor MN2 can bear the peak voltage at this time, and is not damaged, and the reliability in the face of high-power interference is greatly improved.

In fig. 10, a diode is used in the MOS transistor protection circuit, but the present invention is not limited to this device, and other devices with limited voltage function, such as a MOS transistor (the MOS transistor adopts diode connection), may also be applied to the present scheme to replace the diode function.

In the sixth embodiment, the number of diodes connected in series is determined according to the voltage limiting condition actually required, and is not limited to one or two. As in this case, the previous ESD protection circuit has a certain protection effect due to the fact that two diodes are connected in series to ground. Therefore, a single diode is adopted to be connected to the grid source electrode (D3 and D4) of the MOS tube when the protection effect is enhanced, so that the voltage limiting value is further reduced. The number of diodes is selected depending on the voltage resistance value of the MOS transistor to be protected and the peripheral circuit, and is not limited to the number in the present application.

In the description of the present application and its embodiments, it should be understood that the terms "top," "bottom," "height," and the like indicate an orientation or positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, rather than to indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.

In this application and in its embodiments, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed, unless otherwise explicitly stated and defined as such; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

In this application and in its embodiments, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the present application. The components and arrangements of specific examples are described above in order to simplify the disclosure of this application. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A MOS transistor control circuit, comprising:

a voltage-controlled switch MP connected in parallel with the bias resistor R;

2. The MOS transistor control circuit of claim 1, wherein the level edge detection circuit is specifically configured to:

3. The MOS transistor control circuit of claim 1, wherein the level edge detection circuit is specifically configured to:

4. The MOS transistor control circuit of claim 1, wherein the level edge detection circuit is specifically configured to:

5. An LNA single stage amplification device, comprising:

the LNA single-stage amplifying circuit with the cascode structure comprises an amplifying transistor MN2 and a cascade transistor MN1 which are connected in series, a first bias resistor R1 for providing bias potential for the amplifying transistor MN2, a second bias resistor R2 for providing bias potential for the cascade transistor MN1, an input blocking capacitor C1 for providing input blocking function and a filter capacitor C2 for providing filtering function;

6. The LNA single stage amplification device of claim 5, wherein the level edge detection circuit is specifically configured to:

7. The LNA single stage amplification device of claim 5, wherein the level edge detection circuit is specifically configured to:

8. The LNA single stage amplification device of claim 5, wherein the level edge detection circuit is specifically configured to:

9. The LNA single stage amplification device of claim 6, wherein the level edge detection circuit comprises an inverter one INV1, a capacitor four C4, a NAND gate one NAND1, a NAND gate three NAND3, an inverter four INV4, a control signal output terminal one CTLP and a control signal output terminal two CTLN;

the level edge detection circuit further comprises an inverter II INV2, an inverter III INV3, a capacitor five C5 and a NAND gate II NAND2;

The output end of the NAND gate II NAND2 is connected with the other input end of the NAND gate III NAND 3;

the output end of the NAND gate III NAND3 is connected with the input end of the inverter IV INV4, and the output end of the inverter IV INV4 is connected with the control signal output end CTLP;

10. The LNA single stage amplification device of claim 7, wherein the level edge detection circuit comprises an inverter one INV1, a capacitor four C4, a NAND gate one NAND1, an inverter four INV4, a control signal output terminal one CTLP and a control signal output terminal two CTLN;

11. The LNA single stage amplification device of claim 8, wherein the level edge detection circuit comprises an inverter two INV2, an inverter one INV1, a capacitor four C4, a NAND gate one NAND1, an inverter four INV4, a control signal output terminal one CTLP and a control signal output terminal two CTLN;

12. The LNA single stage amplification device of any one of claims 5 to 11, wherein the LNA single stage amplification circuit comprises a radio frequency amplification path; the radio frequency amplification path includes:

the input blocking capacitor C1 is connected between the radiofrequency input RFIN and the control end of the amplifying transistor MN 2;

13. The LNA single stage amplification device of claim 12, wherein the LNA single stage amplification circuit further comprises a bias circuit that outputs the first bias voltage Vb1 and the second bias voltage Vb2 with the enable signal EN on.