CN116130504B - Pixel unit, manufacturing method thereof, micro display screen and pixel split device - Google Patents

Pixel unit, manufacturing method thereof, micro display screen and pixel split device Download PDF

Info

Publication number
CN116130504B
CN116130504B CN202310389702.2A CN202310389702A CN116130504B CN 116130504 B CN116130504 B CN 116130504B CN 202310389702 A CN202310389702 A CN 202310389702A CN 116130504 B CN116130504 B CN 116130504B
Authority
CN
China
Prior art keywords
layer
bonding
back plate
light
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310389702.2A
Other languages
Chinese (zh)
Other versions
CN116130504A (en
Inventor
王亚洲
邵明镜
杨志祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novos Technology Suzhou Co ltd
Original Assignee
Novos Technology Suzhou Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novos Technology Suzhou Co ltd filed Critical Novos Technology Suzhou Co ltd
Priority to CN202310389702.2A priority Critical patent/CN116130504B/en
Publication of CN116130504A publication Critical patent/CN116130504A/en
Application granted granted Critical
Publication of CN116130504B publication Critical patent/CN116130504B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0756—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses a pixel unit and a manufacturing method thereof, a micro display screen and a pixel discrete device, wherein the pixel unit comprises a back plate and a display unit arranged on the back plate; the display unit comprises a first device layer and a second device layer which are stacked along a direction far away from the backboard, wherein the first device layer comprises a first stacking layer, and the second device layer comprises a second stacking layer; the first stacking layer comprises a first bonding layer and a first compound light-emitting layer which are arranged in a bonding mode, the second stacking layer comprises a second bonding layer and a second compound light-emitting layer which are arranged in a bonding mode, the light transmittance of the second bonding layer is not more than 5%, and at least part of first visible light emitted by the first compound light-emitting layer penetrates through the second device layer along the vertical direction of the backboard and is transmitted to the outside of the pixel unit; according to the multi-color display device, multi-color display is achieved through the mode of stacking at least two device layers on the backboard, so that the pixel density is improved, the variegation phenomenon caused by photoexcitation is avoided, the light loss is effectively avoided, and the performance of a pixel unit is improved.

Description

Pixel unit, manufacturing method thereof, micro display screen and pixel split device
Technical Field
The present disclosure relates to the field of semiconductor devices, and more particularly, to a pixel unit, a method for manufacturing the pixel unit, a micro display, and a pixel split device.
Background
Micro-LED display technology is widely regarded as the next generation display technology, has great prospect in the field of wearable devices and direct display, and is a very challenging problem at present. At present, the colorized structural layout mainly comprises two types of horizontal distribution and coaxial vertical distribution of red, green and blue sub-pixels, and both the two schemes have certain defects.
In the red, green and blue sub-pixel horizontal distribution structure, three sub-pixels in the horizontal direction form a color pixel unit. The pixel size of the pixel unit in the horizontal direction is larger, so that the pixel density of the formed micro display device is smaller, and the micro display with small pixel size and high pixel density is challenging.
In the red-green-blue coaxial vertical arrangement scheme, the pixel size and the pixel density can be ensured. However, because of the photoexcitation, blue light and green light, which are short wavelength light sources, have higher energy to excite red light more easily, resulting in the problem that red sub-pixels are lit up under the influence of photoexcitation effect when short wavelength sub-pixels (such as blue sub-pixels or green sub-pixels) are lit up individually. In order to solve the problem of photoexcitation, a unidirectional light-transmitting film layer (such as a light screen layer) is often required to be introduced, but this leads to attenuation of the overall performance, for example, in chinese patent application publication No. CN114793476a, the microdisplay includes a red compound light-emitting layer, a green compound light-emitting layer, and a blue compound light-emitting layer, and the reflective layers thereof all need to shield the upper sub-pixel layer, but allow the lower sub-pixel layer to transmit. This structure actually absorbs light of different wavelengths, resulting in light loss of the underlying light as it passes through, affecting the performance of the microdisplay.
Therefore, there is a need for a color display semiconductor device that effectively overcomes the above-described drawbacks.
Disclosure of Invention
The purpose of the application is to provide a pixel unit, a manufacturing method thereof, a micro display screen and a pixel discrete device, which can effectively avoid the variegation phenomenon caused by photoexcitation and effectively avoid light loss.
In order to achieve the above object, a first aspect of the present application proposes a pixel unit, where the pixel unit includes a back plate and a display unit disposed on the back plate;
the display unit comprises a first device layer and a second device layer which are sequentially stacked along a direction far away from the backboard, wherein the first device layer comprises a first stacking layer, and the second device layer comprises a second stacking layer;
the first stacking layer comprises a first bonding layer and a first compound light-emitting layer which are arranged in a bonding mode, the second stacking layer comprises a second bonding layer and a second compound light-emitting layer which are arranged in a bonding mode, the light transmittance of the second bonding layer is not more than 5%, the first compound light-emitting layer emits first visible light in a working state, and the second compound light-emitting layer emits second visible light which is different from the first visible light in the working state;
At least part of the first visible light emitted by the first compound light-emitting layer passes through the second device layer along the vertical direction of the back plate and is transmitted to the outside of the pixel unit.
In a preferred embodiment, the display unit further includes a third device layer disposed on a side of the second device layer away from the first device layer, the third device layer includes a third stacked layer, the third stacked layer includes a third bonding layer and a third compound light-emitting layer that are disposed in a bonding manner, a light transmittance of the third bonding layer is not more than 5%, and the third compound light-emitting layer emits a third visible light in a working state;
at least a portion of the first visible light emitted from the first compound light-emitting layer passes through the second device layer and the third device layer in a vertical direction of the back plate and is transmitted to the outside of the pixel unit, and/or,
and at least part of the second visible light emitted by the second compound light-emitting layer passes through the third device layer along the vertical direction of the backboard and is transmitted to the outside of the pixel unit.
In a preferred embodiment, the back plate is provided with a drive circuit, the drive circuit being provided with at least one anode; the display unit further includes a first anode electrical connection structure;
One end of the first anode electrical connection structure is connected with the corresponding anode, the other end of the first anode electrical connection structure penetrates through the first device layer to be connected with the second stacking layer, and projection of the first anode electrical connection structure on the backboard is located in projection of the second stacking layer on the backboard.
In a preferred embodiment, the back plate further comprises a first reinforcing structure, said first reinforcing structure being connected to at least one of said anodes;
the pixel unit further comprises a dielectric layer, and the dielectric layer is arranged between the display unit and the backboard.
In a preferred embodiment, the pixel unit further includes a second reinforcing structure surrounding the display unit;
the first compound light-emitting layer comprises a first P-type ohmic contact layer, a first active quantum well layer and a first N-type ohmic contact layer;
the first N-type ohmic contact layer extends and is connected with the second reinforcing structure, and the first N-type ohmic contact layer is made of transparent conductive materials.
In a preferred embodiment, the first device layer further includes a first dielectric filling layer, and the first stacked layer and the first anode electrical connection structure are both embedded in the first dielectric filling layer; the second device layer further comprises a second dielectric filling layer, and the second stacking layer is embedded in the second dielectric filling layer; the third device layer further comprises a third dielectric filling layer, and the third stacking layer is embedded in the third dielectric filling layer;
The first medium filling layer, the second medium filling layer and the third medium filling layer are all made of transparent medium materials.
In a preferred embodiment, at least part of the first stacked layer is not coincident with the projection of at least part of the second stacked layer on the back plate, and at least part of the first visible light emitted by the first compound light emitting layer is transmitted outwards through the second dielectric filling layer along the vertical direction of the back plate.
In a preferred embodiment, at least part of the first stacked layer coincides with the projection of at least part of the second stacked layer onto the back plate;
the second device layer further comprises at least one first optical lens, one side of any first optical lens is connected with the first N-type ohmic contact layer, and the other side of any first optical lens is connected with the second N-type ohmic contact layer included in the second stacked layer;
the third device layer further comprises at least one second optical lens, one side of any second optical lens is connected with the second N-type ohmic contact layer, and the other side of any second optical lens is connected with a third N-type ohmic contact layer included in the third stacked layer;
at least a portion of the projection of the first optical lens onto the back plate coincides with at least a portion of the corresponding projection of the second optical lens onto the back plate.
In a second aspect, there is provided a method for manufacturing a pixel unit according to any one of the first aspects, the method comprising:
preparing a backboard;
fabricating a display unit, bonding a first target compound semiconductor prepared in advance with the back plate to form a first stacked layer and constructing to form the first device layer; bonding a previously prepared second target compound semiconductor with the first device layer to form a second stacked layer and configuring to form the second device layer; the second bonding layer included in the second stacked layer has a light transmittance of not more than 5%, the first compound light-emitting layer included in the first stacked layer emits first visible light in a working state, and the second compound light-emitting layer emits second visible light different from the first visible light in the working state; at least part of the first visible light emitted by the first compound light-emitting layer passes through the second device layer along the vertical direction of the back plate and is transmitted to the outside of the pixel unit.
In a preferred embodiment, the bonding the first target compound semiconductor prepared in advance with the back plate to form a first stacked layer and to configure to form the first device layer includes:
Plating an insulating material on the surface of the backboard provided with at least one anode to form a dielectric layer;
manufacturing a first P-type ohmic contact layer on the surface of the first target compound semiconductor;
bonding the back plate with the first target compound semiconductor and removing the substrate of the first target compound semiconductor;
exposing the first N-type ohmic contact layer through etching or polishing to form a first stacked layer;
and filling the first dielectric filling layer and constructing a corresponding electric connection structure to form the first device layer.
In a preferred embodiment, the bonding of the previously prepared second target compound semiconductor with the first device layer to form a second stacked layer and to construct the second device layer includes:
manufacturing a second P-type ohmic contact layer on the surface of the second target compound semiconductor;
bonding the first device layer with the second target compound semiconductor and removing the substrate of the second target compound semiconductor;
exposing the second N-type ohmic contact layer through etching or polishing to form a second stacked layer;
and filling a second dielectric filling layer and constructing a corresponding electric connection structure to form the second device layer.
In a preferred embodiment, the bonding of the pre-prepared second target compound semiconductor with the first device layer to form a second stacked layer and complete the construction of the second device layer further includes:
at least one first optical lens is structured within the second stack of layers and/or the second dielectric filler layer.
In a third aspect, a micro display is provided, the micro display comprising:
the micro display screen backboard comprises a driving circuit, an input interface and an output interface;
the display area is arranged on the micro display screen backboard, and comprises at least two display units which are arranged in an array mode and are included by the pixel units according to any one of the first aspect;
and the peripheral common cathode is electrically connected with each display unit respectively.
In a fourth aspect, there is provided a pixel level discrete device comprising:
a discrete device backplane comprising at least three anode pads and at least one cathode pad;
the device main body is arranged on the discrete device backboard, and comprises at least two display units which are arranged in an array mode and are included in the pixel unit according to any one of the first aspect.
Compared with the prior art, the application has the following beneficial effects:
the application provides a pixel unit and a manufacturing method thereof, a micro display screen and a pixel separation device, wherein the pixel unit comprises a back plate and a display unit arranged on the back plate; the display unit comprises a first device layer and a second device layer which are sequentially stacked along the direction far away from the backboard, wherein the first device layer comprises a first stacking layer, and the second device layer comprises a second stacking layer; the first stacking layer comprises a first bonding layer and a first compound luminescent layer which are arranged in a bonding way, the second stacking layer comprises a second bonding layer and a second compound luminescent layer which are arranged in a bonding way, the light transmittance of the second bonding layer is not more than 5%, the first compound luminescent layer emits first visible light in a working state, and the second compound luminescent layer emits second visible light which is different from the first visible light in a working state; at least part of the first visible light emitted by the first compound light-emitting layer passes through the second device layer along the vertical direction of the backboard and is transmitted to the outside of the pixel unit; according to the pixel unit, multicolor display is realized by stacking at least two device layers on the backboard, so that the pixel density is improved, the variegated phenomenon caused by photoexcitation is further avoided, the light loss is effectively avoided, and the performance of the pixel unit is improved;
Further, one end of the first anode electrical connection structure is connected with the corresponding anode, the other end of the first anode electrical connection structure penetrates through the first device layer to be connected with the second stacking layer, and projection of the first anode electrical connection structure on the backboard is located in projection of the second stacking layer on the backboard; compared with the mode of constructing the side wall electric connection structure in the prior art, the arrangement mode of the anode electric connection structure can effectively reduce the area of the pixel unit in the horizontal direction and improve the light emergent area occupation ratio of the pixel unit, so that the pixel density is improved;
it should be noted that, the present application only needs to achieve at least one of the above technical effects.
Drawings
Fig. 1 is a top view of a pixel unit in embodiment 1;
FIG. 2 is a cross-sectional view of section A-B of FIG. 1;
fig. 3 is a schematic diagram of an exemplary circuit configuration of the back plate in embodiment 1;
fig. 4 is a schematic diagram of an exemplary circuit configuration of a further back plate in embodiment 1;
FIG. 5 is a schematic circuit diagram of any one of the device layers in example 1;
FIG. 6 is a schematic diagram of the emission color of each device layer corresponding to the pixel cell of FIG. 1;
FIG. 7 is a cross-sectional view of still another section A-B in example 1;
FIG. 8 is a top view of a back plate covered with a dielectric layer;
FIG. 9 is a cross-sectional view of one construction of the back plate of FIG. 8, covered with bonding material, taken along section A-B;
FIG. 10 is a cross-sectional view of yet another configuration of the back plate of FIG. 8, overlaid with bonding material, taken along section A-B;
fig. 11 is a cross-sectional view of a first target compound semiconductor covered with a bonding material;
fig. 12 is a cross-sectional view of the back plate after bonding with the first target compound semiconductor;
FIG. 13 is a schematic view of the structure after the electrical connection via is constructed;
FIG. 14 is a schematic structural diagram after constructing a first device layer;
FIG. 15 is a schematic diagram of the structure after construction of a second device layer;
fig. 16 is a cross-sectional view of a-B section of still another pixel unit in embodiment 2;
FIG. 17 is a schematic diagram of the emission color of each device layer corresponding to the pixel cell of FIG. 16;
FIG. 18 is a schematic diagram of the micro-display in embodiment 3;
fig. 19 is a schematic view showing the structure of a pixel-level discrete device in embodiment 4.
Reference numerals:
100-pixel cell, 101-back plate, 11-anode, 12-first enhancement structure, 102-display cell, 20-first device layer, 21-first stacked layer, 211-first bonding layer, 212-first compound light emitting layer, 213-first P-type ohmic contact layer, 214-first active quantum well layer, 215-first N-type ohmic contact layer, 22-first dielectric fill layer, 30-second device layer, 31-second stacked layer, 32-second dielectric fill layer, 311-second bonding layer, 312-second compound light emitting layer, 313-second P-type ohmic contact layer, 314-second active quantum well layer, 315-second N-type ohmic contact layer, 41-first anode electrical connection structure, 42-second anode electrical connection structure, 50-third device layer, 51-third stacked layer, 511-third bonding layer, 512-third compound light emitting layer, 513-third P-type ohmic contact layer, 514-third active quantum well layer, 515-third N-type ohmic contact layer, 52-third dielectric fill layer, 60-dielectric layer, 70-second enhancement structure, 80-microlens structure, 91-first optical lens, 92-second optical lens, 93-third optical lens, 200-microdisplay screen, 300-driving back plane, 400-display area, 500-peripheral common cathode, 600-external IO interface, 700-pixel level discrete device, 710-discrete device back plane, 720-device body, 730-anode pad.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "connected," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Example 1
As shown in fig. 1 to 15, the present embodiment provides a pixel unit 100, and the pixel unit 100 is used for a semiconductor device including, but not limited to, micro-LEDs, micro-lasers, and other optoelectronic devices. The pixel unit 100 includes a back plate 101 and a display unit 102 disposed on the back plate 101.
Description: fig. 1 is a top view of the pixel unit 100, fig. 2 is a cross-sectional view of the section a-B in fig. 1, and the subsequent structural diagram is also a top view under the current structure or a corresponding cross-sectional view of the section a-B.
The backplate 101 in this embodiment may be an active backplate combining one or more of Thin Film Transistors (TFTs), LTPS low temperature polysilicon, CMOS integrated circuits, high mobility transistors (HEMTs), etc. Specifically, the back plate 101 is provided with a driving circuit, and the driving circuit 10 is provided with at least one anode 11, and an exemplary circuit diagram of the driving circuit is shown in fig. 3 or 4. It should be noted that, the driving circuit in this embodiment is an active driving circuit, and the circuit diagram shown in this embodiment is only a simple schematic diagram. The driving circuit may comprise an active, passive or semi-passive control circuit, such as an exemplary circuit diagram of any of the device layers shown in fig. 5. All anodes included in the driving circuit may be arranged linearly or in an array, and any anode is located in the middle or at the edge of the back plate 101, which is not limited in this embodiment.
In some embodiments, the backplate 101 comprises at least one Top Metal (Top Metal) that covers at least one anode; alternatively, the backplate 101 includes an in-situ mirror disposed on its upper surface that covers or exposes at least one anode. The in-situ mirror may be a metal such as aluminum, gold, silver, etc.; the Bragg reflection layer can also be formed by stacking two or more films with different refractive indexes, such as a lamination of silicon oxide and titanium oxide, a lamination of silicon oxide and aluminum oxide, a lamination of silicon oxide and silicon nitride, and the like; it may also be an ODR total reflection mirror of a metal and dielectric stack, such as at least one combination of silver and silicon oxide, aluminum and aluminum oxide, gold and silicon oxide. Of course, in some embodiments, the backplate 101 includes a Top Via (Top Via) corresponding to each anode 11.
Preferably, as shown in fig. 2, the back plate 101 further comprises a first reinforcing structure 12, the first reinforcing structure 12 being connected to the at least one anode 11. Specifically, the first reinforcing structure 12 is a mirror to provide optical enhancement, or the first reinforcing structure 12 is a metal block structure to dissipate heat to realize thermal enhancement.
In addition, the pixel unit 100 further includes a dielectric layer 60, where the dielectric layer 60 is disposed between the display unit 102 and the back plate 101, and transparent insulating materials such as silicon oxide, silicon nitride, and aluminum oxide may be used. When backplate 101 includes a top via corresponding to each anode 11, a large area metal fill structure is formed around the top via, which may be bare drain, may be buried under dielectric layer 60, for forming a metal reflective or metal-dielectric total reflection structure, wherein the metal material may be gold, silver, aluminum, copper, etc., and the dielectric material may be silicon oxide, silicon nitride, aluminum oxide, etc.
With continued reference to fig. 2, the display unit 102 includes a first device layer 20, a second device layer 30, and an anode electrical connection structure corresponding to the respective device layers stacked in order along a direction away from the backplate 101, where the first device layer 20 includes a first stacked layer 21 and a first dielectric filling layer 22, and the first stacked layer 21 is embedded in the first dielectric filling layer 22. Likewise, the second device layer 30 includes a second stacked layer 31 and a second dielectric filling layer 32, and the second stacked layer 31 is embedded in the second dielectric filling layer 32. And, the anode electrical connection structures corresponding to the device layers outside the display unit 102 are all disposed in the device layers on the opposite inner sides thereof, for example, one end of the first anode electrical connection structure 41 corresponding to the second device layer 30 is connected to the corresponding anode 11, and the other end passes through the first device layer 20 and is connected to the second stacked layer 31.
The first dielectric filling layer 22 and the second dielectric filling layer 32 are made of transparent dielectric materials, so that light rays of the lower device layer can penetrate.
Of course, to achieve enhancement of the illumination intensity of the pixel unit 100 or to form a redundant structure, the pixel unit in this embodiment includes, but is not limited to, a two-layer device layer structure. For example, to realize white light display, the pixel unit 100 in this embodiment further includes a third device layer 50 stacked on a side of the second device layer 30 away from the first device layer 20, where the third device layer 50 includes a third stacked layer 51 and a third dielectric filling layer 52, and the third stacked layer 51 is embedded in the third dielectric filling layer 52. The third dielectric fill 52 is also made of a transparent medium. Similarly, the pixel unit 100 further includes a second anode electrical connection structure 42 corresponding to the third device layer 50, wherein one end of the second anode electrical connection structure 42 is connected to the corresponding anode 11 of the back plate 101, and the other end passes through the first device layer 20 and the second device layer 30 and is connected to the third stacked layer 51, and the second anode electrical connection structure 42 passes through the first device layer 20 and the second device layer 30 and is connected to the third stacked layer 51. Any device layer in this embodiment may be a common pattern or a combination of patterns, such as a quadrilateral, a hexagon, an octagon, a circle, etc., which is not further limited in this embodiment. In a preferred embodiment, a schematic diagram of a top view of an emission color of a pixel unit in an operating state shown in fig. 2 is shown in fig. 6 (fig. 6 is only a schematic diagram of an emission color of each device layer, and does not represent an emission color of the entire pixel unit), where R represents a red light source, G represents a green light source, and B represents a blue light source.
With continued reference to fig. 2, the projection of the first anode electrical connection structure 41 onto the back plate 101 is within the projection of the second stack layer 31 onto the back plate, and the projection of the second anode electrical connection structure 42 onto the back plate 101 is within the projection of the second stack layer 31 onto the back plate 101. That is, in the horizontal direction, the first anode electrical connection structure 41 occupies a lateral area not exceeding the second stacked layer 31, and the second anode electrical connection structure 42 occupies a lateral area not exceeding the third stacked layer 51. In this manner, the first anode electrical connection structure 41 or the second anode electrical connection structure 42 may be disposed perpendicular to the back plate 101 or at an angle, may be disposed extending in the same direction or may be disposed in a bent manner, and in this embodiment, the present invention is not limited thereto, and all electrical connection structures that are structures of the mating device layer are within the scope of the present embodiment.
Therefore, the number of the device layers of the pixel unit 100 in this embodiment is two or more, and for convenience of description, this embodiment uses three device layers as an example for further detailed description, and further, in this embodiment, the first device layer 20, the second device layer 30, and the third device layer 50 included in the pixel unit 100 cooperate to form white light in a working state.
The first stacked layer 21 includes a first bonding layer 211 and a first compound light-emitting layer 212 which are bonded together, the second stacked layer 31 includes a second bonding layer 311 and a second compound light-emitting layer 312 which are bonded together, and the third stacked layer 51 includes a third bonding layer 511 and a third compound light-emitting layer 512 which are bonded together. In order to realize white light color matching, as shown in fig. 2 and 6, the first compound light emitting layer 212 is formed by using a red light compound epitaxy and emits a first visible light (red light) in an operating state, the second compound light emitting layer 312 is formed by using a green light compound epitaxy and emits a second visible light (green light) in an operating state, and the second compound light emitting layer 312 is formed by using a blue light compound epitaxy and emits a third visible light (blue light) in an operating state.
The first bonding layer 211, the second bonding layer 311 and the third bonding layer 511 are made of conductive materials, such as compound materials as ITO, znO, gaP, gaAs, gaN, or metals or alloys as Au, al, cu, sn, and adhesion layers including Cr, ti, etc. The light transmittance of the second bonding layer 311 is not more than 5%, the light transmittance of the third bonding layer 511 is not more than 5%, and the generated light cannot be transmitted to the first compound light emitting layer 212 in the single operation state of the second compound light emitting layer 312 or the third compound light emitting layer 512 with higher energy (short wavelength light source), so as to avoid the problem of variegated color caused by the excitation of the first compound light emitting layer 212 in the single operation state of the second compound light emitting layer 312 or the third compound light emitting layer 512.
The first dielectric filling layer 22, the second dielectric filling layer 32 and the third dielectric filling layer 52 are made of insulating transparent materials, such as silicon oxide, silicon nitride, aluminum oxide, etc., which have better light transmittance.
On the basis of this, at least part of the first visible light emitted from the first compound light-emitting layer 212 passes through the second device layer 30 and the third device layer 50 in the vertical direction of the back plate 101 and is transmitted to the outside of the pixel unit 100, and/or at least part of the second visible light emitted from the second compound light-emitting layer 312 passes through the third device layer 50 in the vertical direction of the back plate 101 and is transmitted to the outside of the pixel unit 100.
To achieve this, as shown in fig. 2, at least part of the first stacked layers 21 do not coincide with the projection of at least part of the second stacked layers 31 onto the back plate 101, more preferably, at least part of the first stacked layers 21, at least part of the second stacked layers 31 and at least part of the third stacked layers 51 do not coincide with the projection of at least part of the second stacked layers 31 onto the back plate 101. That is, the first stacked layer 21, the second stacked layer 31, and the third stacked layer 51 are arranged offset from each other in the vertical direction of the back plate 101. The dislocation arrangement mode facilitates that at least part of the first visible light emitted by the first compound light-emitting layer 212 passes through the second medium filling layer 32 along the vertical direction of the back plate 101 to be transmitted outwards, so that the visible light emitted by the lower device layer passes through the upper device layer and passes through the light-emitting surface of the pixel unit 100.
Further, the pixel unit 100 further includes a second reinforcing structure 70 surrounding the display unit 102. The second enhancement structure 70 serves to enhance common cathode current spreading and inter-pixel optical isolation, as well as to enhance current spreading.
Further, the first compound light emitting layer 212 includes a first P-type ohmic contact layer 213, a first active quantum well layer 214, and a first N-type ohmic contact layer 215, which are sequentially disposed. The second compound light emitting layer 312 includes a second P-type ohmic contact layer 313, a second active quantum well layer 314, and a second N-type ohmic contact layer 315 sequentially disposed. The third compound light emitting layer 512 includes a third P-type ohmic contact layer 513, a third active quantum well layer 514, and a third N-type ohmic contact layer 515, which are sequentially disposed. The first N-type ohmic contact layer 215, the second N-type ohmic contact layer 315 and the third N-type ohmic contact layer 515 extend and are respectively connected to the second reinforcing structure 70, and the first N-type ohmic contact layer 215 is made of a transparent conductive material such as AlGaAs, gaN, ITO or ZnO. In this embodiment, the second reinforcing structure 70 is made of Cu, al, or other metal. As a preferred example, any of the N-type ohmic contact layers of the present embodiment is made of a transparent conductive material such as ITO. In this embodiment, the N-type ohmic contact layer of each device layer is set to be transparent, so that light emitted from the device layer and the device layer below the device layer is prevented from being blocked when the N-type ohmic contact layer extends to the second enhancement structure 70 in the device layer.
The first active quantum well layer 214, the second active quantum well layer 314 and the third active quantum well layer 514 refer to quantum well active quantum well layers, for example, the first active quantum well layer 214 adopts an InGaN ternary material system or a quaternary AlGaInP red compound LED epitaxy of GaAs substrate. The second active quantum well layer 214 or the third active quantum well layer 514 employs InGaN ternary compound. The materials of the first P-type ohmic contact layer 213, the second P-type ohmic contact layer 313, and the third P-type ohmic contact layer 513 may be transparent conductive materials such as ITO, or may be a laminate or alloy of metal materials such as Au, ni, ag, mg. The first P-type ohmic contact layer 213 is formed on the first active quantum well layer by vapor deposition, sputtering or the like214, and preferably, the ITO film is formed by a thickness of 500nm by N 2 And annealing at 500 ℃ in the environment to form ohmic contact.
Exemplary, the first compound light-emitting layer 212 structure is shown in table 1 below:
TABLE 1
Layer name Material of material
P-type ohmic contact layer P-GaAs
Active quantum well layer AlGaInP
N-type ohmic contact layer AlGaAs
And, the second compound light emitting layer 312 or the third compound light emitting layer 512 has a structure as shown in one of the following tables 2 or 3, respectively:
TABLE 2
Layer name Material of material
P-type ohmic contact layer P-GaAs
Active quantum well layer InGaN&GaN
N-type ohmic contact layer GaN
TABLE 3 Table 3
Layer name Material of material
P-type ohmic contact layer P-GaN
Active quantum well layer InGaN&GaN
N-type ohmic contact layer GaN
In a specific implementation process, the size and shape of each layer of compound device can be adjusted according to the white light color matching requirement, such as matching any regular or irregular shape of square, round, etc., and exemplary light source color distribution is shown in fig. 6.
In a preferred embodiment, as shown in fig. 7, the pixel unit 100 further includes a microlens structure 80, and the microlens structure 80 is disposed on a surface of the display unit 102 away from the back plate 101. Generally, the microlens structure 80 is a hemispherical structure to improve the optical characteristics of the pixel cell 100.
Corresponding to the pixel unit 100, the present embodiment further provides a pixel unit manufacturing method, which includes the following steps:
s1, preparing a backboard, and as shown in FIG. 8, plating an insulating material on the surface of the backboard provided with at least one anode to form a dielectric layer.
Specifically, the back plate may be an active back plate formed by one or a combination of a Thin Film Transistor (TFT), low Temperature Polysilicon (LTPS), CMOS (integrated circuit), and high mobility transistor (HEMT), and the CMOS is preferably used as the back plate in this embodiment, and includes at least one anode. For example, in the pixel unit with white light color matching function, the plurality of anodes arranged on the back plate at least comprise an R anode, a G anode and a B anode. Of course, the surface of the back plate is provided with at least one top metal covering the anode or an in-situ mirror provided on the surface of the back plate.
In one embodiment, as shown in fig. 9 and 10, a first reinforcing structure, such as an optical reinforcing structure or a thermal reinforcing structure, is previously constructed in the back plate. Illustratively, the first reinforcing structure is configured to be coupled to the R anode, and the G/B anode is isolated separately, and the first reinforcing structure is electrically functional to the R anode.
The dielectric layer is plated on the surface of the backboard in a film plating mode, and then corresponding through holes are formed at positions corresponding to the anodes. The dielectric layer is made of one or more of silicon oxide, silicon nitride and aluminum oxide.
S2, preparing a first target compound semiconductor, and manufacturing a first P-type ohmic contact layer on the surface of the first target compound semiconductor, as shown in FIG. 11.
The first target compound semiconductor includes a first active quantum well layer and a corresponding substrate. In this embodiment, the first active quantum well layer is an AlGaInP red light system compound, and the substrate is preferably N-GaAs.
In one embodiment, the first P-type ohmic contact layer may be made of transparent conductive material such as ITO, znO, or a laminate or alloy of metal materials such as Ni, au, ag, or the like. The first P-type ohmic contact layer is formed by vapor deposition, sputtering and the likeITO coating film, ITO film thickness 110nm, through N 2 And annealing at 550 ℃ in the environment to form ohmic contact. Of course, the thickness of the first P-type ohmic contact layer and the conditions for forming the contact may be adjusted and changed as required.
And S3, bonding the backboard with the first target compound semiconductor and removing the substrate of the first target compound semiconductor.
In this embodiment, the back plate is bonded to the first target compound semiconductor to form a conductive and opaque first bonding layer. Illustratively, cr10nm and/or Au100nm are sputtered or evaporated on the bonding surface of the back plate and the first target compound semiconductor, respectively. After performing surface planarization treatment by CMP to make the surface roughness less than or equal to 10nm, treating for 30s in Ar plasma atmosphere with the power of 30W, activating the surface of the bonding layer by using the plasma surface to make the surface hydrophilic, and then performing first-layer compound stacking at normal temperature, namely performing relative bonding to form an intermediate product structure after the first bonding layer backboard is bonded with the first target compound semiconductor and the substrate of the first target compound semiconductor is removed, wherein the cross section of the intermediate product structure in the section A-B is shown in figure 12.
And S4, exposing the first N-type ohmic contact layer through etching or polishing to form a first stacked layer.
Specifically, the first N-type ohmic contact layer is exposed by employing wet etching to an Etch Stop layer (Etch Stop) or dry etching, as shown in fig. 13.
S5, filling the first dielectric filling layer and constructing a corresponding electric connection structure to form a first device layer.
The step S5 is implemented by adopting a damascene-like process. Specifically, step S5 includes:
s51, filling the first dielectric filling layer for the first time, wherein the upper surface of the first dielectric filling layer exceeds the first N-type ohmic contact layer.
And S52, performing patterning treatment on the first dielectric filling layer obtained in the step S51 to obtain an anode electrical connection channel corresponding to the upper device layer and a cathode electrical connection channel for connecting the first N-type ohmic contact layer and the second circumferential reinforcing structure.
And S53, filling the anode electrical connection channel and the cathode electrical connection channel obtained in the step S52 to form corresponding anode electrical connection structures, and completing connection between the first N-type ohmic contact layer and the second enhancement structure.
And S54, filling the first dielectric filling layer for the second time so that the first dielectric filling layer covers the first N-type ohmic contact layer.
The first device layer is constructed as described above, and the cross-sectional structure thereof is shown in fig. 14.
When the pixel unit further includes a second reinforcing structure disposed in the circumferential direction of the display unit, the steps S52 to S53 further include constructing a second reinforcing structure channel disposed in the circumferential direction of the display unit and corresponding to the second reinforcing structure, and filling the second reinforcing structure layer by layer with a metal material to form a second reinforcing structure.
S6, preparing a second target compound semiconductor, and repeating the steps S2-S5 to construct a second device layer. The second target compound semiconductor in this step is Si, sapphire, ga-based 2 O 3 InGaN ternary compounds (green compounds) of the substrate.
Specifically, step S6 includes:
s61, preparing a second target compound semiconductor, and manufacturing a second P-type ohmic contact layer on the surface of the second target compound semiconductor.
And S62, bonding the first device layer and the second target compound semiconductor, and removing the substrate of the second target compound semiconductor.
And S63, exposing the second N-type ohmic contact layer through etching or polishing to form a second stacked layer.
S64, filling the second dielectric filling layer and constructing a corresponding electric connection structure to form a second device layer, wherein the cross-sectional structure of the second device layer is shown in FIG. 15. The specific steps of this step S64 refer to the specific procedure of step S5.
When the pixel unit includes only two device layers, the display unit is constructed in step S6. When the fabricated pixel unit includes three or more device layers, the following step S7 is performed.
S7, preparing a third target compound semiconductor, and repeating the steps S2-S5 to construct a third device layer. The second target compound semiconductor in this step is Si, sapphire, ga-based 2 O 3 InGaN ternary compounds (blue compounds) of the substrate.
Specifically, step S7 includes:
and S71, preparing a third target compound semiconductor, and manufacturing a third P-type ohmic contact layer on the surface of the third target compound semiconductor.
And S72, bonding the second device layer with the third target compound semiconductor and removing the substrate of the third target compound semiconductor.
And S73, exposing the third N-type ohmic contact layer through etching or polishing to form a third stacked layer.
And S74, filling the third dielectric filling layer and constructing a corresponding electric connection structure to form a third device layer, wherein the cross-sectional structure of the third device layer is shown in fig. 2.
After the construction of all the device layers is completed, preferably, a microlens structure is constructed on the surface of the outermost device layer, and the microlens structure may be formed by thickening the transparent dielectric layer of the last device layer and forming a specific convex surface, concave surface or plane, and performing planarization treatment. The microlens structure in this embodiment is a hemispherical structure, and a sectional view of the a-B section thereof is shown in fig. 7.
In summary, the pixel unit in this embodiment realizes multicolor display by stacking at least two device layers on the back plate to improve pixel density, so as to further avoid the variegated phenomenon caused by photoexcitation and effectively avoid optical loss, thereby improving the performance of the pixel unit;
Compared with the mode of constructing the side wall electric connection structure in the prior art, the arrangement mode of the anode electric connection structure in the embodiment can effectively reduce the area of the pixel unit in the horizontal direction and improve the light emitting area occupation ratio of the pixel unit, so that the pixel density is improved.
Example 2
Referring to fig. 16, the present embodiment provides yet another pixel unit 100, and the pixel unit 100 has substantially the same structure as the pixel unit 100 in embodiment 1, except that: at least part of the first stack 21 coincides with the projection of at least part of the second stack 31 onto the back plate 101; the second device layer 30 further includes at least one first optical lens 91, and one side of any first optical lens 91 is connected to the first N-type ohmic contact layer 215, and the other side is connected to the second N-type ohmic contact layer 315 included in the second stacked layer 31. When the pixel unit 100 further includes a third device layer, the third device layer 50 further includes at least one second optical lens 92, one side of any second optical lens 92 is connected to the second N-type ohmic contact layer 315, and the other side is connected to the third N-type ohmic contact layer 515 included in the third stacked layer 51; the projection of at least part of the first optical lens 91 onto the back plate coincides with the projection of at least part of the corresponding second optical lens 92 onto the back plate 101.
When the dielectric filling layer of each device layer is made of a transparent dielectric material, the first optical lens 91 is connected to the first N-type ohmic contact layer 215 or the second N-type ohmic contact layer 315 through the first dielectric filling layer 22 with a smaller thickness. The optical lenses of the other device layers are arranged in a similar manner to the first optical lens 91.
When each device layer is made of an insulating material having low light transmittance, the first optical lens 91 is directly connected to the first N-type ohmic contact layer 215, and the first optical lens 91 is directly connected to the second N-type ohmic contact layer 315. The optical lenses of the other device layers are arranged in a similar manner to the first optical lens 91. The third device layer 50 further includes at least one third optical lens 93, where one side of any third optical lens 93 is connected to the third N-type ohmic contact layer 315, and the other side is connected to the third N-type ohmic contact layer 515 included in the third stacked layer 51; the projection of at least part of the first optical lens 91 onto the back plate coincides with the projection of at least part of the corresponding second optical lens 92 onto the back plate 101.
Preferably, when the device layer included in the pixel unit 100 includes three or more layers, the plurality of optical lenses corresponding to the same device layer are located in the same vertical direction of the back plate 101 and have the same cross-sectional area, so as to avoid any optical lens from causing a loss of light emitting area to the device layer where it is located.
In the above manner, the optical lenses are respectively disposed in the rest of the device layers except the first device layer 20 (i.e. stacked above the first device layer 20) in the display unit 102, so that the light emitted by the first device layer 20 and the second device layer 30 in the working state is transmitted to the outside through one or more optical lenses to form the light source.
Further, compared to embodiment 1, the display unit 102 in this embodiment includes the first stacked layer 21, the second stacked layer 31, and the third stacked layer 51, and the light emitting areas between the two stacked layers do not affect each other, and no misalignment or avoidance arrangement is required. In the implementation process, the preset light emitting requirement can be realized by adjusting the cross section area and the shape of each optical lens in the horizontal direction and the optical parameters of the optical lenses. Further, when the first stacked layer 21, the second stacked layer 31 and the third stacked layer 51 extend to the maximum area in the horizontal direction, and the projected edges of the three on the back plate 101 overlap, the pixel size of each device layer reaches the maximum.
In this structure, the color of the light source emitted by each device layer is shown in fig. 17, specifically, the first device layer 20 includes two columns of red light sources arranged in a column, the second device layer 30 includes one column of green light sources, and the third device layer 50 is a full-face blue light source.
Similarly, the present embodiment also provides a method for manufacturing a pixel unit corresponding to the pixel unit 100. The manufacturing method is different from the manufacturing method of the pixel unit described in the previous embodiment in that:
when the pixel unit includes only two device layers, step S6 further includes:
s65, constructing at least one first optical lens in the second stacked layer and/or the second medium filling layer.
Specifically, after the second dielectric filling layer is filled, at least one corresponding hollow channel is constructed in the second stacking layer and/or the second dielectric filling layer according to the mode of constructing the electrical connection channel, and the first optical lens is formed by filling the transparent dielectric material into the at least one hollow channel.
It should be noted that, when the dielectric filling layer of any device layer is made of a transparent dielectric material, the hollowed-out channel extends downward to a portion of the dielectric filling layer near the N-type ohmic contact layer. When any dielectric filling layer is made of a dielectric material with low light transmittance, the hollowed-out channel extends downwards to the N-type ohmic contact layer of the device layer below the hollowed-out channel.
After the construction of the optical lens is completed, the N-type ohmic contact layer filling construction of the corresponding device layer and the subsequent construction of the medium filling layer are further completed, and finally the construction of the current device layer is completed.
When the pixel unit includes at least three device layers, step S7 further includes:
s75, constructing at least one second optical lens and at least one third optical lens in the third stacking layer and/or the third medium filling layer. The second optical lens is vertically corresponding to the first optical lens, so that the light-emitting line of the first stacked layer is emitted from the light-emitting surface through the second optical lens and the first optical lens. And a third optical lens for transmitting and emitting light emitted from the second stacked layer from the light emitting surface.
In the pixel unit with white light color matching requirement, the number and positions of the first optical lens, the second optical lens and the third optical lens are adjusted according to the color matching requirement, and any setting mode is within the implementation range of the embodiment.
Example 3
The present embodiment provides a micro display 200, as shown in fig. 18, the micro display 200 includes:
the driving backboard 300, the driving backboard 300 comprises at least two driving circuits, an input interface and an output interface;
the display area 400 is disposed on the driving backboard 300, and the display area 400 includes at least two display units 102 as in embodiment 1, and at least two display units 102 are arranged in an array;
The peripheral common cathode 500, the peripheral common cathode 500 is electrically connected to the second reinforcing structure 70 of each display unit 102, respectively, so that the entire micro display 200 is common to the cathodes. It should be noted that, the peripheral common cathode 500 is a metal frame structure surrounding the display area 400.
The external IO interface 600 is located at an arbitrary position of the driving backplate 300.
Further, the arrangement direction of each pixel unit 100 in the micro display 200 that is arranged adjacently is not limited in this embodiment.
The specific structure and corresponding technical effects of the micro display in this embodiment are described in detail with reference to embodiment 1 or 2, and will not be described in further detail in this embodiment.
Example 4
As shown in fig. 19, the present embodiment provides a pixel-level discrete device 700, the pixel-level discrete device 700 including:
a discrete device backplane 710, the discrete device backplane 710 comprising at least three anode pads 730 and at least one cathode pad (not shown);
the device body 720, the device body 720 is disposed on the discrete device back plane 710, and the device body 720 includes at least two display units 102 as the pixel units in embodiment 1 or 2, and at least two display units 102 are arranged in an array.
At least two bonding pads, including one cathode bonding pad 740 and at least one anode bonding pad 730, at least a portion of any anode bonding pad 730 and at least a portion of the cathode bonding pad are embedded in the discrete device back plate 710, respectively, any anode electrical connection structure is connected with the corresponding anode bonding pad 730, and the cathode electrical connection structure is connected with the corresponding cathode bonding pad 740.
All the above-mentioned optional technical schemes can be combined arbitrarily to form optional embodiments of the application, and any plurality of embodiments can be combined, so that the requirements for coping with different application scenes are obtained, and are all within the protection scope of the application, and are not described in detail herein.
It should be noted that the foregoing description is only a preferred embodiment of the present application, and is not intended to limit the present application, but any modifications, equivalents, improvements, etc. within the spirit and principles of the present application are intended to be included in the scope of the present application.

Claims (13)

1. The pixel unit is characterized by comprising a back plate and a display unit arranged on the back plate;
the display unit comprises a first device layer and a second device layer which are sequentially stacked along a direction far away from the backboard, wherein the first device layer comprises a first stacking layer, and the second device layer comprises a second stacking layer;
The first stacking layer comprises a first bonding layer and a first compound light-emitting layer which are arranged in a bonding mode, the second stacking layer comprises a second bonding layer and a second compound light-emitting layer which are arranged in a bonding mode, the light transmittance of the second bonding layer is not more than 5%, the first compound light-emitting layer emits first visible light in a working state, and the second compound light-emitting layer emits second visible light which is different from the first visible light in the working state;
at least part of the first visible light emitted by the first compound light-emitting layer passes through the second device layer along the vertical direction of the backboard and is transmitted to the outside of the pixel unit;
the pixel unit further comprises a second reinforcing structure which is arranged around the circumference of the display unit;
the first compound light-emitting layer comprises a first P-type ohmic contact layer, a first active quantum well layer and a first N-type ohmic contact layer;
the first N-type ohmic contact layer extends and is connected with the second reinforcing structure, and the first N-type ohmic contact layer is made of transparent conductive materials.
2. The pixel unit according to claim 1, wherein the display unit further comprises a third device layer disposed on a side of the second device layer away from the first device layer, the third device layer comprising a third stacked layer, the third stacked layer comprising a third bonding layer and a third compound light-emitting layer disposed in a bonded manner, the third bonding layer having a light transmittance of not more than 5%, the third compound light-emitting layer emitting third visible light in an operating state;
At least a portion of the first visible light emitted from the first compound light-emitting layer passes through the second device layer and the third device layer in a vertical direction of the back plate and is transmitted to the outside of the pixel unit, and/or,
and at least part of the second visible light emitted by the second compound light-emitting layer passes through the third device layer along the vertical direction of the backboard and is transmitted to the outside of the pixel unit.
3. A pixel cell according to claim 2, wherein the back plate is provided with a drive circuit, the drive circuit being provided with at least one anode; the display unit further includes a first anode electrical connection structure;
one end of the first anode electrical connection structure is connected with the corresponding anode, the other end of the first anode electrical connection structure penetrates through the first device layer to be connected with the second stacking layer, and projection of the first anode electrical connection structure on the backboard is located in projection of the second stacking layer on the backboard.
4. A pixel cell as claimed in claim 3, wherein the back plate further comprises a first reinforcing structure, the first reinforcing structure being connected to at least one of the anodes;
the pixel unit further comprises a dielectric layer, and the dielectric layer is arranged between the display unit and the backboard.
5. The pixel cell of claim 3, wherein the first device layer further comprises a first dielectric fill layer, the first stack layer and the first anode electrical connection structure are both embedded within the first dielectric fill layer; the second device layer further comprises a second dielectric filling layer, and the second stacking layer is embedded in the second dielectric filling layer; the third device layer further comprises a third dielectric filling layer, and the third stacking layer is embedded in the third dielectric filling layer;
the first medium filling layer, the second medium filling layer and the third medium filling layer are all made of transparent medium materials.
6. The pixel cell of claim 5, wherein at least a portion of the first stacked layer is misaligned with a projection of at least a portion of the second stacked layer onto the back plate, and wherein at least a portion of the first visible light emitted by the first compound light emitting layer is transmitted outward through the second dielectric fill layer in a direction perpendicular to the back plate.
7. A pixel cell as claimed in claim 3, wherein at least part of the first stack layer coincides with the projection of at least part of the second stack layer onto the back plate;
The second device layer further comprises at least one first optical lens, one side of any first optical lens is connected with the first N-type ohmic contact layer, and the other side of any first optical lens is connected with a second N-type ohmic contact layer included in the second stacked layer;
the third device layer further comprises at least one second optical lens, one side of any second optical lens is connected with the second N-type ohmic contact layer, and the other side of any second optical lens is connected with a third N-type ohmic contact layer included in the third stacked layer;
at least a portion of the projection of the first optical lens onto the back plate coincides with at least a portion of the corresponding projection of the second optical lens onto the back plate.
8. The method for manufacturing a pixel unit according to any one of claims 1 to 7, wherein the method for manufacturing the pixel unit comprises:
preparing a backboard;
fabricating a display unit, bonding a first target compound semiconductor prepared in advance with the back plate to form a first stacked layer and constructing to form the first device layer; bonding a previously prepared second target compound semiconductor with the first device layer to form a second stacked layer and configuring to form the second device layer; the second bonding layer included in the second stacked layer has a light transmittance of not more than 5%, the first compound light-emitting layer included in the first stacked layer emits first visible light in a working state, and the second compound light-emitting layer emits second visible light different from the first visible light in the working state; at least part of the first visible light emitted by the first compound light-emitting layer passes through the second device layer along the vertical direction of the back plate and is transmitted to the outside of the pixel unit.
9. The method of manufacturing of claim 8, wherein bonding the pre-prepared first target compound semiconductor to the backplate to form a first stacked layer and to construct the first device layer comprises:
plating an insulating material on the surface of the backboard provided with at least one anode to form a dielectric layer;
manufacturing a first P-type ohmic contact layer on the surface of the first target compound semiconductor;
bonding the back plate with the first target compound semiconductor and removing the substrate of the first target compound semiconductor;
exposing the first N-type ohmic contact layer through etching or polishing to form a first stacked layer;
and filling the first dielectric filling layer and constructing a corresponding electric connection structure to form the first device layer.
10. The method of manufacturing of claim 9, wherein bonding the previously prepared second target compound semiconductor to the first device layer to form a second stacked layer and to construct the second device layer comprises:
manufacturing a second P-type ohmic contact layer on the surface of the second target compound semiconductor;
bonding the first device layer with the second target compound semiconductor and removing the substrate of the second target compound semiconductor;
Exposing the second N-type ohmic contact layer through etching or polishing to form a second stacked layer;
and filling a second dielectric filling layer and constructing a corresponding electric connection structure to form the second device layer.
11. The method of manufacturing of claim 10, wherein bonding the pre-prepared second target compound semiconductor to the back plate to form a second stacked layer and complete the constructing of the second device layer, further comprises:
at least one first optical lens is structured within the second stack of layers and/or the second dielectric filler layer.
12. The micro display screen, its characterized in that, micro display screen includes:
the micro display screen backboard comprises a driving circuit, an input interface and an output interface;
the display area is arranged on the micro display screen backboard, and comprises at least two display units which are arranged in an array mode and are included by the pixel units according to any one of claims 1-7;
and the peripheral common cathode is electrically connected with each display unit respectively.
13. A pixel level discrete device, characterized in that the pixel level discrete device comprises:
A discrete device backplane comprising at least three anode pads and at least one cathode pad;
the device main body is arranged on the discrete device backboard, and comprises at least two display units which are arranged in an array mode and are included in the pixel unit according to any one of claims 1-7.
CN202310389702.2A 2023-04-13 2023-04-13 Pixel unit, manufacturing method thereof, micro display screen and pixel split device Active CN116130504B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310389702.2A CN116130504B (en) 2023-04-13 2023-04-13 Pixel unit, manufacturing method thereof, micro display screen and pixel split device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310389702.2A CN116130504B (en) 2023-04-13 2023-04-13 Pixel unit, manufacturing method thereof, micro display screen and pixel split device

Publications (2)

Publication Number Publication Date
CN116130504A CN116130504A (en) 2023-05-16
CN116130504B true CN116130504B (en) 2023-07-04

Family

ID=86303033

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310389702.2A Active CN116130504B (en) 2023-04-13 2023-04-13 Pixel unit, manufacturing method thereof, micro display screen and pixel split device

Country Status (1)

Country Link
CN (1) CN116130504B (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210086336A (en) * 2019-12-31 2021-07-08 엘지디스플레이 주식회사 Display Panel and Head Mounted Display Device Having the Same Therein
CN114725150B (en) * 2022-03-14 2023-10-03 湖南大学 Micro-LED device and Micro display screen
CN115064528B (en) * 2022-04-29 2023-06-16 诺视科技(苏州)有限公司 Pixel unit for semiconductor device, manufacturing method thereof and micro display screen
CN115084107B (en) * 2022-04-29 2023-05-05 诺视科技(苏州)有限公司 Pixel-level discrete device and manufacturing method thereof
CN114899298B (en) * 2022-07-12 2022-10-25 诺视科技(苏州)有限公司 Pixel unit and manufacturing method thereof, micro display screen and discrete device
CN114899286B (en) * 2022-07-12 2022-10-25 诺视科技(苏州)有限公司 Pixel-level discrete device and manufacturing method thereof
CN114899291B (en) * 2022-07-12 2022-10-25 诺视科技(苏州)有限公司 Pixel unit for semiconductor device, manufacturing method thereof and micro display screen
CN115332288A (en) * 2022-08-24 2022-11-11 诺视科技(苏州)有限公司 Pixel unit and manufacturing method thereof, micro display screen and discrete device

Also Published As

Publication number Publication date
CN116130504A (en) 2023-05-16

Similar Documents

Publication Publication Date Title
US11804511B2 (en) Light emitting device with LED stack for display and display apparatus having the same
US11557577B2 (en) Light emitting device with LED stack for display and display apparatus having the same
US20200066690A1 (en) Led unit for display and display apparatus having the same
JP2021504959A (en) Light emitting diode for display and display device having it
CN115064528B (en) Pixel unit for semiconductor device, manufacturing method thereof and micro display screen
CN114899291B (en) Pixel unit for semiconductor device, manufacturing method thereof and micro display screen
CN115332288A (en) Pixel unit and manufacturing method thereof, micro display screen and discrete device
CN116153962B (en) Pixel unit, manufacturing method thereof, micro display screen and pixel split device
CN219303699U (en) Pixel unit for semiconductor device, micro display screen and pixel split device
CN116130504B (en) Pixel unit, manufacturing method thereof, micro display screen and pixel split device
CN220065700U (en) Pixel unit, micro display screen and pixel split device
CN116404028B (en) Pixel unit, manufacturing method thereof, micro display screen and pixel split device
CN116247072B (en) Pixel unit, manufacturing method thereof, micro display screen and pixel split device
CN116564950A (en) Pixel unit, manufacturing method thereof, micro display screen and pixel split device
US11437353B2 (en) Light emitting device for display and display apparatus having the same
US20220336428A1 (en) Light emitting diode and display apparatus having the same
CN117352625B (en) Micro LED micro display chip and preparation method
US11756940B2 (en) Light emitting device for display and display apparatus having the same
US20230197693A1 (en) Micro led display apparatus and method of manufacturing the same
CN117096246A (en) Micro light emitting diode display screen and preparation method thereof
CN117558859A (en) Anti-crosstalk micro-display luminous pixel, manufacturing method thereof and micro-display screen
CN117790659A (en) Micro-display luminous pixel with omnibearing reflecting mirror structure and its making method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant