CN116130420A - Method for reducing damage of work function layer of HKMG device - Google Patents

Method for reducing damage of work function layer of HKMG device Download PDF

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Publication number
CN116130420A
CN116130420A CN202310245663.9A CN202310245663A CN116130420A CN 116130420 A CN116130420 A CN 116130420A CN 202310245663 A CN202310245663 A CN 202310245663A CN 116130420 A CN116130420 A CN 116130420A
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work function
layer
function layer
metal
dielectric layer
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CN202310245663.9A
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Chinese (zh)
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许任辉
伏广才
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202310245663.9A priority Critical patent/CN116130420A/en
Publication of CN116130420A publication Critical patent/CN116130420A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a method for reducing damage of a work function layer of an HKMG device, which comprises the following steps: step 1) providing a semiconductor structure, which comprises a substrate and a grid structure of a plurality of semiconductor devices formed on the substrate, wherein the grid structure comprises a laminated structure of a grid dielectric layer, a work function layer and a metal grid, and the work function layer is formed between the grid dielectric layer and the metal grid and is U-shaped and positioned on the side wall and the bottom of the metal grid; step 2) selectively growing a metal barrier layer on the surface of the work function layer and the metal gate; step 3) forming a dielectric layer on the surface of the structure formed in the step 2); step 4) patterning and etching the dielectric layer to form a contact hole above the metal gate. The invention solves the problem that the threshold voltage is shifted due to damage to the work function layer in the process of forming the contact hole of the existing HKMG device.

Description

Method for reducing damage of work function layer of HKMG device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing damage of a work function layer of an HKMG device.
Background
In the existing semiconductor industry, polysilicon is widely used as a standard gate fill material in semiconductor devices (e.g., MOS transistors). However, as the size of the MOS transistor decreases, the device performance of the conventional polysilicon gate decreases due to the boron penetration effect, and the depletion effect, which is difficult to avoid, increases the equivalent gate dielectric layer thickness and decreases the gate capacitance, thereby degrading the device performance. Accordingly, the semiconductor industry has attempted to replace conventional polysilicon gates with new gate fill materials, such as Work Function (WF) metal layers, for use as control electrodes for matching high dielectric constant (HK) gate dielectric layers, i.e., metal Gates (MG). HKMG has a gate dielectric layer of high dielectric constant (HK) and a Metal Gate (MG), and is commonly abbreviated in the art as HKMG.
However, during the formation of the contact hole of the semiconductor element through photolithography, etching and cleaning processes, the metal gate and the work function metal layer are easily damaged, thereby causing the threshold voltage drift of the device.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a method for reducing damage to a work function layer of an HKMG device, which is used for solving the problem that the threshold voltage shifts due to damage to the work function layer in the process of forming a contact hole in the conventional HKMG device.
To achieve the above and other related objects, the present invention provides a method of reducing damage to a work function layer of an HKMG device, the method comprising:
step 1) providing a semiconductor structure, which comprises a substrate and a grid structure of a plurality of semiconductor devices formed on the substrate, wherein the grid structure comprises a laminated structure of a grid dielectric layer, a work function layer and a metal grid, and the work function layer is formed between the grid dielectric layer and the metal grid and is U-shaped and positioned on the side wall and the bottom of the metal grid;
step 2) selectively growing a metal barrier layer on the surface of the work function layer and the metal gate;
step 3) forming a dielectric layer on the surface of the structure formed in the step 2);
step 4) patterning and etching the dielectric layer to form a contact hole above the metal gate;
the semiconductor device comprises a PMOS tube and an NMOS tube, wherein the PMOS tube and the NMOS tube have the same grid structure.
Optionally, the material of the metal barrier layer includes at least one of Co, W, pb, or TiSi.
Optionally, the thickness of the metal barrier layer comprises 20 angstroms to 50 angstroms.
Optionally, the metal barrier layer is formed using an atomic layer deposition process or an electroplating process while step 2) is performed.
Optionally, the work function layer of the NMOS tube is made of TiAl, and the work function layer of the PMOS tube is made of TiAlC.
Optionally, the gate dielectric layer is a high-K dielectric layer.
Optionally, the material of the metal gate includes metal Al or metal W.
Optionally, the semiconductor structure further includes a side wall, a stop layer and an interlayer dielectric layer, the side wall is formed on the side wall of the gate structure, and the stop layer is formed between the side wall and the interlayer dielectric layer.
Optionally, a source region and a drain region of the NMOS transistor and a source region and a drain region of the PMOS transistor are formed in the substrate.
Optionally, when the step 4) is executed, the contact hole is formed above the source region and the drain region of the NMOS transistor and above the source region and the drain region of the PMOS transistor by etching the dielectric layer.
Optionally, the gate structure further includes a gate blocking layer formed between the gate dielectric layer and the work function layer.
Optionally, after step 4), the method further comprises a step of wet cleaning the structure formed in step 4).
As described above, the method for reducing the damage of the work function layer of the HKMG device protects the metal gate and the work function layer by forming the metal protection layer on the surfaces of the metal gate and the work function layer, so as to prevent the metal gate and the work function layer from being damaged by boundary effect brought by subsequent processes and avoid the threshold voltage drift of the device.
Drawings
Fig. 1 shows a flow chart of a method of reducing work function layer damage in HKMG devices of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor structure according to the present invention.
Fig. 3 is a schematic cross-sectional view of the semiconductor structure after forming a metal barrier layer on the surface of the semiconductor structure according to the present invention.
Fig. 4 is a schematic cross-sectional view of the dielectric layer according to the present invention.
Fig. 5 is a schematic cross-sectional view of the present invention after forming a contact hole.
Description of the reference numerals
10: a semiconductor structure; 11: a substrate; 12: a gate structure; 121: a gate dielectric layer; 122: a work function layer; 123: a metal gate; 124: a gate barrier layer; 13: a side wall; 14: a stop layer; 15: an interlayer dielectric layer; 16: shallow trench isolation structures; 20: a metal barrier layer; 30: a dielectric layer; 40: a contact hole; 51: a first source region; 52: a first drain region; 61: a second source region; 62: second drain region
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the embodiment provides a method for reducing damage to a work function layer of an HKMG device, where the method includes:
step 1) providing a semiconductor structure 10, which comprises a substrate 11 and a gate structure 12 of a plurality of semiconductor devices formed on the substrate 11, wherein the gate structure 12 comprises a laminated structure of a gate dielectric layer 121, a work function layer 122 and a metal gate 123, and the work function layer 122 is formed between the gate dielectric layer 121 and the metal gate 123 and is in a U shape and positioned on the side wall and the bottom of the metal gate 123;
step 2) selectively growing a metal barrier layer 20 on the surface of the work function layer 122 and the metal gate 123;
step 3) forming a dielectric layer 30 on the surface of the structure formed in step 2);
step 4) patterning and etching the dielectric layer 30 to form a contact hole 40 above the metal gate 123;
the semiconductor device comprises a PMOS tube and an NMOS tube, wherein the PMOS tube and the NMOS tube have the same grid structure.
The method for reducing the loss of the work function layer of the HKMG device provided in this embodiment is described in detail below with reference to the accompanying drawings.
As shown in fig. 2, in step 1), a semiconductor structure 10 is provided, which includes a substrate 11 and a gate structure 12 of a plurality of semiconductor devices formed on the substrate 11, wherein the gate structure 12 includes a stacked structure of a gate dielectric layer 121, a work function layer 122 and a metal gate 123, and the work function layer 122 is formed between the gate dielectric layer and the metal gate 123 and is located on a side wall and a bottom of the metal gate 123 in a U shape.
In this embodiment, the semiconductor structure 10 is divided into a first device region a, a second device region B and a dummy region C, wherein the dummy region B is located between the first device region a and the second device region B. The first device region A is used for forming an NMOS tube, the second device region B is used for forming a PMOS tube, the dummy region C is used for forming any one of the NMOS tube and the PMOS tube, and the specific forming can be determined according to the densities of the NMOS tube and the PMOS tube.
Specifically, the semiconductor structure 10 further includes a sidewall 13, a stop layer 14, and an interlayer dielectric layer 15, where the sidewall 13 is formed on a sidewall of the gate structure 12, and the stop layer 13 is formed between the sidewall 14 and the interlayer dielectric layer 15.
Specifically, the substrate 11 is formed with a source region and a drain region of the NMOS transistor, and a source region and a drain region of the PMOS transistor.
In this embodiment, the source region and the drain region of the NMOS transistor are the first source region 51 and the first drain region 52, respectively, and the source region and the drain region of the PMOS transistor are the second source region 61 and the second drain 62, respectively.
Specifically, the gate dielectric layer 121 is a high-K dielectric layer.
In this embodiment, the gate dielectric layer 121 is made of hafnium oxide, silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, lanthanum oxide, zirconium oxide, or the like.
Specifically, the work function layer 122 of the NMOS transistor is made of TiAl, and the work function layer 122 of the PMOS transistor is made of TiAlC.
Specifically, the material of the metal gate 123 includes metal Al or metal W.
Specifically, the gate structure 12 further includes a gate blocking layer 124, and the gate blocking layer 124 is formed between the gate dielectric layer 121 and the work function layer 122.
In this embodiment, the material of the gate blocking layer 124 includes titanium nitride or tantalum nitride.
Further, in this embodiment, a shallow trench isolation structure 16 is also formed in the substrate 11.
As shown in fig. 3, in step 2), a metal barrier layer 20 is selectively grown on the work function layer 122 and the surface of the metal gate 123.
In this embodiment, the metal barrier layer 20 is introduced to prevent the work function layer 122 and the metal gate 123 from being damaged due to etching and cleaning processes during the formation of the contact hole 40.
Specifically, in performing step 2), the metal barrier layer 20 is formed using an atomic layer deposition process or an electroplating process.
Specifically, the material of the metal barrier layer 20 includes at least one of Co, W, pb, or TiSi.
Specifically, the thickness of the metal barrier layer 20 includes 20 to 50 angstroms.
As shown in fig. 4, in step 3), a dielectric layer 30 is formed on the surface of the structure formed in step 2).
In this embodiment, the dielectric layer 30 is formed on the surface of the structure formed in the step 2) by a deposition process. The dielectric layer 30 is made of silicon oxide.
As shown in fig. 5, in step 4), the dielectric layer 30 is patterned to form a contact hole 40 over the metal gate 123.
Specifically, in the step 4), the contact hole is formed by etching the dielectric layer 30 above the source region and the drain region of the NMOS transistor and above the source region and the drain region of the PMOS transistor.
In this embodiment, the contact hole 40 is formed above the metal gate 123, above the first source region 51 and the first drain region 52 of the NMOS transistor, and above the second source region 61 and the second drain region 62 of the PMOS transistor by etching the dielectric layer 30.
Specifically, after step 4), the method further includes a step of wet cleaning the structure formed in step 4).
In this embodiment, the wet cleaning of the structure formed in step 4) is performed using ultra-dilute hydrofluoric acid (UDHF), the volume ratio of hydrofluoric acid to water being 1:2000.
In summary, in the method for reducing damage to the work function layer of the HKMG device, the metal gate and the work function layer are protected by forming the metal protection layer on the surfaces of the metal gate and the work function layer, so that the metal gate and the work function layer are prevented from being damaged by the boundary effect caused by the subsequent process, and the threshold voltage drift of the device is avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (12)

1. A method of reducing damage to a work function layer of an HKMG device, the method comprising:
step 1) providing a semiconductor structure, which comprises a substrate and a grid structure of a plurality of semiconductor devices formed on the substrate, wherein the grid structure comprises a laminated structure of a grid dielectric layer, a work function layer and a metal grid, and the work function layer is formed between the grid dielectric layer and the metal grid and is U-shaped and positioned on the side wall and the bottom of the metal grid;
step 2) selectively growing a metal barrier layer on the surface of the work function layer and the metal gate;
step 3) forming a dielectric layer on the surface of the structure formed in the step 2);
step 4) patterning and etching the dielectric layer to form a contact hole above the metal gate;
the semiconductor device comprises a PMOS tube and an NMOS tube, wherein the PMOS tube and the NMOS tube have the same grid structure.
2. The method of reducing work function layer damage to an HKMG device of claim 1, wherein the material of the metallic barrier layer comprises at least one of Co, W, pb, or TiSi.
3. The method of reducing the work function layer damage of an HKMG device of claim 1, wherein the thickness of the metal barrier layer comprises 20 angstroms to 50 angstroms.
4. A method of reducing damage to a work function layer of an HKMG device according to any one of claims 1 to 3, wherein the metal barrier layer is formed using an atomic layer deposition process or an electroplating process when step 2) is performed.
5. The method for reducing the damage to the work function layer of the HKMG device according to claim 1, wherein the work function layer of the NMOS transistor is made of TiAl, and the work function layer of the PMOS transistor is made of TiAlC.
6. The method of reducing work function layer damage to an HKMG device of claim 1, wherein the gate dielectric layer is a high K dielectric layer.
7. The method of reducing the work function layer damage of an HKMG device of claim 1, wherein the metal gate material comprises metal Al or metal W.
8. The method of claim 1, wherein the semiconductor structure further comprises a sidewall, a stop layer and an interlayer dielectric layer, the sidewall is formed on the sidewall of the gate structure, and the stop layer is formed between the sidewall and the interlayer dielectric layer.
9. The method of reducing work function layer damage of an HKMG device of claim 1, wherein source and drain regions of the NMOS transistor and source and drain regions of the PMOS transistor are formed in the substrate.
10. The method of claim 9, wherein the contact holes are formed by etching the dielectric layer over the source and drain regions of the NMOS transistor and over the source and drain regions of the PMOS transistor while step 4) is performed.
11. The method of reducing work function layer damage to an HKMG device of claim 1, wherein the gate structure further comprises a gate barrier layer formed between the gate dielectric layer and the work function layer.
12. The method of reducing the work function layer damage of an HKMG device of claim 1, further comprising, after step 4), a step of wet cleaning the structure formed in step 4).
CN202310245663.9A 2023-03-14 2023-03-14 Method for reducing damage of work function layer of HKMG device Pending CN116130420A (en)

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CN202310245663.9A CN116130420A (en) 2023-03-14 2023-03-14 Method for reducing damage of work function layer of HKMG device

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Application Number Priority Date Filing Date Title
CN202310245663.9A CN116130420A (en) 2023-03-14 2023-03-14 Method for reducing damage of work function layer of HKMG device

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