CN116129764B

CN116129764B - Pixel optical structure for display optical efficiency

Info

Publication number: CN116129764B
Application number: CN202310257782.6A
Authority: CN
Inventors: 梁英喆; 金映锡; A·L·霍斯蒂恩; 程成; 许锦纬; 吕欣颐; I·G·饶; J·崔; J·M·博金斯; J·P·埃贝森; J·M·约翰逊; 廖瑞智; S·E·莫莱萨; 康盛球; 邓洋; 葛志兵
Original assignee: Apple Inc
Current assignee: Apple Inc
Priority date: 2022-03-22
Filing date: 2023-03-17
Publication date: 2023-11-24
Anticipated expiration: 2043-03-17
Also published as: CN116129764A; CN117373357A

Abstract

The present disclosure relates to pixel optical structures for display optical efficiency. An electronic device may have a display with an array of inorganic light emitting diodes. The array of inorganic light emitting diodes may be overlapped by a polarizer layer such as a circular polarizer. Alternatively, the display may be a polarizer-less display without any polarizer layer over the array of inorganic light emitting diodes. Each inorganic light emitting diode may be surrounded by a diffuser that redirects the edge emission towards the viewer. Top diffusers, color filter layers, microlenses, and/or microlenses with color filtering and/or diffusing properties can also optionally overlap each inorganic light emitting diode. These inorganic light emitting diodes may have reflective sidewalls to mitigate edge emission. In this type of arrangement, the array of inorganic light emitting diodes may be coplanar with one or more opaque masking layers. To mitigate reflection, the display may include two opaque masking layers with different properties or a single phase separated opaque masking layer.

Description

Pixel optical structure for display optical efficiency

Background

The present disclosure relates generally to electronic devices, and more particularly to electronic devices having displays.

Electronic devices typically include a display. For example, the electronic device may have an Organic Light Emitting Diode (OLED) display based on organic light emitting diode pixels, or a Liquid Crystal Display (LCD) based on liquid crystal display pixels. If careless, the display may have a lower resolution, contrast, or efficiency than desired, or may be affected by other artifacts.

Disclosure of Invention

An electronic device may have a display such as a light emitting diode display. The display may have an array of inorganic light emitting diodes. The array of inorganic light emitting diodes may be overlapped by a polarizer layer such as a circular polarizer. Alternatively, the display may be a polarizer-less display without any polarizer layer over the array of inorganic light emitting diodes.

Each inorganic light emitting diode may be surrounded by a diffuser that redirects the edge emission towards the viewer. The diffuser may be patterned to be absent outside the area surrounding the inorganic light emitting diode to achieve higher transmittance for the optical sensor under the display, or may be formed as a blanket layer. The top diffuser may also be patterned to be over the inorganic light emitting diodes, or the top diffuser may be formed as a blanket layer over the array of inorganic light emitting diodes. A color filter layer, microlenses, and/or microlenses having color filtering and/or diffusing properties can also optionally overlap each of the inorganic light emitting diodes.

These inorganic light emitting diodes may have reflective sidewalls to mitigate edge emission. In this type of arrangement, the array of inorganic light emitting diodes may be coplanar with one or more opaque masking layers.

To mitigate reflection, two opaque masking layers with different properties (e.g., different transmittance and different refractive index) may be included in the display. Alternatively, a single phase separated opaque masking layer may be used. The phase separated opaque masking layer may have a refractive index gradient along its depth with a minimum refractive index at the upper surface.

The light emitting diode display may overlap the optical sensor. The opaque masking layer in the display may include openings that do not overlap any light emitting diodes to allow additional ambient light to pass through the display to the optical sensor.

Drawings

FIG. 1 is a schematic diagram of an exemplary electronic device with a display according to various embodiments.

Fig. 2 is a schematic diagram of an exemplary display according to various embodiments.

Fig. 3 is a schematic diagram of an exemplary display having pixel control circuits according to various embodiments.

Fig. 4 is a schematic diagram of an exemplary passive matrix of light emitting diodes controlled by pixel control circuits according to various embodiments.

Fig. 5 is a cross-sectional side view of an exemplary display having a polarizer and light emitting diodes according to various embodiments.

Fig. 6 is a top view of the exemplary display of fig. 5, according to various embodiments.

Fig. 7 is a cross-sectional side view of an exemplary display with a polarizer and redundant light emitting diodes according to various embodiments.

Fig. 8 is a top view of the exemplary display of fig. 7, according to various embodiments.

FIG. 9 is a cross-sectional side view of an exemplary display having a polarizer, redundant light emitting diodes, and an opaque masking layer formed using dynamic photolithography, in accordance with various embodiments.

Fig. 10 is a cross-sectional side view of an exemplary display having a polarizer and light emitting diodes overlapped by two planarization layers, in accordance with various embodiments.

FIG. 11 is a cross-sectional side view of an exemplary display having a polarizer and light emitting diodes overlapped by microlenses, according to various embodiments.

Fig. 12 is a cross-sectional side view of an exemplary display having a polarizer and light emitting diodes overlapped by two planarizing layers and microlenses, according to various embodiments.

Fig. 13 is a top view of an exemplary display with different sized opaque masking layer openings for different color light emitting diodes, according to various embodiments.

FIG. 14 is a cross-sectional side view of an exemplary display having a polarizer and light emitting diodes overlapped by a patterned top diffuser, according to various embodiments.

FIG. 15 is a cross-sectional side view of an exemplary display having a polarizer and light emitting diodes overlapped by a blanket top diffuser according to various embodiments.

FIG. 16 is a cross-sectional side view of an exemplary display having polarizers, light emitting diodes, and a horizontal opaque masking layer portion between the light emitting diodes, according to various embodiments.

FIG. 17 is a cross-sectional side view of an exemplary display having polarizers, light emitting diodes, and vertical opaque masking layer portions between the light emitting diodes, according to various embodiments.

Fig. 18 is a cross-sectional side view of an exemplary display having a polarizer, a light emitting diode, and an additional planarizing layer, in accordance with various embodiments.

Fig. 19 is a cross-sectional side view of an exemplary display having a polarizer, light emitting diodes, and a thick insulating layer, according to various embodiments.

FIG. 20 is a cross-sectional side view of an exemplary display having a first opaque masking layer and a second opaque masking layer with different properties according to various embodiments.

FIG. 21 is a cross-sectional side view of an exemplary display having a color filter layer formed over an opaque masking layer, according to various embodiments.

FIG. 22 is a cross-sectional side view of an exemplary display with a low optical density opaque masking layer according to various embodiments.

FIG. 23 is a cross-sectional side view of an exemplary display having a phase-separated opaque masking layer according to various embodiments.

Fig. 24 is a diagram of an exemplary method for forming a phase separation layer, such as the phase separation opaque masking layer of fig. 23, in accordance with various embodiments.

Fig. 25 is a graph of refractive index as a function of depth for a phase separated layer, such as the phase separated opaque masking layer of fig. 23, according to various embodiments.

Fig. 26 is a cross-sectional side view of an exemplary light emitting diode having a corrugated upper surface, according to various embodiments.

FIG. 27 is a cross-sectional side view of an exemplary light emitting diode having a non-planar reflective lower surface, according to various embodiments.

FIG. 28 is a cross-sectional side view of an exemplary display having a polarizer, a light emitting diode, and an opaque masking layer with an opening overlapping the sensor, according to various embodiments.

Fig. 29 is a top view of the exemplary display of fig. 28, according to various embodiments.

FIG. 30 is a cross-sectional side view of an exemplary display having a polarizer, a light emitting diode, an opaque masking layer with an opening overlapping the sensor, and a top diffuser with portions removed between the sensor and the opening, according to various embodiments.

FIG. 31 is a cross-sectional side view of an exemplary display having a polarizer, light emitting diodes, and a low optical density opaque masking layer overlapping the sensor, according to various embodiments.

FIG. 32 is a cross-sectional side view of an exemplary display having a polarizer, a light emitting diode, and first and second opaque masking layers with different properties formed over a sensor, according to various embodiments.

FIG. 33 is a cross-sectional side view of an exemplary polarizer-less display with light emitting diodes overlapped by a patterned top diffuser and color filter layer, according to various embodiments.

Fig. 34 is a top view of the exemplary polarizer-less display of fig. 33, in accordance with various embodiments.

FIG. 35 is a cross-sectional side view of an exemplary polarizer-less display with redundant light emitting diodes overlapped by patterned top diffuser and color filter layers, according to various embodiments.

FIG. 36 is a cross-sectional side view of an exemplary polarizer-less display having redundant light emitting diodes that are each overlapped by a patterned top diffuser and color filter layer formed using dynamic photolithography, according to various embodiments.

FIG. 37 is a cross-sectional side view of an exemplary polarizer-less display with redundant light emitting diodes overlapped by a patterned top diffuser and color filter layer formed using dynamic photolithography, according to various embodiments.

FIG. 38 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode and first and second opaque masking layers having different properties, according to various embodiments.

FIG. 39 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes overlapped by two planarizing layers and microlenses, according to various embodiments.

FIG. 40 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes overlapped by microlenses, according to various embodiments.

FIG. 41 is a cross-sectional side view of an exemplary polarizer-less display with light emitting diodes overlapped by color filtering microlenses, according to various embodiments.

FIG. 42 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes overlapped by diffusing microlenses, according to various embodiments.

FIG. 43 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes overlapped by a blanket top diffuser, according to various embodiments.

FIG. 44 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes with reflective sidewalls overlapped by a patterned top diffuser and color filter layer, according to various embodiments.

FIG. 45 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes with reflective sidewalls overlapped by a patterned top diffuser and quantum dot layer, according to various embodiments.

FIG. 46 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes with reflective sidewalls overlapped by diffusing microlenses, according to various embodiments.

FIG. 47 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes with reflective sidewalls overlapped by a patterned top diffuser, color filter layer, and microlenses, according to various embodiments.

FIG. 48 is a cross-sectional side view of an exemplary polarizer-less display having light emitting diodes with reflective sidewalls overlapped by microlenses, according to various embodiments.

FIG. 49 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode with reflective sidewalls and a phase separated opaque masking layer, according to various embodiments.

FIG. 50 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode with reflective sidewalls and first and second opaque masking layers with different properties, according to various embodiments.

FIG. 51 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode and first and second opaque masking layers formed over a sensor, according to various embodiments.

FIG. 52 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode and a low optical density opaque masking layer formed over the sensor, according to various embodiments.

FIG. 53 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode with reflective sidewalls and an opaque masking layer with an opening formed over the sensor, according to various embodiments.

FIG. 54 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode with reflective sidewalls and first and second opaque masking layers formed over a sensor, according to various embodiments.

FIG. 55 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode with reflective sidewalls, first and second opaque masking layers formed over a sensor, and a cathode line formed between the first and second opaque masking layers, according to various embodiments.

FIG. 56 is a cross-sectional side view of an exemplary polarizer-less display having a light emitting diode with reflective sidewalls and a low optical density opaque masking layer formed over the sensor, according to various embodiments.

Detailed Description

The present application claims priority from U.S. patent application Ser. No. 18/161,763, filed on even 30 th 1/2023, U.S. patent application Ser. No. 18/161,764, filed on even 30 th 1/2023, U.S. provisional patent application Ser. No. 63/322,306, filed on even 22 th 3/2022, and U.S. provisional patent application Ser. No. 63/322,309, filed on even 22 th 3/2022, which are incorporated herein by reference in their entirety.

An exemplary electronic device of the type that may have a display is shown in fig. 1. The electronic device 10 may be a computing device such as a laptop computer, a computer monitor including an embedded computer, a tablet, a cellular telephone, a media player or other handheld or portable electronic device, a smaller device (such as a wristwatch device, a hanging device, a headset or earpiece device, a device embedded in glasses or other equipment worn on the head of a user, or other wearable or miniature device), a display, a computer display including an embedded computer, a computer display not including an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment having a display is installed in a kiosk or automobile), or other electronic equipment. The electronic device 10 may have the shape of a pair of eyeglasses (e.g., a support frame), may form an outer shell having the shape of a helmet, or may have other configurations for helping mount and secure components of one or more displays on or near the user's head.

As shown in fig. 1, the electronic device 10 may include control circuitry 16 for supporting the operation of the device 10. The control circuitry 16 may include storage devices such as hard drive storage devices, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid state drive), volatile memory (e.g., static random access memory or dynamic random access memory), and so forth. Processing circuitry in control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, and the like.

Input-output circuitry in device 10, such as input-output device 12, may be used to allow data to be provided to device 10 and to allow data to be provided from device 10 to an external device. Input-output devices 12 may include buttons, joysticks, wheels, touch pads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, light emitting diodes and other status indicators, data ports, and the like. The user may control the operation of device 10 by input resource provisioning commands through input-output device 12, and may receive status information and other outputs from device 10 using the output resources of input-output device 12.

The input-output device 12 may include one or more displays, such as display 14. The display 14 may be a touch screen display including touch sensors for gathering touch input from a user, or the display 14 may be touch insensitive. The touch sensor of display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch member, a force-based touch sensor structure, a light-based touch sensor, or other suitable touch sensor arrangement. The touch sensor for display 14 may be formed from electrodes formed on a common display substrate having display pixels of display 14, or may be formed from a separate touch sensor panel that overlaps with the pixels of display 14. If desired, the display 14 may be touch insensitive (i.e., the touch sensor may be omitted). The display 14 in the electronic device 10 may be a heads-up display that can be viewed without requiring the user to be remote from a typical point of view, or may be a head-mounted display incorporated into a device worn on the user's head. The display 14 may also be a holographic display for displaying holograms, if desired.

Control circuitry 16 may be used to run software, such as operating system code and application programs, on device 10. During operation of the device 10, software running on the control circuit 16 may display images on the display 14.

The input-output device 12 may also include one or more sensors 13, such as force sensors (e.g., strain gauges, capacitive force sensors, resistive force sensors, etc.), audio sensors such as microphones, touch and/or proximity sensors such as capacitive sensors (e.g., two-dimensional capacitive touch sensors associated with a display, and/or touch sensors forming buttons, touch pads, or other input devices not associated with a display), and other sensors. According to some embodiments, the sensors 13 may include optical sensors such as optical sensors that emit and detect light (e.g., optical proximity sensors such as transflective optical proximity structures), ultrasonic sensors, and/or other touch sensors and/or proximity sensors, monochrome and color ambient light sensors, image sensors (cameras), fingerprint sensors, temperature sensors, proximity sensors, and other sensors for measuring three-dimensional contactless gestures ("air gestures"), pressure sensors, sensors for detecting position, orientation, and/or motion (e.g., accelerometers, magnetic sensors such as compass sensors, gyroscopes, and/or inertial measurement units that include some or all of these sensors), health sensors, radio frequency sensors, depth sensors (e.g., structured light sensors and/or depth sensors based on stereoscopic imaging devices), optical sensors such as self-mixing sensors and light detection and ranging (laser radar) sensors that acquire time-of-flight measurements), humidity sensors, moisture tracking sensors, and/or other sensors. In some arrangements, the device 10 may use the sensor 13 and/or other input-output devices to gather user input (e.g., buttons may be used to gather button press input, touch sensors overlapping the display may be used to gather user touch screen input, a touch pad may be used to gather touch input, a microphone may be used to gather audio input, an accelerometer may be used to monitor when a finger contacts the input surface, and thus may be used to gather finger press input, etc.).

The display 14 may be an organic light emitting diode display, a display formed from an array of discrete light emitting diodes (micro-LEDs) each formed from a crystalline semiconductor die, a liquid crystal display, or any other suitable type of display. Device configurations in which display 14 includes micro LEDs are sometimes described herein as examples. However, this is merely illustrative. Any suitable type of display may be used if desired. In general, the display 14 may have a rectangular shape (i.e., the display 14 may have a rectangular footprint and a rectangular perimeter edge extending around the rectangular footprint) or may have other suitable shapes. The display 14 may be planar or may have a curved profile.

Fig. 2 is a diagram of an exemplary display. The display of fig. 2 is an active matrix display. As shown in fig. 2, display 14 may include layers, such as substrate layer 26. A substrate layer such as layer 26 may be formed from a rectangular planar material layer or a material layer having other shapes (e.g., rounded or other shapes having one or more curved edges and/or straight edges). The substrate layer of display 14 may include a glass layer, a polymer layer, a silicon layer, a composite film including a polymer material and an inorganic material, a metal foil, and the like.

The display 14 may have an array of pixels 22, such as pixel array 28, for displaying an image for a user. The pixels 22 (e.g., micro LEDs) in the array 28 may be arranged in rows and columns. The edges of the array 28 may be straight or curved (i.e., each row of pixels 22 and/or each column of pixels 22 in the array 28 may have the same length or may have different lengths). Any suitable number of rows and columns (e.g., ten or more, a hundred or more, or a thousand or more, etc.) may be present in array 28. Display 14 may include pixels 22 of different colors. For example, display 14 may include red pixels, green pixels, and blue pixels.

The display driver circuit 20 may be used to control the operation of the pixels 22. The display driver circuit 20 may be formed from integrated circuits, thin film transistor circuits, and/or other suitable circuits. The exemplary display driver circuit 20 of fig. 2 includes a display driver circuit 20A and additional display driver circuits such as a gate driver circuit 20B. The gate driver circuit 20B may be formed along one or more edges of the display 14. For example, the gate driver circuit 20B may be arranged along the left and right sides of the display 14, as shown in fig. 2.

As shown in fig. 2, the display driver circuit 20A (e.g., one or more display driver integrated circuits, thin film transistor circuits, etc.) may include communication circuitry for communicating with system control circuitry via signal path 24. Path 24 may be formed by traces on a flexible printed circuit or other cabling. The control circuitry may be located on one or more printed circuits in the electronic device 10. During operation, control circuitry (e.g., control circuitry 16 of FIG. 1) may provide image data to circuitry, such as display driver integrated circuits in circuitry 20, for causing an image to be displayed on display 14. The display driver circuit 20A of fig. 2 is positioned at the top of the display 14. This is merely illustrative. The display driver circuit 20A may be positioned at both the top and bottom of the display 14 or in other portions of the device 10.

In order to display an image on the pixel 22, the display driver circuit 20A may supply corresponding image data to the data line D when a control signal is issued to a supporting display driver circuit, such as the gate driver circuit 20B, through the signal path 30. With the exemplary arrangement of fig. 2, the data lines D extend vertically through the display 14 and are associated with respective columns of pixels 22.

The gate driver circuit 20B (sometimes referred to as a gate line driver circuit or a horizontal control signal circuit) may be implemented using one or more integrated circuits and/or may be implemented using thin film transistor circuits on the substrate 26. The horizontal control lines G (sometimes referred to as gate lines, scan lines, emission control lines, etc.) extend horizontally across the display 14. Each gate line G is associated with a respective row of pixels 22. If desired, there may be a plurality of horizontal control lines such as gate lines G associated with each row of pixels. The individually controlled signal paths and/or global signal paths in the display 14 may also be used to issue other signals (e.g., power signals, etc.).

Gate driver circuit 20B may assert a control signal on gate line G in display 14. For example, gate driver circuit 20B may receive clock signals and other control signals from circuit 20A on path 30 and may sequentially assert a gate line signal on gate line G from gate line signal G in a first row of pixels 22 in array 28 in response to the received signals. As each gate line is asserted, data from data line D may be loaded into the corresponding row of pixels. In this way, control circuitry, such as display driver circuits 20A and 20B, may provide signals to pixels 22 for instructing pixels 22 to display a desired image on display 14. Each pixel 22 may have a light emitting diode and circuitry (e.g., thin film circuitry on substrate 26) responsive to control signals and data signals from display driver circuitry 20.

The gate driver circuit 20B may include a gate driver circuit block, such as a gate driver row block. Each gate driver row block may include circuitry such as output buffers and other output driver circuitry, register circuitry (e.g., registers that may be linked together to form a shift register), and signal lines, power lines, and other interconnects. Each gate driver row block may provide one or more gate signals to one or more respective gate lines in a corresponding pixel row of the pixel array in an active area of display 14.

The active matrix addressing scheme of fig. 2 is merely illustrative. Display 14 may instead use pixel control circuitry that addresses a local passive matrix of pixels, if desired. An example of this type is shown in fig. 3. As shown in fig. 3, display 14 may also include layers, such as substrate layer 26. The layer such as substrate 26 may be formed from a material layer such as a glass layer, a polymer layer, a composite film including a polymer and an inorganic material, a metal foil, a semiconductor such as silicon or other semiconductor material, a material layer such as sapphire (e.g., a crystalline transparent layer, ceramic, etc.), or other materials. The substrate 26 may optionally be transparent (e.g., have a transmittance of greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 98%, greater than 99%, etc.). The substrate 26 may be planar or may have other shapes (e.g., concave, convex, shapes with planar and curved surface areas, etc.). The contour of the substrate 26 (e.g., when viewed from above along the Z-direction) may be circular, oval, rectangular, square, may have a combination of straight and curved edges, or may have other suitable shapes. As shown in the rectangular substrate example of fig. 3, the substrate 26 may have left and right vertical edges and upper and lower horizontal edges.

Display 14 may have an array of pixels 22 for displaying images for a user. A corresponding pixel control circuit 40 (sometimes referred to as a drive circuit 40 or micro-driver 40) may be used to control the group of one or more pixels 22 in fig. 3. The pixel control circuit 40 may be formed using integrated circuits (e.g., silicon integrated circuits) and/or thin film transistor circuits on the substrate 26. The thin film transistor circuit may include thin film transistors formed of silicon (e.g., polysilicon thin film transistors or amorphous silicon transistors) and/or may include thin film transistors based on semiconductor oxide (e.g., indium gallium zinc oxide transistors or other semiconductor oxide thin film transistors). Semiconductor oxide transistors, such as indium gallium zinc oxide transistors, may exhibit low leakage currents and may therefore be advantageous in configurations of display 14 where reduced power consumption (e.g., by reducing the refresh rate of pixels of the display) is desired. If desired, a configuration may be used in which the pixel control circuits 40 are each formed of a group of a silicon integrated circuit and a thin film semiconductor oxide transistor.

The pixels 22 may be organized in an array (e.g., an array having rows and columns). Pixel control circuits 40 may be organized in an associated array (e.g., an array having rows and columns). As shown in fig. 3, pixel control circuits 40 may be interspersed between pixel arrays 22. The pixels 22 and pixel control circuit 40 may be organized in an array having a rectangular outline, or may have an outline of other suitable shape. There may be any suitable number of rows and columns in each array (e.g., ten or more, a hundred or more, or a thousand or more).

Each pixel 22 may be formed of a light emitting member such as a light emitting diode. Each pixel may contain a pair of leds or other suitable number of leds for redundancy, if desired. In this type of configuration, pairs of light emitting diodes in each pixel may be driven in parallel (as an example). In case one of the light emitting diodes fails, the other light emitting diode will still generate light. Alternatively or additionally, a plurality of pixel control circuits may be configured to control each pixel. In the event that one of the pixel control circuits fails, the other pixel control circuit will still control the pixel.

A display driver circuit such as display driver circuit 20 may be coupled to conductive paths such as metal traces on substrate 26 using solder or conductive adhesive. The display driver circuit 20 may include communication circuitry for communicating with the system control circuit via path 24. Path 24 may be formed from traces or other cabling on a flexible printed circuit or may be formed using other signal path structures in device 10. The control circuitry may be located on a main logic board in the electronic device in which the display 14 is used. During operation, control circuitry (e.g., control circuitry 16 of FIG. 1) on the logic board may provide information to circuitry, such as display driver circuitry 20, regarding an image to be displayed on display 14. To display an image on the display pixels 22, the display driver circuit 20 may provide corresponding image data, control signals, and/or power signals to the signal lines S. The signal lines supply corresponding image data, control signals, and power to the pixel control circuits 40. Based on the received power, image data, and control signals, pixel control circuit 40 directs the corresponding subset of pixels 22 to generate light at the desired intensity level.

The signal line S may carry analog control signals and/or digital control signals (e.g., scan signals, transmit transistor control signals, clock signals, digital control data, power signals, etc.). In some cases, signal lines may be coupled to respective columns of pixel control circuits 40. In some cases, signal lines may be coupled to respective rows of pixel control circuits 40. Each pixel control circuit 40 may be coupled to one or more signal lines. The circuitry 20 may be formed on the upper edge of the display 14 (as in fig. 3), on the lower edge of the display 14, on the upper and left edges of the display 14, on the upper, left and right edges of the display, or any other desired location within the display 14.

Display control circuitry, such as circuitry 20, may be implemented using one or more integrated circuits (e.g., a display driver integrated circuit, such as a timing controller integrated circuit, and associated source driver circuitry and/or gate driver circuitry) or may be implemented using thin film transistor circuitry implemented on substrate 26.

The pixels 22 may be organic light emitting diode pixels or liquid crystal display pixels. Alternatively, the pixels 22 in fig. 3 may be formed of discrete inorganic light emitting diodes (sometimes referred to as micro LEDs). The pixels 22 may include light emitting diodes of different colors (e.g., red, green, blue). The corresponding signal lines may be used to carry red, green and blue data. Other color pixel arrangements (e.g., a four color arrangement, an arrangement including white pixels, a three pixel configuration with pixels other than red, green, and blue pixels, etc.) may be used if desired. To produce different colors, the light emitting diodes of the pixels 22 may be constructed of different material systems (e.g., alGaAs for red diodes, gaN multiple quantum well diodes with different quantum well configurations for green and blue diodes, respectively), may be formed using different phosphorescent materials or different quantum dot materials to produce red, blue and/or green light emission, or may be formed using other techniques or combinations of these techniques. The light emitting diodes of the pixels 22 may radiate upward (i.e., the pixels 22 may use a top-emitting design) or may radiate downward through the substrate 26 (i.e., the pixels 22 may use a bottom-emitting design). The light emitting diode may have a thickness of between 0.5 and 10 microns and may have a lateral dimension (as an example) of between 2 and 100 microns. Light emitting diodes having other thicknesses (e.g., less than 2 microns, greater than 2 microns, etc.) and having other lateral dimensions (e.g., less than 10 microns, less than 20 microns, greater than 3 microns, greater than 15 microns, etc.) may also be used if desired.

If desired, digital control signals may be provided to the circuits 40 (via signal lines S), which may then generate corresponding analog light-emitting drive signals based on the digital control signals. During operation of display 14, each pixel control circuit 40 may provide output signals to a corresponding group of pixels 22 based on control signals received by the pixel control circuit from display driver circuit 20.

For example, each pixel control circuit 40 may control a respective local passive matrix 42 of LED pixels 22. Fig. 4 is a schematic diagram of a local passive matrix 42 of LED pixels 22. As shown in fig. 4, the anode of each LED 22 is coupled to a respective anode contact line a (sometimes referred to as anode contact a or anode line a). The LEDs 22 of each column in the passive matrix are connected to a common anode contact a. The cathode of each LED 22 is coupled to a respective cathode contact line C (sometimes referred to as cathode contact C or cathode line C). The LEDs 22 of each row in the passive matrix are connected to a common cathode contact C.

The pixel control circuit 40 may also control the current and voltage supplied to each anode line a. The pixel control circuit 40 may also control the voltage supplied to each cathode contact line C. In this way, the pixel control circuit 40 controls the current through each light emitting diode 22, which controls the intensity of the light emitted by each light emitting diode. During operation of the passive matrix, pixel control circuit 40 may scan pixels 22 row by row at a high speed to cause each LED 22 to emit light at a desired brightness level. In other words, each pixel in the first row is updated to a desired brightness level, then each pixel in the second row is updated to a desired brightness level, and so on.

The pixel control circuit 40 may have a first output terminal 32 coupled to the anode contact line a and a second output terminal 34 coupled to the cathode contact line C. For example, the pixel control circuit 40 may have one output terminal 32 per anode contact line and one output terminal 34 per cathode contact line. Thus, using a passive matrix as in fig. 4 allows the pixel control circuit 40 to control 64 light emitting diodes (e.g., in an 8 x 8 grid) using only 16 outputs (8 anode output terminals and 8 cathode output terminals).

Fig. 5 is a cross-sectional side view of an exemplary display (e.g., a display having the arrangement of fig. 3 and 4) having LEDs 22 and pixel control circuitry 40. As shown in fig. 5, the display 14 may include a substrate 26. As previously mentioned, the substrate 26 may be formed from a layer of material such as a glass layer, a polymer layer (e.g., polyimide), a composite film including a polymer and an inorganic material, a metal foil, a semiconductor such as silicon or other semiconductor material, a layer of material such as sapphire, and the like. In the example of fig. 5, the substrate 26 may be formed of polyimide.

A pixel control circuit 40 (sometimes referred to as a micro-driver 40) is formed on the substrate 26. The pixel control circuit 40 is laterally surrounded by a planarization layer 54. For example, planarizing layer 54 may be an optically clear organic resin. Planarization layer 54 may be formed of any other desired material.

One or more insulating layers 56 are formed on the upper surface of the planarizing layer 54. Each insulating layer 56 may be formed of the same material, or different insulating layers may be formed of different materials. Layer 56 may be formed of the same material as layer 54 or a different material than layer 54. For example, layer 56 may be formed of an optically clear organic resin. In general, layer 56 may be formed of any desired material. Layer 56 serves as an insulating layer for back plane metal layer 72. The backplane metal layer 72 may include various signal lines and conductive vias for electrical routing signals within the display 14. For example, a back-plate metal layer may electrically connect the micro-driver 40 to the LEDs 22.

A spacer layer 70 and LEDs are formed on the upper surface of layer 56. The spacer 70 may be formed of the same material as the layer 56 or a different material than the layer 56. The spacer 70 may be formed of the same material as the layer 54 or a different material than the layer 54. For example, the spacer 70 may be formed of an optically clear organic resin. In general, the spacer 70 may be formed of any desired material. The spacers are used to position the LEDs 22 at a desired location (height) within the display. The LED22 may be attached to the upper surface of the spacer 70 with an adhesive or with a conductive structure (e.g., a conductive adhesive).

The LED 22 and spacer 70 may be laterally surrounded by the planarization layer 58. Planarization layer 58 may be formed of the same material as layer 54 or a different material than layer 54. Planarization layer 58 may be formed of the same material as layer 56 or a different material than layer 56. Planarization layer 58 may be formed of the same material as layer 70 or a different material than layer 70. For example, planarizing layer 58 may be formed of an optically clear organic resin.

A conductive layer such as a cathode line C may be formed on an upper surface of the planarization layer 58. The cathode line C may be formed of a transparent conductive material such as Indium Tin Oxide (ITO). The cathode line C may have a high transmittance (e.g., greater than 75%, greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 99%, etc.). The cathode line C may be electrically connected to one or more LEDs 22 on the display (as shown and discussed in connection with fig. 4).

An opaque masking layer 60 may be formed over the LEDs on the display 14. As shown in fig. 5, an opaque shielding layer 60 is formed on the upper surface of the cathode line C. The opaque masking layer has openings aligned with the LEDs 22 (to allow light from the LEDs 22 to pass through the opaque masking layer). The opaque masking layer 60 may have an opacity of greater than 50%, greater than 70%, greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 99%, etc. The opaque masking layer 60 may be formed of, for example, carbon black particles embedded in an organic resin. Covering the back plate metal (72) with the opaque masking layer 60 prevents ambient light from reflecting from the back plate metal toward the viewer (which would reduce display contrast).

A planarization layer 62 is formed over the opaque masking layer 60. Planarization layer 62 may be formed of the same material as layer 54 or a different material than layer 54. Planarization layer 62 may be formed of the same material as layer 58 or a different material than layer 58. Planarization layer 62 may be formed of the same material as layer 56 or a different material than layer 56. Planarization layer 62 may be formed of the same material as layer 70 or a different material than layer 70. For example, the planarization layer 62 may be formed of an optically clear organic resin.

A polarizer layer 64 may be formed over the planarization layer 62. The polarizer layer 64 may be a circular polarizer layer 64 including a linear polarizer and a quarter-wave plate. The circular polarizer may mitigate reflection of ambient light from the display 14.

A cover layer 66 may be formed over polarizer layer 64. The cover layer 66 may be formed of glass, polymer, a crystalline transparent layer such as sapphire, or the like. The cover layer 66 may have a high transmittance (e.g., greater than 75%, greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 99%, etc.).

Layers 54, 56, 58, and 62 may each have a high transmittance (e.g., greater than 75%, greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 99%, etc.).

The LED 22 may emit light vertically in the positive Z-direction (e.g., through an opening in the opaque masking layer 60). In addition, the LED 22 may emit edge light parallel to the XY plane (or more closely in angle to the XY plane than vertical). To increase the efficiency of the display 14, it is desirable to redirect edge-emitted light toward the viewer of the display. Thus, as shown in FIG. 5, a diffuser 68 may be formed around each LED 22. The diffuser 68 may be formed of nanoparticles (sometimes referred to as diffusing nanoparticles or light scattering nanoparticles) embedded in a clear organic resin (sometimes referred to as a host material). The bulk material of the diffuser may be the same material as layer 58 (in other words, the diffuser is formed of nanoparticles embedded in layer 58). Alternatively, a separate host material, different from the material of layer 58, may be included for diffuser 68.

As shown in the top view of fig. 6, the diffuser 68 may be formed in a ring that laterally surrounds the LEDs 22. This enables the side-emitted light from all sides of the LED 22 to be redirected towards the viewer of the display to increase the efficiency of the display.

In fig. 5 and 6, the diffuser 68 is patterned to be absent outside the area surrounding the inorganic light emitting diode. This may allow for higher transmittance through the display to an optical sensor below the display, for example. This example is merely illustrative. In another possible arrangement, the diffuser 68 may be a blanket layer that extends across the display over the entire planarization layer 58. In other words, the entire planarizing layer 58 may include embedded nanoparticles such that the entire planarizing layer 58 functions as a diffuser layer. In all embodiments herein having a side diffuser 68, the side diffuser may be patterned to be included only in the area surrounding the inorganic light emitting diode (as in fig. 5), or the side diffuser may be a blanket layer that completely covers the display (e.g., the entire planarization layer 58 acts as a diffuser layer).

The arrangements of fig. 5 and 6 are merely illustrative. In another possible arrangement, redundant LEDs may be included for each LED in the display. FIG. 7 is a cross-sectional side view of an exemplary display with redundant LEDs. As shown, a first spacer 70-1 and a second spacer 70-2 are formed on the upper surface of the insulating layer 56. The first LED 22-1 is formed on the upper surface of the spacer 70-1, and the second LED22-2 is formed on the upper surface of the spacer 70-2. Each of the LEDs 22-1 and 22-2 may be electrically connected to the cathode line C.

Including redundant LEDs may allow for the possibility of manufacturing errors in the LEDs 22. In other words, the manufacturing process of the LEDs 22 may result in a small percentage of the LEDs 22 being inoperable. If one of the LEDs is not operational, the redundant LEDs may instead be used for the display 14 (where possible). The LEDs 22-1 and 22-2 may thus be the same color LEDs (e.g., each configured to emit red light, each configured to emit green light, each configured to emit blue light, etc.).

As shown in FIG. 7, a diffuser 68 may be interposed between LEDs 22-1 and 22-2 and formed around the perimeter of LEDs 22-1 and 22-2. FIG. 8 is a top view of the display 14 in FIG. 7, showing how the diffuser 68 has a portion interposed between the LEDs 22-1 and 22-2 (in the XY plane). The diffuser 68 also has a portion that extends around the perimeter of the LEDs 22-1 and 22-2.

In fig. 7 and 8, the opaque masking layer 60 has an opening (in the Z direction) that overlaps both the LED 22-1 and the LED 22-2. This example is merely illustrative. In another possible arrangement shown in fig. 9, a dynamic photolithography process may be used to cover unused redundant LEDs. In other words, the LEDs 22 may be tested to verify which LEDs are functioning properly. Upon confirming that one of the LEDs is functioning properly (e.g., LED 22-2 in FIG. 9), the opaque masking layer 60 may be patterned to cover the unused LEDs (e.g., LED 22-1 in FIG. 9).

Each pixel in display 14 may have a LED pair. The opaque masking layer may cover one LED (e.g., an unused LED) of the LED pair and define an opening over the other LED (e.g., an LED for displaying light). Such selective patterning of the opaque masking layer based on which LEDs are functioning properly may be referred to as dynamic lithography (because the pattern of the opaque masking layer is updated for each display during fabrication).

The diffuser 68 in fig. 9 has the same arrangement as the diffuser in fig. 7. However, the top view of the display of fig. 9 is the same as the top view of the display shown in fig. 6 (with a single LED emitting light through each opening in the opaque masking layer).

To increase the efficiency of display 14, planarizing layer 62 (e.g., in fig. 5, 7, or 9) may have a low refractive index. For example, planarizing layer 62 may have a refractive index of less than 1.5, less than 1.45, less than 1.4, less than 1.35, less than 1.3, etc. The low refractive index of the planarizing layer 62 may cause off-axis light to be reflected at the interface between the LED 22 and the planarizing layer 62 by total internal reflection, resulting in light ultimately being reflected from the LED sidewalls toward the display viewer.

The example of forming planarizing layer 62 from a low refractive index material is merely illustrative. In another desired arrangement, shown in fig. 10, planarization layer 62 may be formed using multiple layers. The first layer 62-2 may be positioned between the LED 22 and the second layer 62-1. Planarization layer 62-2 can have a refractive index of less than 1.5, less than 1.45, less than 1.4, less than 1.35, less than 1.3, etc. Planarization layer 62-1 may have a refractive index that is greater than the refractive index of layer 62-2 (e.g., at least 0.05, at least 0.1, at least 0.15, at least 0.2, at least 0.3, etc.). Planarization layer 62-1 may have a refractive index greater than 1.4, greater than 1.5, greater than 1.6, greater than 1.7, etc.

To extract light from the light emitting diode (and thereby increase the efficiency of the display), one or more microlenses may be formed over the light emitting diode. Fig. 11 is a cross-sectional side view of an exemplary display showing exemplary microlenses 74. Microlenses 74 are formed over the openings in the opaque masking layer 60 (and corresponding LEDs 22) on the upper surface of the cathode electrode lines C. The microlenses 74 can be formed of an inorganic material or an organic material. The microlenses 74 can have a refractive index greater than 1.4, greater than 1.5, greater than 1.7, greater than 1.9, greater than 2.0, less than 2.2, less than 2.0, less than 1.8, less than 1.6, etc.

The example in which the microlenses 74 are formed on the upper surface of the cathode line C in fig. 11 is merely illustrative. In another possible arrangement shown in fig. 12, the planarization layer 62 is divided into a first planarization layer 62-1 and a second planarization layer 62-2 (as in fig. 10), and microlenses 74 are formed on the upper surface of the planarization layer 62-2.

Misalignment between the LEDs and corresponding openings in the opaque masking layer may cause visible artifacts on the display 14. To alleviate these problems, larger openings may be provided in the opaque masking layer for the LED. However, making the opaque masking layer opening too large may increase diffuse reflection on the display beyond the target level. To balance these factors, the openings for LEDs of certain colors may have different sizes than the openings for LEDs of other colors.

Generally, the human eye is more sensitive to green light than to red and blue light. The human eye may be less sensitive to blue light than to red and green light. Thus, the opaque masking layer openings for the green pixels may be larger than the openings for the red and blue pixels. Since the human eye is most sensitive to green light, a large opening for the green pixel provides the greatest tolerance for LED opening misalignment. The opaque masking layer openings for blue pixels may be smaller than the openings for red and blue pixels. Since the human eye is least sensitive to blue light, the small openings for the blue pixels reduce diffuse reflection in the display without causing artifacts due to misalignment of the LED openings.

As shown in FIG. 13, display 14 may include a green LED, such as LED 22-G, a blue LED, such as LED22-B, and a red LED, such as LED 22-R. Each opening may be defined by an opening having a first lateral dimension and a second lateral dimension (e.g., in the XY plane). The opening may be square (such that the first and second lateral dimensions are the same as in fig. 13) or may be rectangular that is non-square (such that the first and second lateral dimensions are different). Each red LED 22-R may be overlapped by an opening in the opaque masking layer having a maximum dimension 76-1. Each green LED 22-G may be overlapped by an opening in the opaque masking layer having a maximum dimension 76-2. Each blue LED22-B may be overlapped by an opening in the opaque masking layer having a maximum dimension 76-3. Maximum dimension 76-2 is greater than maximum dimension 76-1 (e.g., greater than 5%, greater than 10%, greater than 15%, greater than 25%, greater than 50%, etc.). Maximum dimension 76-1 is greater than maximum dimension 76-3 (e.g., greater than 5%, greater than 10%, greater than 15%, greater than 25%, greater than 50%, etc.). The area of each opening for the green pixel may be greater than the area of each opening for the red pixel (e.g., greater than 5%, greater than 10%, greater than 15%, greater than 25%, greater than 50%, etc.). The area of each opening for a red pixel may be greater than the area of each opening for a blue pixel (e.g., greater than 5%, greater than 10%, greater than 15%, greater than 25%, greater than 50%, etc.). Customizing the opaque masking layer opening size as in fig. 13 mitigates both reflection and artifacts caused by LED opening misalignment.

Fig. 14 illustrates another way of mitigating visible artifacts in the display 14. One potential cause of visible artifacts in displays is different LEDs with different emission profiles. To alleviate this type of variation, each LED may be covered by a top diffuser 78. The diffuser 78 may be formed of nanoparticles (sometimes referred to as diffusing nanoparticles or light scattering nanoparticles) embedded in a clear organic resin (sometimes referred to as a host material). The bulk material of the diffuser may be the same material as layer 62 (in other words, the diffuser is formed of nanoparticles embedded in layer 62). Alternatively, a separate host material, different from the material of layer 62, may be included for diffuser 78. As shown in fig. 14, a diffuser 78 may be formed over the LEDs 22 on the upper surface of the cathode line C. The nanoparticles for diffuser 78 may be the same as the nanoparticles for diffuser 68 or may be different from the nanoparticles for diffuser 68. The host material for the diffuser 78 may be the same as the host material for the diffuser 68 or may be different from the host material for the diffuser 68.

In fig. 14, a diffuser 78 may be patterned to be positioned over each LED in the display 14. This example is merely illustrative. In another possible arrangement shown in fig. 15, a blanket diffuser may be formed over the display that overlaps all of the LEDs in the display. As shown in fig. 15, a diffuser 78 is formed across the width of the display (and overlaps with the plurality of LEDs in the display). In this type of arrangement, the bulk material of diffuser 78 may be the same material as layer 62, the bulk material of diffuser 78 may be the same material as layer 58, the bulk material of diffuser 78 may be the same material as layer 56, the bulk material of diffuser 78 may be the same material as layer 54, the bulk material of diffuser 78 may be the same material as layer 70, or the bulk material of diffuser 78 may be a different material than the bulk material for layers 54, 56, 58, 70, and 62. The nanoparticles for diffuser 78 may be the same as the nanoparticles for diffuser 68 or may be different from the nanoparticles for diffuser 68.

One potential cause of visible artifacts in displays is the reflection of high angle light from the interface (e.g., glass-air interface) between the cover layer and the exterior of the device. These reflections may reflect from adjacent pixels, causing light to be visible in the nominally off region of the display. Consider light 80 in fig. 16. If careless, this light may reflect from the interface between the outer surface of the display cover 66 and the air, from adjacent LEDs 22, and toward the viewer of the display. To prevent these reflections, an additional opaque masking layer 82 may be included between pixels in the display. As shown in fig. 16, an opaque masking layer 82 is formed between the planarizing layer 62 and the polarizing plate 64. This example is merely illustrative. The opaque masking layer 82 may instead be embedded in the planarization layer 62, formed between the polarizer 64 and the cover layer 66, or formed at another desired location within the display stack. The opaque masking layer 82 overlaps the area between adjacent LEDs 22 in the display.

The material for opaque masking layer 82 may be the same as the material for opaque masking layer 60 or may be different from the material for opaque masking layer 60.

In fig. 16, an opaque masking layer 82 is formed as a horizontal layer (e.g., parallel to layer 60 and the XY plane) at an upper portion of planarization layer 62. This example is merely illustrative. In another possible arrangement shown in fig. 17, the opaque masking layer 82 may be formed from a vertical bar of opaque masking layer extending parallel to the Z-axis. The vertical portion of the opaque masking layer may extend entirely through the planarization layer 62 (e.g., from an upper surface of the planarization layer 62 adjacent to the polarizer 64 to a lower surface of the planarization layer 62 adjacent to the opaque masking layer 60). This example is merely illustrative. The vertical portions of the opaque masking layer may instead extend only partially through the planarization layer 62.

As shown in fig. 17, multiple (e.g., two, three, more than three) vertical portions of the opaque masking layer may be included between adjacent LEDs in the display 14. The material for opaque masking layer 82 may be the same as the material for opaque masking layer 60 or may be different from the material for opaque masking layer 60.

As shown in fig. 18, the planarizing layer 54 may have some non-planarity (e.g., adjacent to the micro-driver 40). Such uneven topography may lead to visible artifacts in the display 14. To mitigate these types of visible artifacts, an additional planarization layer 90 (shown in fig. 18) may be included between the insulating layer 56 and the planarization layer 58. For example, the additional planarization layer 90 may be formed of an optically clear organic resin. The material of layer 90 may be the same material as that used in layer 54, layer 56, layer 70, layer 58, and/or layer 62. Alternatively, the material of layer 90 may be a different material than the material in layers 54, 56, 58, 70, and 62.

Layer 90 may have a maximum thickness 84 of greater than 3 microns, greater than 5 microns, greater than 8 microns, greater than 10 microns, less than 20 microns, less than 10 microns, between 5 microns and 10 microns, etc. The presence of layer 90 ensures a planarized upper surface for overlying layers such as spacers 70, planarization layer 58, cathode lines C, opaque masking layer 60, etc.

In fig. 18, the insulating layer 56 (including the back plate metal 72) has a total thickness 86. The thickness 86 may be less than 10 microns, less than 5 microns, less than 3 microns, greater than 1 micron, etc. Another option for providing a planar surface for the display 14 over the micro-driver 40 is to increase the thickness of the insulating layer 56. Fig. 19 is a cross-sectional side view of this type of display. As shown in fig. 19, insulating layer 56 has a thickness 88 (e.g., maximum thickness) that is greater than thickness 86 of fig. 18. The thickness 88 in fig. 19 may be greater than 3 microns, greater than 5 microns, greater than 8 microns, greater than 10 microns, less than 20 microns, less than 10 microns, between 3 microns and 10 microns, etc.

One or more layers in display 14 may be designed to mitigate reflection of ambient light. Reducing reflection of ambient light may reduce undesirable visible artifacts in the display. Fig. 20-23 are cross-sectional side views of a portion of the display 14 (e.g., a portion between LEDs). In particular, fig. 20 to 23 show various arrangements of display layers for reducing reflection. In fig. 20 to 23, the cathode line C is omitted from the drawings for clarity. However, it should be understood that the cathode line C may still be included in the display.

In fig. 20, two opaque masking layers are used instead of one opaque masking layer. As shown, a first opaque masking layer 60-1 is formed over a second opaque masking layer 60-2. A second opaque masking layer 60-2 is formed over planarization layer 58. Opaque masking layer 60-1 may have a refractive index similar to that of planarizing layer 62. For example, the difference between the refractive index of layer 60-1 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

Opaque masking layer 60-2 may have a refractive index similar to that of planarizing layer 58. For example, the difference between the refractive index of layer 60-2 and the refractive index of layer 58 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

The refractive index of planarizing layer 62 may be lower than the refractive index of planarizing layer 58. Thus, the refractive index of opaque masking layer 60-1 may be lower than the refractive index of opaque masking layer 60-2. The difference between the refractive index of layer 60-1 and the refractive index of layer 60-2 may be greater than 0.5, greater than 0.3, greater than 0.2, greater than 0.1, greater than 0.05, greater than 0.01, etc.

The opaque masking layers 60-1 and 60-2 may each be formed of carbon black particles embedded in an organic resin. The density of carbon black particles within the organic resin may be selected for each opaque masking layer to control the transmittance of the opaque masking layer. Higher carbon black particle density (sometimes referred to as optical density) results in lower transmittance and higher opacity, while lower carbon black particle density results in higher transmittance and lower opacity. In one exemplary arrangement, the optical density of the opaque masking layer 60-2 may be greater than the optical density of the opaque masking layer 60-1 (e.g., greater than 10%, greater than 20%, greater than 50%, greater than 100%, greater than 200%, etc.). The total transmittance of the opaque masking layer 60-1 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. The total transmittance of the opaque masking layer 60-2 may be less than 3%, less than 5%, less than 10%, less than 25%, etc. The difference in total transmittance between opaque masking layers 60-1 and 60-2 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc.

As a specific example, layer 62 may have a refractive index of 1.4. Layer 60-1 may have a refractive index of 1.6. Layer 60-2 may have a refractive index of 1.7. Layer 62 may have a refractive index of 1.8. Reducing the optical density of opaque masking layer 60-1 allows the refractive index of layer 60-1 to be reduced relative to layer 60-2.

In fig. 21, a color filter layer 92 is formed over the opaque masking layer 60. The color filter layer 92 may have a refractive index similar to that of the planarization layer 62. For example, the difference between the refractive index of color filter layer 92 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

Opaque masking layer 60 may have a refractive index similar to that of planarizing layer 58. For example, the difference between the refractive index of layer 60 and the refractive index of layer 58 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

The refractive index of planarizing layer 62 may be lower than the refractive index of planarizing layer 58. Accordingly, the refractive index of the color filter layer 92 may be lower than that of the opaque masking layer 60. The difference between the refractive index of layer 60 and the refractive index of layer 92 may be greater than 0.5, greater than 0.3, greater than 0.2, greater than 0.1, greater than 0.05, greater than 0.01, etc.

The total transmittance of the opaque masking layer 60 may be less than 3%, less than 5%, less than 10%, less than 25%, etc. Color filter layer 92 may include, for example, a composite of red, green, and blue pigments.

In fig. 22, a low optical density opaque masking layer 94 is formed between planarizing layers 62 and 58. Opaque masking layer 94 may have a refractive index similar to that of planarizing layer 62. For example, the difference between the refractive index of opaque masking layer 94 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

The total transmittance of the opaque masking layer 94 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. The opaque masking layer 94 may have an optical density and thickness selected to substantially block ambient light reflection from the back plate metal 72. The total thickness of layer 94 may be greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 4 microns, etc.

In fig. 23, a phase separated opaque masking layer 96 is formed between planarization layers 62 and 58. To form the phase separated opaque masking layer 96, a solution may be formed on the planarizing layer 58. The solution may include a polymeric binder, a black material (e.g., carbon black particles), and a low refractive index additive. The low refractive index additive may have a low Surface Free Energy (SFE). After solution deposition, the solution may be heated in a Vacuum Chamber Drying (VCD) step. Heating from the VCD step causes phase separation in solution, wherein the low refractive index additive migrates to the surface of the phase separated opaque masking layer. The resulting phase separated opaque masking layer has a refractive index gradient at its upper surface. The refractive index gradient may mitigate reflection at an interface between the opaque masking layer and a subsequently deposited planarization layer (62).

Fig. 24 is a diagram illustrating an exemplary method for forming the phase-separated opaque masking layer 96. As shown in fig. 24, a solution coating 98 is initially deposited on planarization layer 58. As previously mentioned, the solution coating 98 may include a polymeric binder, a black material (e.g., carbon black particles), and a low refractive index additive. The solution coating 98 may also include a solvent. The solution is then heated in a vacuum chamber (sometimes referred to as a vacuum chamber drying step) to cause phase separation and/or solidification of the solution 98, which forms a phase separated opaque masking layer 96 (right side in fig. 24). During the heating step of fig. 24, the solution may be heated at a temperature greater than 100 degrees celsius, greater than 125 degrees celsius, greater than 150 degrees celsius, greater than 200 degrees celsius, less than 200 degrees celsius, between 125 degrees celsius and 175 degrees celsius, or the like. The solution may be heated for at least 5 minutes, at least 15 minutes, at least 25 minutes, at least 45 minutes, less than 45 minutes, between 15 minutes and 45 minutes, etc.

Fig. 25 is a graph of refractive index of the phase separated opaque masking layer 96 as a function of depth (in the negative Z direction). As shown by curve 100 in fig. 25, phase-separated opaque masking layer 96 is at depth 0 (e.g., at phase separation At the upper surface from opaque masking layer 96) has a minimum refractive index n ₁ . The refractive index then increases gradually in the negative Z direction. As shown in fig. 25, the refractive index may reach a maximum refractive index n at a given depth in the phase separated opaque masking layer 96 ₂ . The refractive index is then measured in the negative Z direction (in n ₂ Where) remains approximately constant.

The low refractive index additive in the phase separated opaque masking layer 96 can have a surface free energy (in mN/m) of less than 50, less than 40, less than 30, less than 20, etc. This property may cause the low refractive index additive to migrate to the upper surface of the phase separation opaque masking layer 96 during the vacuum chamber drying step of fig. 24. The low refractive index additive in the phase separated opaque masking layer 96 may include polyhedral oligomeric silsesquioxanes (POSS), pentanes, hexanes, octanes, benzene, or any other desired base molecule. The low refractive index additive in the phase separated opaque masking layer 96 may be fluorinated (e.g., fluorine added to the base molecule). Inclusion of fluorine in the additive can reduce the Surface Free Energy (SFE) of the additive, ensuring that the low refractive index additive migrates to the surface during phase separation.

N in FIG. 25 ₁ The size of (e.g., refractive index at the upper surface of phase separated opaque masking layer 96 adjacent to planarizing layer 62) may be less than 1.5, less than 1.45, between 1.35 and 1.45, greater than 1.3, etc. N in FIG. 25 ₁ The difference between the refractive index of the planarizing layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

N in FIG. 25 ₂ The size of (e.g., refractive index at the lower surface of phase separated opaque masking layer 96 adjacent planarizing layer 58) may be greater than 1.5, greater than 1.6, greater than 1.65, less than 1.9, less than 1.8, between 1.65 and 1.75, etc. N in FIG. 25 ₂ The difference between the refractive index of planarizing layer 58 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc.

N in phase separated opaque masking layer 96 ₁ And n ₂ The difference between them may be greater than 0.5, greater than 0.3, greater than 0.2, greater than 0.1, greater than0.05, greater than 0.01, etc.

The refractive index of the phase-separated opaque masking layer 96 may vary across a depth of at least 10 nanometers, at least 20 nanometers, at least 30 nanometers, less than 40 nanometers, less than 30 nanometers, between 10 nanometers and 30 nanometers, and the like. The total thickness of the phase separated opaque masking layer 96 may be greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 4 microns, etc. The refractive index of the phase-separated opaque masking layer 96 may vary across a depth that is less than 20% of the total thickness of the phase-separated opaque masking layer, less than 15% of the total thickness of the phase-separated opaque masking layer, less than 10% of the total thickness of the phase-separated opaque masking layer, less than 5% of the total thickness of the phase-separated opaque masking layer, greater than 10% of the total thickness of the phase-separated opaque masking layer, between 5% and 15% of the total thickness of the phase-separated opaque masking layer, etc.

In fig. 23-25, a phase separation layer is used to planarize the index matching between layers 58 and 62. This example is merely illustrative. The same concept of a phase separation layer with a refractive index gradient can be used for index matching between any desired layers in display 14, if desired. For example, phase separation layers for index matching between planarizing layer 62 and polarizer 64, opaque masking layer 60, color filter layer 92 (in fig. 21), and/or microlenses 74 (in fig. 10 and 11) may be included, phase separation layers for index matching between diffuser 68 and opaque masking layer 60 and/or color filter layers may be included, and the like. In general, any two layers in display 14 may have an intervening phase separation layer with a refractive index gradient for index matching.

In fig. 23 to 25, the phase separation layer has a varying refractive index for reducing reflection using refractive index matching. This example is merely illustrative. If desired, a phase separation layer formed using a technique similar to that of FIG. 24 may be used for other purposes. For example, the phase separation layer may selectively alter the hydrophobicity or roughness of the layers in the display. For example, a phase separation technique may be used to form a layer in display 14, such as planarization layer 62. Planarizing layer 62 can include an additive having a higher hydrophilicity than the bulk material used for the planarizing layer. During phase separation, the highly hydrophilic additive migrates to the surface of the planarizing layer. The surface of the planarisation layer may thus have a higher hydrophilicity due to the phase separation. This may improve the compatibility between the planarizing layer and the adjacent layer, for example. The opaque masking layer or color filter layer in the display may also include a highly hydrophilic additive in a similar manner (e.g., to promote adhesion to adjacent layers). As another example, the diffuser 68 (or another layer in the display) may contain macromolecules (e.g., metal oxides) that may lead to undesirably rough surfaces. The phase separation additive may be included in a layer formed of small molecules. Small molecules can migrate to the surface during phase separation, improving planarization of the layer (e.g., diffuser).

As another example, the diffuser 68, the planarizing layer 58, the insulating layer 56, and/or another display layer may include a leaching barrier additive that migrates to the surface during the phase separation process. The leaching barrier additive may block diffusion of potentially problematic materials (e.g., fluorine from the planarizing layer 62) into the layer and damage display components such as the LED 22. The leaching barrier additive may form a crosslinked layer at the surface of the layer during phase separation, thereby increasing the barrier efficiency of the phase separation layer at that surface.

In general, a phase separation layer formed using the technique of fig. 24 may eventually (after phase separation) have an additive with a maximum concentration at one surface of the layer and a concentration gradient as the depth into the phase separation layer increases. Properties affected by additives (e.g., hydrophilicity, refractive index, planarity, barrier efficiency, etc.) may thus follow this same curve (having local maxima/minima at the surface and having a gradient with increasing depth into the phase separation layer).

Another possible technique to mitigate visible artifacts in the display 14 is to use LEDs having non-planar upper and/or lower surfaces. Fig. 26 is a cross-sectional side view of an exemplary LED having a corrugated upper surface. As shown in fig. 26, the upper surface 102 of the LED 22 may have alternating ridges 104 and valleys 106. The ridges and valleys may extend along a longitudinal axis that is parallel to the Y-axis (into and out of the page in fig. 26). The corrugated upper surface of fig. 26 may prevent visible artifacts associated with the reflection of the LED 22.

In another possible arrangement shown in fig. 27, the LED 22 may have a lower surface defined by the metal layer 108. The metal layer 108 may sometimes be referred to as p-metal (as this metal is used as a contact for the p-type semiconductor in the LED 22). The metal layer 108 may have a reflectivity of greater than 50%, greater than 70%, greater than 80%, greater than 90%, greater than 99%, etc. As shown in fig. 27, the metal layer 108 is non-planar. The metal layer may have curvature along one dimension (e.g., along the X-axis shown in fig. 27). The metal layer may optionally have curvature along two dimensions (e.g., along the X-axis and the Y-axis). In fig. 27, the metal layer 108 has a convex curvature (e.g., extends in the negative Z-direction). This example is merely illustrative. The metal layer 108 may instead have a concave curvature or an irregular curvature. The non-planar lower surface of the LED 22 defined by the metal layer 108 may prevent visible artifacts associated with the reflection of the LED 22.

In some electronic devices, it may be desirable for an optical sensor, such as an ambient light sensor or a camera, to operate through the display 14. In other words, the optical sensor is positioned within the active area of the display 14. Ambient light may pass through the display stack (including the LEDs 22) to the sensor.

Fig. 28 is a cross-sectional side view of the display overlapping the optical sensor 13. The display may have any of the display arrangements described herein (e.g., the arrangement of fig. 14 with the diffuser 78 overlapping the LEDs 22). To allow more ambient light 112 to reach the sensor 13, the opaque masking layer 60 may have one or more additional openings 110 that do not overlap any LEDs. The opening 110 may allow additional ambient light to pass through the layers of the display 14 and ultimately be sensed by the sensor 13. The openings 110 may be positioned to overlap with the portion of the display stack having the highest transmissivity (e.g., the portion having the least backplate metal 72). The opening 110 may be positioned over a portion of the insulating layer 56 having the lowest density back plane metal 72. In case the opaque masking layer does not block ambient light (e.g. in the open area 110), the amount of ambient light reaching the sensor 13 is much larger.

In the example of fig. 28, the diffuser 78 fills the opening in the opaque masking layer 60 that overlaps the LED 22. This example is merely illustrative. If desired, the diffuser 78 may be omitted from the opening in the opaque masking layer 60 over the LEDs 22.

Fig. 29 is a top view of the exemplary display of fig. 28. As shown in fig. 29, LEDs 22 are distributed across the display. The opaque masking layer 60 has an opening that accommodates the LED 22. The opaque masking layer additionally has an opening 110 that allows ambient light to pass through the display to the sensor 13. The size, shape, and arrangement of the openings 110 may be selected based on the density of the underlying backplate metal and/or may be selected to mitigate diffraction artifacts in the image sensed by the sensor 13. In general, the openings 110 may have any desired arrangement.

In some cases, the sensor may operate with a display that includes a blanket top diffuser (e.g., of the type shown in fig. 15). In this type of arrangement (shown in fig. 30), the diffuser 78 may be removed (omitted) below the portion of the opaque masking layer 60 having the openings 110. Thus, the opaque masking layer has portions formed on the top diffuser (e.g., on the left side of fig. 30) and portions formed on the cathode line C and/or planarization layer 58 without an intervening top diffuser.

FIG. 31 is a cross-sectional side view of another arrangement for a display overlapping a sensor. In this example, a low optical density opaque masking layer 94 (e.g., of the type shown and discussed in connection with fig. 22) is formed between planarization layers 62 and 58. Opaque masking layer 94 may have a refractive index similar to that of planarizing layer 62. For example, the difference between the refractive index of opaque masking layer 94 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc. The total transmittance of the opaque masking layer 94 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. The total thickness of layer 94 may be greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 4 microns, etc.

The opacity of the low optical density opaque masking layer 94 in fig. 31 may be low enough to allow ambient light 112 to pass through the display stack to the sensor 13. Thus, no openings 110 (from fig. 28 and 30) are required in the low optical density opaque masking layer 94.

FIG. 32 is a cross-sectional side view of another arrangement for a display overlapping a sensor. In this example, two opaque masking layers 60-1 and 60-2 are used (as discussed in detail in connection with FIG. 21). When an opaque masking layer of this type is formed over sensor 13, opening 110 may be formed in opaque masking layer 60-2 (having a higher opacity) rather than in opaque masking layer 60-1 (having a lower opacity). As shown in fig. 32, an opaque masking layer 60-1 is formed in an opening 110 in the opaque masking layer 60-2. This example is merely illustrative, and openings 110 may be formed in both layers 60-1 and 60-2, if desired. Selectively removing portions of opaque masking layer 60-2 in opening 110 allows more ambient light 112 to reach sensor 13.

In the foregoing embodiments, the display 14 includes a polarizer 64 (e.g., a circular polarizer). The polarizer layer 64 may be a circular polarizer layer 64 including a linear polarizer and a quarter-wave plate. The circular polarizer may mitigate reflection of ambient light from the display 14. As a result of reducing reflection of ambient light, polarizer 64 also reduces the brightness of the display light emitted by LEDs 22 in display 14. Therefore, the polarizing plate 64 may be omitted in some cases in order to improve the efficiency of the display. In this type of arrangement (e.g., as shown in fig. 33), there is no polarizer between the LEDs 22 and the display cover 66. These types of displays may be referred to as polarizer-less displays.

Fig. 33 is a cross-sectional side view of a polarizer-less display. As shown in fig. 33, the arrangement of the display is similar to the previously described display with a polarizer. It should be noted that for the sake of brevity, the description of the components that have been described in connection with another figure may be omitted herein.

In fig. 33, the LEDs 22 are formed on the spacers 70 and may be laterally surrounded by the diffuser 68. An opaque masking layer 60 is formed over the planarization layer 58 and the cathode line C. The opaque masking layer has an opening to allow light from the LED 22 to pass through to reach the viewer. An additional diffuser 78 (sometimes referred to as a top diffuser) is formed in the opening of the opaque masking layer 60.

In addition to the diffuser 78, each LED 22 may be covered by a color filter layer 114. Color filter layer 114 may mitigate unwanted ambient light reflection from diffuser 78 and/or LEDs 22 while still passing light emitted by LEDs 22. For example, if the LED 22 emits red light, the color filter layer 114 may be a red color filter layer that blocks other colors of light while passing red light. If the LED 22 emits blue light, the color filter layer 114 may be a blue color filter layer that blocks other colors of light while passing blue light. If the LED 22 emits green light, the color filter layer 114 may be a green color filter layer that blocks other colors of light while passing green light.

Fig. 34 is a top view of a pixel in the polarizer-less display of fig. 33. As shown, the diffuser 78 overlaps the LEDs 22. A color filter layer 114 is then formed on top of both the LEDs 22 and the top diffuser 78.

In fig. 33 and 34, the diffuser 68 is patterned to be absent outside the area surrounding the inorganic light emitting diode. This may allow for higher transmittance through the display to an optical sensor below the display, for example. This example is merely illustrative. In another possible arrangement, the diffuser 68 may be a blanket layer that extends across the display over the entire planarization layer 58. In other words, the entire planarizing layer 58 may include embedded nanoparticles such that the entire planarizing layer 58 functions as a diffuser layer. In all non-polarizer displays herein having a side diffuser 68, the side diffuser may be patterned to be included only in the area surrounding the inorganic light emitting diodes (as in fig. 33), or the side diffuser may be a blanket layer that completely covers the display (e.g., the entire planarization layer 58 acts as a diffuser layer).

In another possible arrangement, redundant LEDs may be included for each LED in a polarizer-less display. Fig. 35 is a cross-sectional side view of an exemplary polarizer-less display with redundant LEDs. As shown, a first spacer 70-1 and a second spacer 70-2 are formed on the upper surface of the insulating layer 56. The first LED 22-1 is formed on the upper surface of the spacer 70-1, and the second LED 22-2 is formed on the upper surface of the spacer 70-2. Each of the LEDs 22-1 and 22-2 may be electrically connected to the cathode line C.

As shown in FIG. 35, a diffuser 68 may be interposed between LEDs 22-1 and 22-2 and formed around the perimeter of LEDs 22-1 and 22-2. A single opening in opaque masking layer 60 is formed over LEDs 22-1 and 22-2. A top diffuser 78 is formed in the opening and overlaps both LEDs 22-1 and 22-2. The color filter layer 114 overlaps the top diffuser 78. Color filter layer 114 may mitigate unwanted ambient light reflection from diffuser 78 and/or LEDs 22-1 and 22-2 while still passing light emitted by the LEDs.

In fig. 35, the opaque masking layer 60 has an opening (in the Z direction) that overlaps both the LED 22-1 and the LED 22-2. This example is merely illustrative. In another possible arrangement shown in fig. 36, a dynamic photolithography process may be used to cover unused redundant LEDs. In other words, the LEDs 22 may be tested to verify which LEDs are functioning properly. Upon confirming that one of the LEDs is functioning properly (e.g., LED 22-2 in FIG. 36), the opaque masking layer 60 may be patterned to cover the unused LEDs (e.g., LED 22-1 in FIG. 36).

The top diffuser 78 and color filter layer 114 may also be formed using a dynamic photolithography process. Thus, the diffuser 78 is formed in an opening in the opaque masking layer 60 (overlapping the LED22-2 but not overlapping the LED 22-1). Similarly, color filter layer 114 is patterned to overlap with LED22-2 and not with LED 22-1.

If desired, to simplify the deposition process of the color filter layer, the color filter layer may overlap both LEDs 22-1 and 22-2 (even if only LED22-2 emits light through the opaque masking layer opening). As shown in FIG. 37, a top diffuser 78 is formed in the opening in the opaque masking layer 60 (and overlaps LED22-2 but not LED 22-1). However, color filter layer 114 is formed over opaque masking layer 60 and top diffuser 78 and overlaps both LEDs 22-1 and 22-2. In other words, the opaque masking layer 60 and the top diffuser 78 are formed using a dynamic photolithography process, while the color filter layer 114 is not formed using a dynamic photolithography process.

Another possible arrangement for a polarizer-less display is shown in fig. 38. As shown, two opaque masking layers are used instead of one of the opaque masking layers in fig. 38. The top diffuser 78 is formed in an opening formed in both opaque masking layers 60-1 and 60-2. A color filter layer 114 is formed over the top surface of the top diffuser 78 and the opaque masking layer 60-1. As shown in fig. 38, a first opaque masking layer 60-1 is formed on a second opaque masking layer 60-2. A second opaque masking layer 60-2 is formed over planarization layer 58 (with intervening cathode lines C). Opaque masking layer 60-1 may have a refractive index similar to that of planarizing layer 62. For example, the difference between the refractive index of layer 60-1 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc. Opaque masking layer 60-2 may have a refractive index similar to that of planarizing layer 58. For example, the difference between the refractive index of layer 60-2 and the refractive index of layer 58 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc. The refractive index of planarizing layer 62 may be lower than the refractive index of planarizing layer 58. Thus, the refractive index of opaque masking layer 60-1 may be lower than the refractive index of opaque masking layer 60-2. The difference between the refractive index of layer 60-1 and the refractive index of layer 60-2 may be greater than 0.5, greater than 0.3, greater than 0.2, greater than 0.1, greater than 0.05, greater than 0.01, etc.

The opaque masking layers 60-1 and 60-2 in fig. 38 may each be formed of carbon black particles embedded in an organic resin. In one exemplary arrangement, the optical density of the opaque masking layer 60-2 may be greater than the optical density of the opaque masking layer 60-1 (e.g., greater than 10%, greater than 20%, greater than 50%, greater than 100%, greater than 200%, etc.). The total transmittance of the opaque masking layer 60-1 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. The total transmittance of the opaque masking layer 60-2 may be less than 3%, less than 5%, less than 10%, less than 25%, etc. The difference in total transmittance between opaque masking layers 60-1 and 60-2 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. As a specific example, layer 62 may have a refractive index of 1.4. Layer 60-1 may have a refractive index of 1.6. Layer 60-2 may have a refractive index of 1.7. Layer 62 may have a refractive index of 1.8. Reducing the optical density of opaque masking layer 60-1 allows the refractive index of layer 60-1 to be reduced relative to layer 60-2.

In another possible arrangement shown in fig. 39, the planarizing layer 62 may be split into two layers in a polarizer-less display. The first layer 62-2 may be positioned between the LED 22 and the second layer 62-1. Planarization layer 62-2 can have a refractive index of less than 1.5, less than 1.45, less than 1.4, less than 1.35, less than 1.3, etc. Planarization layer 62-1 may have a refractive index that is greater than the refractive index of layer 62-2 (e.g., at least 0.05, at least 0.1, at least 0.15, at least 0.2, at least 0.3, etc.). Planarization layer 62-1 may have a refractive index greater than 1.4, greater than 1.5, greater than 1.6, greater than 1.7, etc.

To extract light from the light emitting diode (and thereby increase the efficiency of the display), one or more microlenses may be formed over the light emitting diode. In fig. 39, microlenses 74 are formed over openings in the opaque masking layer 60 (and corresponding LEDs 22) on the upper surface of the planarization layer 62-2. The microlenses 74 can be formed of an inorganic material or an organic material. The microlenses 74 can have a refractive index greater than 1.4, greater than 1.5, greater than 1.7, greater than 1.9, greater than 2.0, less than 2.2, less than 2.0, less than 1.8, less than 1.6, etc. In fig. 39, planarization layer 62-2 is interposed between color filter 114 and microlens 74. Planarization layer 62-2 conforms to the upper surface and edges of color filter 114.

The example of microlenses 74 formed over planarizing layer 62-2 in fig. 39 is merely illustrative. In another possible arrangement shown in fig. 40, in a polarizer-less display, the microlenses 74 conform directly to the upper surface and edges of the color filter layer 114.

In another possible arrangement for a polarizer-less display, shown in FIG. 41, color filtering microlenses 74-CF are formed over top diffuser 78. The color filter microlenses 74-CF may have a curved upper surface (similar to the microlenses previously discussed). Additionally, the microlenses 74-CF block light of other colors while transmitting light from the overlapping LEDs 22. If the LED 22 emits red light, the micro-lens 74-CF may be a red color filter layer that blocks other colors of light while passing red light. If the LED 22 emits blue light, the micro-lenses 74-CF may be blue color filter layers that block other colors of light while passing blue light. If the LED 22 emits green light, the micro-lenses 74-CF may be green color filter layers that block other colors of light while passing green light. When microlenses 74-CF are used as the color filters, dedicated color filters 114 (e.g., from FIG. 40) may be omitted. The microlenses 74-CF can be formed of an inorganic material or an organic material. The microlenses 74-CF can have a refractive index greater than 1.4, greater than 1.5, greater than 1.7, greater than 1.9, greater than 2.0, less than 2.2, less than 2.0, less than 1.8, less than 1.6, etc.

In another possible arrangement shown in fig. 42, the color filtering microlenses also function as diffusing microlenses. In other words, the nanoparticles (sometimes referred to as diffusing nanoparticles or light scattering nanoparticles) may be distributed throughout the diffusing microlenses 74-D. When the microlenses have a color filtering function (as in fig. 42), the microlenses 74-D can act as diffusing elements, allowing for the omission of both the dedicated color filter element 114 and the top diffuser 78. In another possible arrangement, when the microlenses 74-D do not have a color filtering function (e.g., as in fig. 40), the microlenses may act as a diffusing element, allowing the top diffuser 78 to be omitted (while the color filter layer 114 remains present). The microlenses 74-D can be formed of an inorganic material or an organic material. The microlenses 74-D can have a refractive index greater than 1.4, greater than 1.5, greater than 1.7, greater than 1.9, greater than 2.0, less than 2.2, less than 2.0, less than 1.8, less than 1.6, etc.

In fig. 33-41, the top diffuser 78 is patterned as separate patches formed over each LED 22. This example is merely illustrative. In any of these arrangements, the top diffuser 78 may instead be formed as a blanket layer formed across the entire display. FIG. 43 is a cross-sectional side view of an exemplary polarizer-less display with a top diffuser 78. As shown in fig. 43, a diffuser 78 is formed across the width of the display (and overlaps with the plurality of LEDs in the display). The opaque masking layer 60 is formed over the top diffuser 78 such that the diffuser 78 is interposed between the planarization layer 58 and the opaque masking layer 60. Color filter layer 114 is formed in the opaque masking layer opening over LED 22 and top diffuser 78.

In fig. 33-43, LEDs 22 may emit some light through their sidewalls (e.g., parallel to the XY plane). Thus, a diffuser 68 is included to redirect these side emissions to the viewer through the opaque masking layer opening. The LED arrangement is merely illustrative.

In another possible arrangement shown in fig. 44, each LED22 may have reflective sidewalls. The reflective sidewalls of the LEDs ensure that all LED light is emitted in the positive Z direction towards the viewer. Thus, the diffuser 68 of fig. 33-43 may be omitted, and the opaque masking layer 60 may be patterned to conform to the sides of the LEDs 22. As shown in fig. 44, the planarizing layer 58 may cover (and laterally surround) the spacer layer 70 and optionally portions of the LEDs 22. An opaque masking layer 60 is formed over planarization layer 58. The opaque masking layer may directly contact the sidewalls of the LED 22. The opaque masking layer 60 may completely laterally surround (e.g., in the XY plane) the LED 22.

With the arrangement type of fig. 44, misalignment between the LEDs 22 and the opaque masking layer openings (which may be present in fig. 33-43) is mitigated. This may reduce visible artifacts in the display and increase the ease of manufacture. The display of fig. 44 is a polarizer-less display. Thus, the diffuser 78 and the color filter element 114 are formed over the LEDs 22.

The LED arrangement in fig. 44, where the LEDs have reflective sidewalls to prevent side emission, may be referred to as a cup-on-chip (CoW) LED arrangement. Generally, any of the foregoing display arrangements (e.g., top diffuser arrangement, color filter element arrangement, opaque masking layer arrangement, microlens arrangement, etc.) may be used in displays with cup-on-chip LEDs (with or without polarizers).

In fig. 44, the color filter elements 114 may optionally be omitted (such that the LEDs are overlapped by the diffuser 78, but not by the color filter elements). In another possible arrangement, the diffuser 78 may optionally be omitted from fig. 44 (such that the LEDs are overlapped by the color filter elements 114, but not by the diffuser).

In the previous embodiment, the color filter elements 114 are formed of homogeneous materials that filter light. This example is merely illustrative. In another possible arrangement shown in fig. 45, display 14 may include a quantum dot layer 120 with quantum dots 122 over LEDs 22 (instead of or in addition to a color filter layer). The quantum dot layer 120 includes quantum dots 122 distributed in a host material (e.g., a transparent host material). The quantum dots may be red quantum dots (e.g., converting blue light to red light) and/or green quantum dots (e.g., converting blue light to green light). The inclusion of a quantum dot layer as in fig. 45 may allow for the use of a single color LED 22 throughout the display 14. For example, blue LEDs may be used throughout the display 14, with some of the LEDs being selectively covered by a red quantum dot layer or a green quantum dot layer to allow full color emission.

In fig. 45, quantum dot layer 120 conforms to diffuser 78 in a polarizer-less display. This example is merely illustrative. The quantum dot layer may be used in any of the displays herein (with or without a polarizer). A display with a quantum dot layer may also include additional structures (e.g., one or more reflective layers to ensure that light generated by the quantum dot layer is directed in the Z-direction toward the viewer).

FIG. 46 is a cross-sectional side view of an exemplary polarizer-less display with diffusing microlenses 74-D formed over LEDs with reflective sidewalls. The microlenses 74-D in FIG. 46 can also have a color filtering function, allowing for the omission of both the dedicated color filter elements 114 and the top diffuser 78. In another possible arrangement, when the microlenses 74-D do not have a color filtering function (e.g., as in fig. 40), the microlenses may act as a diffusing element, allowing the top diffuser 78 to be omitted (while the color filter layer 114 remains present). The microlenses 74-D can be formed of an inorganic material or an organic material. The microlenses 74-D can have a refractive index greater than 1.4, greater than 1.5, greater than 1.7, greater than 1.9, greater than 2.0, less than 2.2, less than 2.0, less than 1.8, less than 1.6, etc.

The example of a diffusing microlens with color filtering properties formed over the LED 22 in fig. 46 is merely illustrative. In another possible arrangement, a diffuse color filter (having a planar upper surface that does not form microlenses) may be formed over the LEDs 22.

Other arrangements for stacking components may be used in displays having LEDs 22 with reflective sidewalls. In fig. 47, the diffuser 78, color filter element 114, and microlenses 74 overlap the LEDs 22. The microlenses 74 can be formed of an inorganic material or an organic material. The microlenses 74 can have a refractive index greater than 1.4, greater than 1.5, greater than 1.7, greater than 1.9, greater than 2.0, less than 2.2, less than 2.0, less than 1.8, less than 1.6, etc. In fig. 48, planarization layer 62 is divided into a first layer 62-1 and a second layer 62-2, wherein microlenses 74 are formed on the upper surface of layer 62-2 (e.g., similar to that shown in fig. 39). In fig. 49, a phase-separated opaque masking layer 96 is used (as shown and discussed in connection with fig. 23). In fig. 50, opaque masking layer 60 is divided into a first opaque masking layer 60-1 and a second opaque masking layer 60-2 (as shown and discussed in connection with fig. 20). In FIG. 50, cathode line C is formed between opaque masking layers 60-1 and 60-2, and diffuser 78 is formed in the opening in opaque masking layer 60-1 (while LED 22 is formed in the opening in opaque masking layer 60-2). This example is merely illustrative. As one possible alternative, the cathode line C may instead be formed under both of the opaque masking layers 60-1 and 60-2.

In some electronic devices, it may be desirable for an optical sensor, such as an ambient light sensor or a camera, to operate by passing through the polarizer-less display 14. In other words, the optical sensor is positioned within the active area of the polarizer-less display 14. Ambient light may pass through the display stack (including the LEDs 22) to the sensor. The absence of a polarizer in a non-polarizer display may allow more ambient light to reach the sensor.

FIG. 51 is a cross-sectional side view of a polarizer-less display overlapping a sensor. In this example, two opaque masking layers 60-1 and 60-2 are used (as discussed in detail in connection with FIG. 21). When an opaque masking layer of this type is formed over sensor 13, opening 110 may be formed in opaque masking layer 60-2 (having a higher opacity) rather than in opaque masking layer 60-1 (having a lower opacity). As shown in fig. 51, an opaque masking layer 60-1 is formed in an opening 110 in the opaque masking layer 60-2. Selectively removing portions of opaque masking layer 60-2 in opening 110 allows more ambient light 112 to reach sensor 13.

As shown in FIG. 51, a diffuser 78 may be formed in the openings in the opaque masking layers 60-1 and 60-2 over the LEDs 22. A color filter layer 114 is then formed over the top diffuser 78 and the upper surface of the opaque masking layer 60-1 over the LEDs 22.

The openings 110 may be positioned to overlap with the portion of the display stack having the highest transmissivity (e.g., the portion having the least backplate metal 72). The opening 110 may be positioned over a portion of the insulating layer 56 having the lowest density back plane metal 72. In case the opaque masking layer does not block ambient light (e.g. in the open area 110), the amount of ambient light reaching the sensor 13 is much larger. For example, the LEDs and openings in fig. 51 may be arranged with an occupied area as shown in fig. 29.

In the arrangement of fig. 51, the top diffuser 78 is patterned to form a patch over the LEDs 22. This example is merely illustrative. In an alternative arrangement (e.g., similar to that shown in fig. 30), a diffuser is formed across the blanket layer of the display, with portions between the light sensor 13 and the opening 110 selectively removed. In general, for any of the arrangements discussed herein, a blanket diffuser layer (with optional removal over the sensor) may be used instead of the patterned top diffuser shown in fig. 51.

FIG. 52 is a cross-sectional side view of another arrangement for a polarizer-less display overlapping a sensor. In this example, a low optical density opaque masking layer 94 (e.g., of the type shown and discussed in connection with fig. 22) is formed between planarization layers 62 and 58. Opaque masking layer 94 may have a refractive index similar to that of planarizing layer 62. For example, the difference between the refractive index of opaque masking layer 94 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc. The total transmittance of the opaque masking layer 94 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. The total thickness of layer 94 may be greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 4 microns, etc. The opacity of the low optical density opaque masking layer 94 in fig. 52 may be low enough to allow ambient light 112 to pass through the display stack to the sensor 13. Thus, no openings 110 (from FIG. 51) are required in the low optical density opaque masking layer 94. The color filter layer 114 in fig. 52 is formed on the upper surface of the top diffuser 78 and the low optical density opaque masking layer 94.

Fig. 53-56 show additional exemplary arrangements of a polarizer-less display overlapping an optical sensor. In each of fig. 53-56, the LED22 may have reflective sidewalls (in a cup-on-wafer arrangement). In the example of fig. 53, the opening 110 is formed in the opaque masking layer 60 above the sensor 13. The opening 110 may be positioned over a portion of the insulating layer 56 having the lowest density back plane metal 72. In case the opaque masking layer does not block ambient light (e.g. in the open area 110), the amount of ambient light reaching the sensor 13 is much larger. In the example of fig. 53, the cathode line C is formed over the opaque shielding layer 60 and in the opening 110. A diffuser 78 is formed over the LED22 on the cathode line C. The color filter layer 114 conforms to the diffuser 78 and overlaps the diffuser 78 and the LEDs 22.

In fig. 54 and 55, the opaque masking layer is divided into a first layer 60-1 and a second layer 60-2 (as discussed in detail in connection with fig. 21). When an opaque masking layer of this type is formed over sensor 13, opening 110 may be formed in opaque masking layer 60-2 (having a higher opacity) rather than in opaque masking layer 60-1 (having a lower opacity). As shown in fig. 54, an opaque masking layer 60-1 is formed in an opening 110 in the opaque masking layer 60-2. Selectively removing portions of opaque masking layer 60-2 in opening 110 allows more ambient light 112 to reach sensor 13.

In fig. 54, a cathode line C is formed over both of the opaque masking layers 60-1 and 60-2. Thus, the cathode line C is interposed between the LED 22 and the top diffuser 78. The cathode line C overlaps the opaque masking layer 60-1 over the opening 110. In another possible arrangement shown in FIG. 55, a cathode line C is formed between opaque masking layers 60-1 and 60-2. With this arrangement, the LEDs 22 are laterally surrounded by the opaque masking layer 60-2, and not by the opaque masking layer 60-1. The cathode line C is interposed between the LED 22 and the diffuser 78. A top diffuser 78 is formed in the opening in the opaque masking layer 60-1 over the LEDs 22. The top diffuser 78 is laterally surrounded by the opaque masking layer 60-1, and not by the opaque masking layer 60-2 (in a common plane). A color filter layer 114 is formed on the upper surface of the top diffuser 78 and the opaque masking layer 60-1.

FIG. 56 is a cross-sectional side view of another arrangement for a polarizer-less display having LEDs with reflective sidewalls. In this example, a low optical density opaque masking layer 94 (e.g., of the type shown and discussed in connection with fig. 22) is formed between planarization layers 62 and 58. Opaque masking layer 94 may have a refractive index similar to that of planarizing layer 62. For example, the difference between the refractive index of opaque masking layer 94 and the refractive index of layer 62 may be less than 0.3, less than 0.2, less than 0.1, less than 0.05, less than 0.03, less than 0.01, etc. The total transmittance of the opaque masking layer 94 may be greater than 5%, greater than 15%, greater than 25%, greater than 40%, greater than 50%, greater than 70%, etc. The total thickness of layer 94 may be greater than 1 micron, greater than 2 microns, greater than 3 microns, greater than 4 microns, etc. The opacity of the low optical density opaque masking layer 94 in fig. 56 may be low enough to allow ambient light 112 to pass through the display stack to the sensor 13. Thus, openings 110 (e.g., from fig. 53) are not required in the low optical density opaque masking layer 94. The cathode line C in fig. 56 is formed on the upper surface of the LED 22 and the low optical density opaque masking layer 94. A top diffuser 78 is formed over the LEDs 22 on the cathode line C. The color filter layer 114 conforms to the top diffuser 78 and overlaps the LEDs 22.

It is reiterated that each of the structures/arrangements described herein can be used in any desired combination in a single display.

In some displays, each color LED may have the same arrangement (e.g., an arrangement of opaque masking layers, top diffusers, microlenses, color filter layers, etc.). In another possible embodiment, different colored LEDs may have different arrangements. For example, the green LEDs in the display may be overlapped by the corresponding microlenses, while the red LEDs and blue LEDs are not overlapped by the microlenses. Generally, each color LED may have any of the arrangements described herein.

According to one embodiment, there is provided an electronic device including: an array of inorganic light emitting diodes; a display cover layer overlapping the array of inorganic light emitting diodes; a circular polarizer interposed between the array of inorganic light emitting diodes and the display cover layer; and a plurality of diffusers, each diffuser laterally surrounding at least one respective inorganic light emitting diode.

According to another embodiment, the electronic device includes: an opaque masking layer having an opening overlapping the inorganic light emitting diodes.

According to another embodiment, the array of inorganic light emitting diodes includes red inorganic light emitting diodes, green inorganic light emitting diodes, and blue inorganic light emitting diodes, each of the red inorganic light emitting diodes being overlapped by a respective opening in the opaque masking layer having a first area, each of the green inorganic light emitting diodes being overlapped by a respective opening in the opaque masking layer having a second area, each of the blue inorganic light emitting diodes being overlapped by a respective opening in the opaque masking layer having a third area, the second area being greater than the first area, and the first area being greater than the third area.

According to another embodiment, the array of inorganic light emitting diodes comprises pairs of inorganic light emitting diodes of the same color.

According to another embodiment, each opening in the opaque masking layer overlaps a corresponding pair of inorganic light emitting diodes.

According to another embodiment, each opening in the opaque masking layer overlaps one of the inorganic light emitting diodes of the corresponding pair of inorganic light emitting diodes instead of both inorganic light emitting diodes.

According to another embodiment, each diffuser laterally surrounds the perimeter of a respective pair of inorganic light emitting diodes and each diffuser includes a portion interposed between the respective pair of inorganic light emitting diodes.

According to another embodiment, the electronic device includes: a first planarization layer overlapping the inorganic light emitting diode array; and a second planarization layer overlapping the inorganic light emitting diode array, the second planarization layer being interposed between the first planarization layer and the inorganic light emitting diode array.

According to another embodiment, the second planarizing layer has a lower refractive index than the first planarizing layer.

According to another embodiment, the electronic device includes: a plurality of microlenses, each microlens formed over a respective inorganic light emitting diode on an upper surface of the second planarization layer.

According to another embodiment, the electronic device includes: and a plurality of microlenses, each microlens overlapping a corresponding inorganic light emitting diode.

According to another embodiment, the electronic device includes: a plurality of additional diffusers, each additional diffuser overlapping a respective inorganic light emitting diode.

According to another embodiment, the electronic device includes: an additional diffuser overlapping the plurality of inorganic light emitting diodes in the array of inorganic light emitting diodes.

According to another embodiment, the electronic device includes: a first planarization layer coplanar with the array of inorganic light emitting diodes; a first opaque masking layer formed on the first planarization layer, the first opaque masking layer having an opening overlapping the inorganic light emitting diodes, and the first opaque masking layer formed in a first plane; a second planarizing layer formed over the first opaque masking layer; and a second opaque masking layer formed on the second planarization layer, the second opaque masking layer formed in a second plane parallel to the first plane.

According to another embodiment, the electronic device includes: a first planarization layer coplanar with the array of inorganic light emitting diodes; a first opaque masking layer formed on the first planarization layer, the first opaque masking layer having openings overlapping the inorganic light emitting diodes; a second planarizing layer formed over the first opaque masking layer; and a second opaque masking layer orthogonal to the first opaque masking layer and extending through the second planarization layer.

According to another embodiment, the electronic device includes: a substrate; pixel control circuits mounted on the substrate; a first planarization layer disposed on the substrate and laterally surrounding the pixel control circuits; at least one insulating layer formed on the first planarization layer; a back plate metal formed in the at least one insulating layer; a plurality of spacer layers, each inorganic light emitting diode mounted on a respective spacer layer; a second planarizing layer coplanar with the plurality of spacer layers and the array of inorganic light emitting diodes; and a third planarization layer interposed between the at least one insulating layer and the second planarization layer.

According to another embodiment, the electronic device includes: a substrate; pixel control circuits mounted on the substrate; a first planarization layer disposed on the substrate and laterally surrounding the pixel control circuits; at least one insulating layer formed on the first planarization layer; a back plate metal formed in the at least one insulating layer; a plurality of spacer layers, each inorganic light emitting diode mounted on a respective spacer layer; and a second planarizing layer coplanar with the plurality of spacer layers and the array of inorganic light emitting diodes, the at least one insulating layer interposed between the first planarizing layer and the second planarizing layer, and the at least one insulating layer having a total thickness greater than 3 microns.

According to another embodiment, the electronic device includes: a first opaque masking layer; and a second opaque masking layer formed on the first opaque masking layer and having at least one attribute different from the first opaque masking layer.

According to another embodiment, the second opaque masking layer has a different refractive index than the first opaque masking layer and a different transmittance than the first opaque masking layer.

According to another embodiment, the electronic device includes: an opaque masking layer overlapping a region between the inorganic light emitting diode; and a color filter layer overlapping the opaque masking layer in a region between the inorganic light emitting diodes.

According to another embodiment, the electronic device includes: an opaque masking layer overlapping a region between the inorganic light emitting diode, the opaque masking layer having a transmittance of greater than 25% and a thickness of greater than 3 microns.

According to another embodiment, the electronic device includes: an opaque masking layer overlapping a region between the inorganic light emitting diode, the opaque masking layer having a refractive index that gradually varies from an upper surface toward a lower surface.

According to another embodiment, each inorganic light emitting diode has a corrugated upper surface.

According to another embodiment, each inorganic light emitting diode has a non-planar and reflective lower surface.

According to another embodiment, the electronic device includes: an optical sensor overlapped by at least a portion of the array of inorganic light emitting diodes.

According to one embodiment, there is provided an electronic device including: an array of inorganic light emitting diodes; a display cover layer overlapping the array of inorganic light emitting diodes; a circular polarizer interposed between the array of inorganic light emitting diodes and the display cover layer; and an opaque shielding layer formed over the array of inorganic light emitting diodes, the opaque shielding layer having openings, each opening overlapping a corresponding inorganic light emitting diode, the opaque shielding layer having an upper surface and a lower surface, the upper surface being interposed between the circular polarizer and the lower surface, and the opaque shielding layer having a refractive index that gradually increases from the upper surface toward the lower surface.

According to one embodiment, there is provided an electronic device including: an array of inorganic light emitting diodes; a display cover layer overlapping the array of inorganic light emitting diodes; a circular polarizer interposed between the array of inorganic light emitting diodes and the display cover layer; a first opaque masking layer formed over the array of inorganic light emitting diodes; and a second opaque masking layer formed over the first opaque masking layer, the second opaque masking layer having a lower refractive index than the first opaque masking layer.

The foregoing is merely illustrative and various modifications may be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented independently or may be implemented in any combination.

Claims

1. An electronic device, comprising:

an array of inorganic light emitting diodes;

a display cover layer overlapping the array of inorganic light emitting diodes;

a circular polarizer interposed between the array of inorganic light emitting diodes and the display cover layer;

a plurality of diffusers, wherein each diffuser laterally surrounds at least one respective inorganic light emitting diode; and

an opaque masking layer having openings overlapping the inorganic light emitting diodes, wherein the array of inorganic light emitting diodes comprises red inorganic light emitting diodes, green inorganic light emitting diodes, and blue inorganic light emitting diodes, wherein each of the red inorganic light emitting diodes is overlapped by a respective opening in the opaque masking layer having a first area, wherein each of the green inorganic light emitting diodes is overlapped by a respective opening in the opaque masking layer having a second area, wherein each of the blue inorganic light emitting diodes is overlapped by a respective opening in the opaque masking layer having a third area, wherein the second area is greater than the first area, and wherein the first area is greater than the third area.

2. The electronic device defined in claim 1 wherein the array of inorganic light-emitting diodes comprises pairs of inorganic light-emitting diodes of the same color, wherein each diffuser laterally surrounds a perimeter of a respective pair of inorganic light-emitting diodes, and wherein each diffuser comprises a portion interposed between the respective pair of inorganic light-emitting diodes.

3. The electronic device of claim 2, wherein each opening in the opaque masking layer overlaps a respective pair of inorganic light emitting diodes.

4. The electronic device of claim 2, wherein each opening in the opaque masking layer overlaps one of the inorganic light emitting diodes of the respective pair of inorganic light emitting diodes instead of both inorganic light emitting diodes.

5. The electronic device of claim 1, further comprising:

a first planarization layer overlapping the array of inorganic light emitting diodes;

a second planarization layer overlapping the inorganic light emitting diode array, wherein the second planarization layer is interposed between the first planarization layer and the inorganic light emitting diode array, and wherein the second planarization layer has a lower refractive index than the first planarization layer; and

A plurality of microlenses, wherein each microlens is formed over a respective inorganic light emitting diode on an upper surface of the second planarization layer.

6. The electronic device of claim 1, further comprising:

a plurality of microlenses, wherein each microlens overlaps a respective inorganic light emitting diode; and

a plurality of additional diffusers, wherein each additional diffuser overlaps a respective inorganic light emitting diode.

7. The electronic device of claim 1, further comprising:

an additional diffuser overlapping a plurality of inorganic light emitting diodes in the array of inorganic light emitting diodes.

8. The electronic device of claim 1, further comprising:

a first planarization layer coplanar with the array of inorganic light emitting diodes;

wherein the opaque masking layer is a first opaque masking layer formed on the first planarization layer, and wherein the first opaque masking layer is formed in a first plane;

a second planarizing layer formed over the first opaque masking layer; and

a second opaque masking layer formed on the second planarization layer, wherein the second opaque masking layer is formed in a second plane parallel to the first plane.

9. The electronic device of claim 1, further comprising:

wherein the opaque masking layer is a first opaque masking layer formed on the first planarization layer;

a second planarizing layer formed over the first opaque masking layer; and

a second opaque masking layer orthogonal to the first opaque masking layer and extending through the second planarizing layer.

10. The electronic device of claim 1, further comprising:

a substrate;

a pixel control circuit mounted on the substrate;

a first planarization layer on the substrate, laterally surrounding the pixel control circuit;

at least one insulating layer formed on the first planarization layer;

a back plate metal formed in the at least one insulating layer;

a plurality of spacer layers, wherein each inorganic light emitting diode is mounted on a respective spacer layer;

a second planarizing layer coplanar with the plurality of spacer layers and the array of inorganic light emitting diodes; and

And a third planarization layer interposed between the at least one insulating layer and the second planarization layer.

11. The electronic device of claim 1, further comprising:

a substrate;

a pixel control circuit mounted on the substrate;

at least one insulating layer formed on the first planarization layer;

a back plate metal formed in the at least one insulating layer;

a plurality of spacer layers, wherein each inorganic light emitting diode is mounted on a respective spacer layer; and

a second planarizing layer coplanar with the plurality of spacer layers and the array of inorganic light emitting diodes, wherein the at least one insulating layer is interposed between the first planarizing layer and the second planarizing layer, and wherein the at least one insulating layer has a total thickness greater than 3 microns.

12. The electronic device defined in claim 1 wherein the opaque masking layer is a first opaque masking layer and wherein the electronic device further comprises:

A second opaque masking layer formed on the first opaque masking layer and having at least one attribute different from the first opaque masking layer, wherein the second opaque masking layer has a different refractive index than the first opaque masking layer and a different transmittance than the first opaque masking layer.

13. The electronic device defined in claim 1 wherein the opaque masking layer overlaps a region between an inorganic light-emitting diode and wherein the electronic device further comprises:

and a color filter layer overlapping the opaque masking layer in a region between the inorganic light emitting diodes.

14. The electronic device of claim 1, wherein:

the opaque masking layer overlaps a region between the inorganic light emitting diode, and wherein the opaque masking layer has a transmittance of greater than 25% and a thickness of greater than 3 microns.

15. The electronic device of claim 1, wherein:

the opaque masking layer overlaps a region between the inorganic light emitting diode, and wherein the opaque masking layer has a refractive index that gradually varies from an upper surface toward a lower surface.

16. The electronic device of claim 1, wherein each inorganic light emitting diode has a corrugated upper surface.

17. The electronic device defined in claim 1 wherein each inorganic light-emitting diode has a non-planar and reflective lower surface and wherein the electronic device further comprises

An optical sensor overlapped by at least a portion of the inorganic light emitting diode array.

18. An electronic device, comprising:

an array of inorganic light emitting diodes;

a display cover layer overlapping the array of inorganic light emitting diodes;

a circular polarizer interposed between the array of inorganic light emitting diodes and the display cover layer; and

an opaque masking layer formed over the array of inorganic light emitting diodes, wherein the opaque masking layer has openings, wherein each opening overlaps a respective inorganic light emitting diode, wherein the opaque masking layer has an upper surface and a lower surface, wherein the upper surface is interposed between the circular polarizer and the lower surface, and wherein the opaque masking layer has a refractive index that gradually increases from the upper surface toward the lower surface.

19. An electronic device, comprising:

an array of inorganic light emitting diodes;

a display cover layer overlapping the array of inorganic light emitting diodes;

a first opaque masking layer formed over the array of inorganic light emitting diodes; and

a second opaque masking layer formed over the first opaque masking layer, wherein the second opaque masking layer has a lower refractive index than the first opaque masking layer.