CN116114175A

CN116114175A - Gate drive technique for reducing switch on resistance in switching converter applications

Info

Publication number: CN116114175A
Application number: CN202180062761.8A
Authority: CN
Inventors: T·郭; J·D·鲁特科夫斯基; S·穆赫吉
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2020-09-30
Filing date: 2021-08-31
Publication date: 2023-05-12
Also published as: US20240171060A1; WO2022072963A1; BR112023004792A2; US11916470B2; EP4222863A1; US20220103073A1; KR20230074143A; TW202232892A

Abstract

Techniques and apparatus for driving transistor gates of a Switch Mode Power Supply (SMPS) circuit. One example power supply circuit generally includes a switching converter having a switching transistor and a gate driver having an output coupled to a gate of the switching transistor. The gate driver includes: a first switching device coupled between an output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and the second voltage rail; and a voltage clamp coupled in series with the fourth switching device, the voltage clamp and the fourth switching device being coupled between the third voltage rail and the voltage node (or the output of the gate driver).

Description

Gate drive technique for reducing switch on resistance in switching converter applications

Cross Reference to Related Applications

The present application claims priority from U.S. non-provisional application No. 17/349,687, filed on 6 months 16 of 2021, which claims the benefit and priority from U.S. provisional application No. 63/085,341, filed on 9 months 30 of 2020, which is expressly incorporated by reference in its entirety as if fully set forth herein below for all applicable purposes.

Technical Field

Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly to driver architectures for switch mode power supplies.

Background

The voltage regulator desirably provides a constant Direct Current (DC) output voltage regardless of load current or input voltage variations. The voltage regulator may be classified as a linear voltage regulator or a switching voltage regulator. While linear voltage regulators tend to be small and compact, many applications may benefit from an increase in the efficiency of switching voltage regulators (also referred to as "switching converters"). For example, the linear voltage regulator may be implemented by a Low Dropout (LDO) voltage regulator. The switching regulator may be implemented by a Switched Mode Power Supply (SMPS), such as a buck converter, a boost converter, a buck-boost converter, or a charge pump.

For example, buck converters are SMPS, generally comprising: (1) a high-side switch coupled between a relatively high voltage rail and a switch node, (2) a low-side switch coupled between the switch node and a relatively low voltage rail, (3) and an inductor coupled between the switch node and a load (e.g., represented by a parallel capacitive element). The high-side and low-side switches are typically implemented with transistors, although the low-side switches may alternatively be implemented with diodes.

A charge pump is an SMPS that generally includes at least one switching device to control the connection of a supply voltage across a load through a capacitor. For example, in a voltage doubler, a capacitor of a charge pump circuit may initially be connected across a power supply to charge the capacitor to a supply voltage. The charge pump circuit may then be reconfigured to connect a capacitor in series with the power supply and the load, doubling the voltage across the load. This two-stage cycle repeats at the switching frequency of the charge pump. Charge pumps may be used to multiply or divide voltages by integers or fractions, depending on the circuit topology.

A power management integrated circuit (power management IC or PMIC) is used to manage the power requirements of the host system and may include and/or control one or more voltage regulators (e.g., buck converters or charge pumps). PMIC may be used in battery powered devices, such as cell phones, tablet computers, notebook computers, wearable devices, etc., to control the flow and direction of power in the device. The PMIC may perform various functions for the device, such as DC-DC conversion (e.g., using a voltage regulator as described above), battery charging, power supply selection, voltage scaling, power supply sequencing, and the like.

Disclosure of Invention

The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "detailed description of certain embodiments" one will understand how the features of this disclosure provide the advantages described herein.

Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit typically includes a switching converter having a switching transistor and a gate driver having an output coupled to the gate of the switching transistor. The gate driver includes: a first switching device coupled between an output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and the second voltage rail; and a voltage clamp coupled in series with the fourth switching device, the voltage clamp and the fourth switching device being coupled between the voltage node and the third voltage rail.

Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit typically includes a switching converter having a switching transistor and a gate driver having an output coupled to the gate of the switching transistor. The gate driver includes: a first switching device coupled between an output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and the second voltage rail; a voltage clamp is coupled in series with the fourth switching device, the voltage clamp and the fourth switching device being coupled between the third voltage rail and the output of the gate driver.

Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit typically includes a switching converter having a switching transistor and a gate driver having an output coupled to the gate of the switching transistor. The gate driver includes: a first switching device coupled between an output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and the second voltage rail; a voltage clamp is coupled in series with the fourth switching device, the voltage clamp and the fourth switching device being coupled between the third voltage rail and a voltage node or output of the gate driver.

Certain aspects of the present disclosure provide a Power Management Integrated Circuit (PMIC) that includes at least a portion of the power circuits described herein.

Certain aspects of the present disclosure provide a battery charging circuit including a power supply circuit as described herein.

Certain aspects of the present disclosure provide a method of supplying power. The method generally includes operating a gate driver to turn on a switching transistor of a switching converter by: changing a gate voltage of the switching transistor from a first voltage to a second voltage and routing a current through a first path of the gate driver; the gate voltage of the switching transistor is changed from the second voltage to a third voltage and current is routed through a second path of the gate driver different from the first path.

To the accomplishment of the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to several aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

Fig. 1 is a block diagram of an example apparatus including a Switched Mode Power Supply (SMPS) circuit, in which aspects of the present disclosure may be practiced.

Fig. 2A is a block diagram of an example power supply circuit in which aspects of the present disclosure may be practiced.

Fig. 2B is a circuit diagram of an example gate driver and an example inverting buck-boost converter in which aspects of the present disclosure may be practiced.

Fig. 3A and 3C are circuit diagrams of a portion of an example gate driver for a p-type transistor of a switching converter, in accordance with certain aspects of the present disclosure.

Fig. 3B is an example timing diagram of a portion of the gate driver of fig. 3A, in accordance with certain aspects of the present disclosure.

Fig. 4A and 4C are circuit diagrams of a portion of an example gate driver for an n-type transistor of a switching converter, in accordance with certain aspects of the present disclosure.

Fig. 4B is an example timing diagram of a portion of the gate driver of fig. 4A, in accordance with certain aspects of the present disclosure.

Fig. 5 and 6 are schematic diagrams of example switching converter applications using the gate drivers of fig. 3A and 4A, respectively, in accordance with certain aspects of the present disclosure.

Fig. 7 is a flowchart of example operations for powering in accordance with certain aspects of the present disclosure.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

Detailed Description

Certain aspects of the present disclosure provide techniques and apparatus for driving transistor gates of a Switched Mode Power Supply (SMPS) circuit. One example technique involves pulling down (or up) the gate voltage output from the gate driver to a voltage rail with a lower (or higher) voltage after implementing a fast transient in the SMPS circuit in the Vss (or Vdd) domain to obtain a larger gate-to-source voltage magnitude (|v) _gs |)。

Various aspects of the invention will be described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented in this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or in combination with any other aspect of the disclosure. For example, an apparatus may be implemented or a method practiced using any number of the aspects set forth. In addition, the scope of the present disclosure is intended to cover such an apparatus or method that is practiced using other structures, functions, or structures and functions in addition to or other than the illustrated aspects of the present disclosure. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of the claims.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

As used herein, the term "connected with … …" in various tenses of the verb "connected" may mean that element a is directly connected to element B, or that other elements may be connected between elements a and B (i.e., element a is indirectly connected to element B). In the case of electrical components, the term "connected to … …" may also be used herein to refer to a wire, trace, or other conductive material used to electrically connect components a and B (and any components electrically connected therebetween).

Example apparatus

It should be understood that aspects of the present disclosure may be used in a variety of applications. Although the invention is not limited in this respect, the circuits disclosed herein may be used in any of a variety of suitable devices, such as power supplies for communication systems, battery charging circuits, or power management circuits, video codecs, audio devices such as music players and microphones, televisions, camera devices, and test devices such as oscilloscopes. By way of example only, communication systems intended to be included within the scope of the present disclosure include cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal Communication Systems (PCS), personal Digital Assistants (PDAs), and the like.

FIG. 1 illustrates an example apparatus 100 in which aspects of the present disclosure may be implemented. The device 100 may be a battery-powered apparatus, such as a cellular phone, PDA, handheld device, wireless device, laptop computer, tablet, smart phone, internet of things (IoT) device, wearable device, or the like.

The apparatus 100 may include a processor 104 that controls the operation of the apparatus 100. The processor 104 may also be referred to as a Central Processing Unit (CPU). Memory 106, which may include Read Only Memory (ROM) and Random Access Memory (RAM), provides instructions and data to processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

In certain aspects, the device 100 may also include a housing 108, and the housing 108 may include a transmitter 110 and a receiver 112 to allow transmission and reception of data between the device 100 and a remote location. For certain aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached or otherwise coupled to the housing 108 and electrically coupled to the transceiver 114. The apparatus 100 may also include (not shown) multiple transmitters, multiple receivers, and/or multiple transceivers.

The apparatus 100 may also include a signal detector 118 that may be used to detect and quantify the level of signals received by the transceiver 114. The signal detector 118 may detect such signal parameters: such as total energy, energy per subcarrier per symbol, and power spectral density. The apparatus 100 may also include a Digital Signal Processor (DSP) 120 for use in processing signals.

The device 100 may also include a battery 122 for powering the various components of the device 100. The apparatus 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of the apparatus 100 that the PMIC124 may perform. The PMIC124 may perform various functions for the device, such as DC-to-DC conversion, battery charging, power selection, voltage scaling, power sequencing, and the like. In certain aspects, the PMIC124 may include at least a portion of a power circuit that may include a switch mode power circuit 125. The switch-mode power supply circuit 125 may be implemented by any of a variety of suitable switch-mode power supply circuit topologies, such as a buck converter, a boost converter, an inverting buck-boost converter, or a charge pump. For certain aspects, the PMIC124 may include battery charging circuitry (e.g., master-slave battery charging circuitry). For certain aspects, the power supply circuit may include a driver architecture having gate drive assistance (e.g., gate drive assistance circuitry), as described below.

The various components of apparatus 100 may be coupled together by a bus system 126, which bus system 126 may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.

Example Power supply Circuit with Gate driver and switching Circuit

Fig. 2A is a block diagram of an example power supply circuit 200 in which aspects of the present disclosure may be practiced. The power supply circuit 200 may include control logic 210, a gate driver 220, and a switching circuit 230. The control logic 210 may output control signals to control the timing of components in the gate driver 220. The gate driver 220 may output a signal having a specified output signal swing to control a control input (e.g., gate) of a switching device (e.g., a power Field Effect Transistor (FET)) in the switching circuit 230.

Fig. 2B is a circuit diagram 250 of a portion of an example gate driver 220 and an example switching circuit 230, in which aspects of the present disclosure may be practiced. The gate driver 220 may include

logic buffers

222, 224 and switches S1, S2. An input of the logic buffer 222 may be coupled to an output of the control logic 210 and an output thereof may have a control input coupled to the switch S1. In this example, switch S1 is implemented as a p-type field effect transistor (PFET), with its source coupled to a first voltage rail (labeled "Vin"), its gate coupled to the output of logic buffer 222, and its drain coupled to the output node (labeled "Vg") of this portion of gate driver 220. An input of the logic buffer 224 may have another output coupled to the control logic 210 and an output thereof may have a control input coupled to the switch S2. In this example, switch S2 is implemented as an n-type field effect transistor (NFET) with its drain coupled to the output node of the portion of gate driver 220, its gate coupled to the output of logic buffer 224, and its source coupled to a second voltage rail (e.g., electrical ground) that is lower in voltage than the first voltage rail. The power supply inputs of the logic buffers 222, 224 may be coupled to first and second voltage rails, as depicted in fig. 2B.

In this example, switching circuit 230 is implemented as an inverting buck-boost converter. It should be appreciated, however, that the switching circuit may alternatively be implemented as any of a variety of other suitable switching converter topologies, such as a boost converter. As shown, the inverting buck-boost converter includes power transistors M0, M1, an inductive element L1 (e.g., implemented by one or more inductors), and a capacitive element C1 (e.g., implemented by one or more capacitors). Transistor M0 is a PFET with its source coupled to the first voltage rail, its gate coupled to the output of gate driver 220 (i.e., output node Vg), and its drain coupled to switch node 228. Transistor M1 is an NFET with its drain coupled to switch node 228, its gate coupled to the other output of gate driver 220 (not shown), and its source coupled to output node 232 of the inverting buck-boost converter. The portion of the gate driver 220 that controls the control input of the transistor M1 is not shown, but may be implemented in a similar manner as described above. For certain aspects, transistor M1 may be replaced with another suitable component, such as a diode having an anode coupled to output node 232 and a cathode coupled to switching node 228.

A first terminal of the inductive element Ll is coupled to the switching node 228 and a second terminal of the inductive element Ll is coupled to the second voltage rail. A first terminal of capacitive element C1 is coupled to output node 232 and a second terminal of capacitive element C1 is coupled to the second voltage rail. The output voltage of the inverting buck-boost converter (labeled "VOUT") is generated across capacitive element C1 as shown. In an inverting buck-boost converter, VOUT is typically of opposite polarity to Vin and is adjustable according to the duty cycle of switching transistors M0 and M1.

During operation, the logic buffers 222, 224 may receive control signals (e.g., lower logic level signals) from the control logic and output signals for driving control inputs (e.g., gates) of the switches S1, S2. In certain aspects, the buffer output signal may have a higher voltage swing than the control signal received from the control logic 210. In this way, depending on the switching frequency of the inverting buck-boost and the duty cycle converter, the output signal from gate driver 220 on output node Vg may be pulled down to a logic low level (e.g., to the second voltage rail) to turn on power transistor M0, and may be pulled up to a logic high level (e.g., to the first voltage rail) to turn off transistor M0. Likewise, another output signal from gate driver 220 may be used to control the operation of power transistor M1, where the gate may be pulled up to a logic high to turn on transistor M1 and may be pulled down to a logic low to turn off transistor M1. The gate signal may operate in a break-before-make manner such that transistor M0 is turned off before transistor M0 is turned on, and vice versa. As described above, VOUT is controlled according to the duty cycle of the switching power transistors M0 and M1.

Some applications of the power supply circuit in portable devices (e.g., device 100) may require a relatively high load current at VOUT even if the battery voltage (Vin) is low with minimal impact on the die area. This may involve high current driving to charge and discharge the gate capacitance of the switching transistor M0 through switches S1 and S2 in the gate driver 220 using the example charging path 226 shown in fig. 2B. One way to provide high current drive is to increase the size of the switching transistors (e.g., power transistors M0, M1) in the switching circuit 230 and decrease the drain-to-source on-resistance (R) of the switching transistors _ds,on ). However, increasing the size of the switching transistor significantly increases the area occupied by the power supply circuit. Furthermore, large transistor sizes may increase gate capacitance, which may result in more switching losses and lower light load efficiency.

Example Gate driver for reducing on-resistance of switching transistor

Certain aspects of the present disclosure provide apparatus and techniques for driving the gates of power transistors in a switching regulator with a sufficiently high gate charge current even at lower voltages (e.g., low battery voltages). This may be achieved by introducing a further voltage domain in addition to the first and second voltage rails. By providing an additional voltage domain, a higher gate-to-source voltage amplitude can be obtained, thereby reducing the drain-to-source on-resistance (R _ds,on ) And reduces conduction losses through the switching transistor. Some aspects realize such higher current driving capabilityForce while having little impact on the die area of the gate driver Integrated Circuit (IC).

Fig. 3A is a circuit diagram of a portion of an example gate driver 300 for a p-type transistor (M0) of a switching converter, in accordance with certain aspects of the present disclosure. The gate drive circuit includes switches S1, S21, S22, and S3 and a voltage clamp 302 (labeled "Vclamp"). The switches S1, S21, S22, S3 and the voltage clamp 302 may be implemented by transistors (as shown in fig. 5). Switch S1 is coupled between a first voltage rail (labeled "VDD" herein) and a gate driver output node Vg. The switches S21 and S22 in fig. 3A replace the switch S2 of fig. 2B. Switches S21 and S22 are coupled in series between the output node Vg and a second voltage rail (labeled herein as "VSS") and share a common voltage node 303. Voltage clamp 302 and switch S3 are coupled in series between node 303 and a third voltage rail (labeled "VEE"). When switch S3 is closed, voltage clamp 302 and switch S3 provide gate drive assistance to increase the source-gate voltage (V _sg ) And decreases the on-resistance of the switch (e.g., the on-resistance of transistor M0).

Fig. 3B is an example timing diagram 350 of a portion of the gate driver 300 of fig. 3A, in accordance with certain aspects of the present disclosure. During the high-to-low switching interval (t _HL ) During the initial fast transient between VDD and VSS domains to turn on transistor M0, by switching on the transistor after the on time (t _on ) During which the gate voltage of transistor M0 is further pulled down from VSS to Vclamp using voltage clamp 302<VSS), wherein Vclamp is the voltage at node 303, whereby R of transistor M0 _ds,on And becomes smaller. V of transistor M0 _sg Clamped at its rated voltage (V) by a clamping circuit (clamp 302) _sg,max ) The following (e.g., VDD-Vclamp)<V _sg,max ). Vclamp may be referenced to VDD such that Vclamp is VDD minus the clamp voltage of clamp 302.

The order in which the power transistor M0 is turned on from the off state using the gate driver 300 is as follows. At t ₀ The control signal for the switch S1 changes, the switch S1 changes from an on state to an off state, and the switch S1 is turned off. At t ₁ The control signal for switch S21 is changed, switch S21 is formed fromThe off state changes to the on state and the switch S21 is closed. Because the switch S22 is at t ₁ Transistor M0 is already closed, so transistor M0 is on and the gate drive current temporarily flows along charging path 304 from the first voltage rail (VDD) to the second voltage rail (VSS) through transistor M0 and switches S21 and S22. This also pulls the gate voltage of the output node Vg down from VDD to VSS as t ₁ Fast transient at start t _HL Spacing. At t ₂ The control signal for the switch S22 transitions to change the switch S22 from an on state to an off state such that the switch S22 is turned off. At t ₃ The control signal for switch S3 is asserted to change switch S3 from an off state to an on state such that switch S3 is closed. This routes the gate drive current along charge path 306 through transistor M0, switch S21, voltage clamp 302, and switch S3, pulling the gate voltage at node Vg further down from VSS to Vclamp, where Vclamp is between VSS and VEE. At t ₃ Lowering the gate voltage to Vclamp increases Vsg (=VDD-Vclamp), lowers the on-resistance of transistor M0, and ends t _HL Spacing.

The turn-on sequence for transistor M0 (e.g., switch S1 open→switch S21 closed→switch S22 open→switch S3 closed) is opposite to the turn-off sequence (e.g., switch S3 open→switch S22 closed→switch S21 open→switch S1 closed). The order in which the power transistor M0 is turned off from the on state using the gate driver 300 is as follows. At t ₄ The control signal for the switch S3 is released to change the switch S3 from the on state to the off state, so that the switch S3 is turned off. The gate voltage at node Vg remains at or near Vclamp. At t ₅ The control signal for the switch S22 transitions to change the switch S22 from an off state to an on state such that the switch S22 is closed. At t ₅ Turning off the switch S22 changes the gate voltage at the node Vg from Vclamp to VSS, ending the gate assist period (t _on ) And starts a low-to-high switching interval (t _LH ) To turn off transistor M0. At t ₆ The control signal for the switch S21 transitions to change the switch S21 from an on state to an off state such that the switch S21 is turned off. At t ₇ The control signal for switch S1 is asserted toThe switch S1 is changed from the off state to the on state such that the switch S1 is closed. Closing switch S1 raises the gate voltage at node Vg to VDD and thus turns off p-type transistor M0, transitioning transistor M0 from an on state to an off state, and ending t _LH Spacing.

Voltage clamp 302 may be implemented by any suitable voltage clamp circuit without the burden of high current driving because of the initial high current spike (i.e., at t) that charges the gate capacitance of transistor M0 ₁ Fast transients at) enter the VSS domain (e.g., electrical ground), which is likely to be low impedance. Therefore, a large capacitor need not be included in the clamp circuit. When enough V is obtained from high VDD _sg Or in cases where meaningful V is not available due to lower absolute values of VEE (|vee|) _sg When added, the gate drive auxiliary circuit (also referred to as an "auxiliary circuit") may be disabled (e.g., by opening switch S3 and/or disabling voltage clamp 302) to reduce switching losses.

Fig. 3C is a circuit diagram of a portion of another example gate driver 370 for a p-type transistor (M0) of a switching converter, in accordance with certain aspects of the present disclosure. The gate driver 370 is similar to the gate driver 300 of fig. 3A, but in this case, the voltage clamp 302 and the switch S3 are coupled in series between the gate driver output node Vg and a third voltage rail (labeled "VEE"). When switch S3 is closed, voltage clamp 302 and switch S3 provide gate drive assistance to increase V _sg And decreases the on-resistance of the switch (e.g., the on-resistance of transistor M0). The example timing diagram 350 of fig. 3B and its description are also applicable to portions of the gate driver 370 of fig. 3C.

Fig. 4A is a circuit diagram of a portion of an example gate driver 400 for an n-type transistor (M2) of a switching converter, in accordance with certain aspects of the present disclosure. The gate driver 400 for the positive voltage domain is the counterpart of the gate driver 300 of fig. 3A for the negative voltage domain. For example, gate driver 400 may be used to drive the gates of transistors in a charge pump or low-side NFETs in a buck converter or boost converter. The gate driver 400 includes switches S1, S21, S22, and S3 and voltage clamps (labeled "Vclamp"). Switches S1, S21, S22, S3 and voltage clamp 402 may be implemented by transistors (as shown in fig. 6). Switch S1 is coupled between a first voltage rail (VSS in this case) and gate driver output node Vg. Switches S21 and S22 are coupled in series between the output node Vg and the second voltage rail (in this case VDD) and share a common voltage node 403. Voltage clamp 402 and switch S3 are coupled in series between node 403 and a third voltage rail (labeled "VCC"). When switch S3 is closed, voltage clamp 402 and switch S3 provide gate drive assistance to increase the gate-to-source voltage (V _gs ) And decreases the on-resistance of the switch (e.g., the on-resistance of transistor M2).

Fig. 4B is an example timing diagram 450 of a portion of the gate driver 400 of fig. 4A, in accordance with certain aspects of the present disclosure. During the low-to-high switching interval (t _LH ) During the initial fast transient between the VSS and VDD domains to turn on transistor M2, by switching on the transistor after the on time (t _on ) During which the gate voltage of transistor M2 is further pulled up to Vclamp using voltage clamp 402>VDD), wherein Vclamp is the voltage at node 403, whereby R of transistor M2 _ds,on And becomes smaller. The gate-source voltage (V) _gs ) Clamped at its rated voltage (V) by a clamping circuit (clamp 402) _sg,max ) The following (e.g., vclamp-VSS<V _sg,max ). Vclamp may be referenced to VSS such that Vclamp may be the clamp voltage of clamp 402 plus VSS.

The order in which the power transistor M2 is turned on from the off state using the gate driver 400 is as follows. At t ₀ The control signal for the switch S1 is changed to change the switch S1 from the on state to the off state such that the switch S1 is turned off. At t ₁ The control signal for the switch S21 is changed to change the switch S21 from the off state to the on state such that the switch S21 is closed. Because the switch S22 is at t ₁ Transistor M2 is turned on already closed and the gate drive current temporarily flows along charging path 404 from the second voltage rail (VDD) to the first voltage rail (VSS) through switches S22 and S21 and transistor M2. This in turn pulls the gate voltage at the output node Vg up from VSS to VDD as t ₁ Fast transient at start t _LH Spacing of. At t ₂ The control signal for the switch S22 transitions to change the switch S22 from an on state to an off state such that the switch S22 is turned off. At t ₃ The control signal for switch S3 is asserted to change switch S3 from an off state to an on state such that switch S3 is closed. This causes the gate drive current to be rerouted along the charge path 406 through switch S3, voltage clamp 402, switch S21 and transistor M2, pulling the gate voltage at node Vg further up from VDD to Vclamp, where Vclamp is between VDD and VCC. At t ₃ Raising the gate voltage to Vclamp increases Vgs (=Vclamp-VSS), decreases the on-resistance of transistor M2, and ends t _LH Spacing.

The turn-on sequence for transistor M2 (e.g., switch S1 open→switch S21 closed→switch S22 open→switch S3 closed) is opposite to the turn-off sequence (e.g., switch S3 open→switch S22 closed→switch S21 open→switch S1 closed). The order in which the power transistor M2 is turned off from the on state using the gate driver 400 is as follows. At t ₄ The control signal for switch S3 is de-asserted to change switch S3 from an on state to an off state such that switch S3 is off, thereby terminating current flow through path 406. The gate voltage at node Vg remains at or near Vclamp. At t ₅ The control signal for the switch S22 transitions to change the switch S22 from an off state to an on state such that the switch S22 is closed. At t ₅ Turning off the switch S22 changes the gate voltage at the node Vg from Vclamp to VDD, ending the gate auxiliary period (t _on ) And starts a high-to-low switching interval (t _HL ) To turn off transistor M2. At t ₆ The control signal for the switch S21 transitions to change the switch S21 from the on state to the off state, such that the switch S21 is turned off. At t ₇ The control signal for switch S1 is asserted to change switch S1 from an off state to an on state such that switch S1 is closed. Closing switch S1 reduces the gate voltage at node Vg to VSS and thus turns off n-type transistor M2, transitioning transistor M2 from an on state to an off state, and ending t _HL Spacing.

Voltage clamp 402 may be implemented by any suitable voltage clamp circuitIs achieved without the burden of high current driving because of the initial high current spike (i.e., at t) charging the gate capacitance of transistor M2 ₁ Fast transient at) into the VDD domain, which is likely to be low impedance. Therefore, a large capacitor need not be included in the clamp circuit. When enough V is obtained from high VDD _gs Or in cases where significant V is not available due to low VCC _sg When added, the gate drive auxiliary circuit may be disabled (e.g., by opening switch S3 and/or disabling voltage clamp 402), reducing switching losses.

Fig. 4C is a circuit diagram of a portion of an example gate driver 470 for an n-type transistor (M2) of a switching converter, in accordance with certain aspects of the present disclosure. The gate driver 470 for the positive voltage domain is the counterpart of the gate driver 370 of fig. 3C for the negative voltage domain. The gate driver 470 of fig. 4C is similar to the gate driver 400 of fig. 4A, but in this case, the switch S3 and the voltage clamp 402 are coupled in series between a third voltage rail (labeled "VCC") and the gate driver output node Vg. When switch S3 is closed, voltage clamp 402 and switch S3 provide gate drive assistance to increase V _gs And decreases the on-resistance of the switch (e.g., the on-resistance of transistor M2). The example timing diagram 450 of fig. 4B and its description are also applicable to portions of the gate driver 470 of fig. 4C.

Fig. 5 and 6 are schematic diagrams of example switching converter applications using the gate drive assist circuits of fig. 3A and 4A, respectively, in accordance with certain aspects of the present disclosure. For example, fig. 5 depicts an example power circuit 500 including an inverting buck-boost converter and the gate driver 300 of fig. 3A. In this case, the gate of the high-side p-type transistor (transistor M0) is driven to a negative voltage domain (Vclamp < vss=gnd) using the negative output voltage VOUT as VEE. Switch S1 and voltage clamp 302 are implemented as p-type transistors (e.g., PFETs), while switches S21, S22, and S3 are implemented as n-type transistors (e.g., NFETs). The NFET for switch S22 has a drain coupled to the second voltage rail (GND) and has a source coupled to the common voltage node 303. This arrangement maintains the body diode of the NFET of switch S22 reverse biased when switch S3 is closed. Fig. 5 may be modified to replace gate driver 300 with gate driver 370 of fig. 3C.

As another example, fig. 6 illustrates an example power circuit 600 including a boost converter and the gate driver 400 of fig. 4A. In this case, the gate of the low-side n-type transistor (transistor M2) is driven to Vclamp (> VDD) using a voltage higher than the input Voltage (VDD) (for example, vcc=2vdd). In power supply circuit 600, switch S1 and voltage clamp 402 are implemented as NFETs, while switches S21, S22, and S3 are implemented as PFETs. The PFET for switch S22 has a drain coupled to the second voltage rail (VDD) and has a source coupled to the common voltage node 403. This arrangement maintains the body diode of the PFET of switch S22 reverse biased when switch S3 is closed. Fig. 6 may be modified to replace gate driver 400 with gate driver 470 of fig. 4C.

The gate driver architecture described herein provides several advantages, including increased current drive capability, higher efficiency (due to lower transistor on-resistance), and smaller area (e.g., of power FETs, gate drivers, no high voltage level shifter, and/or voltage clamp circuits).

Example operation of Power supply

Fig. 7 is a flowchart of example operations 700 for powering in accordance with certain aspects of the present disclosure. The operation 700 may be performed by a power supply circuit having a gate driver with gate drive assist circuitry, such as the

gate drivers

300, 370, 400, 470 of fig. 3A, 3C, 4A, 4C, 5, and 6.

The operation 700 may begin at block 702, where a power circuit operates a gate driver (e.g.,

gate driver

300, 370, 400, or 470) to turn on a switching transistor (e.g., transistor M0 or M2) of a switching converter (e.g., switching circuit 230). Operating the gate driver at block 702 may involve changing a gate voltage (Vg) of the switching transistor from a first voltage (e.g., VDD or VSS) to a second voltage (e.g., VSS or VDD) and routing a charging current through a first path of the gate driver (e.g., charging path 304 or 404). Operating the gate driver at block 702 may also involve changing the gate voltage of the switching transistor from a second voltage to a third voltage (e.g., vclamp) and routing a charging current through a second path of the gate driver (e.g., charging path 306 or 406) that is different from the first path. The first path of the gate driver may be from a first voltage rail (e.g., VDD or VSS) at a first voltage to a second voltage rail (VSS or VDD) at a second voltage, and the second path of the gate driver may be from the first voltage rail at the first voltage to a third voltage rail (VEE or VCC) associated with a third voltage.

According to certain aspects, the switching transistor is a p-type transistor (e.g., PFET), the second voltage is lower than the first voltage, and the third voltage is lower than the second voltage (e.g., vclamp < VSS < VDD). On the other hand, the switching transistor is an n-type transistor (e.g., NFET), the second voltage is higher than the first voltage, and the third voltage is higher than the second voltage (e.g., vclamp > VDD > VSS).

According to certain aspects, the operations 700 may further comprise: at block 704, the power supply circuit operates the gate driver to turn off the switching transistor of the switching converter. Operating the gate driver at block 704 may involve changing the gate voltage switching transistor from a third voltage to a second voltage and routing a charging current through a first path of the gate driver. Operating the gate driver at block 704 may further include changing a gate voltage of the switching transistor from the second voltage to the first voltage and routing a charging current through a third path of the gate driver (e.g., through switch S1) different from the first path and the second path.

According to certain aspects, changing the gate voltage of the switching transistor from the first voltage to the second voltage at block 702 involves: disconnecting a first switching device (e.g., switch S1) coupled between an output of the gate driver (e.g., on output node Vg) and a first voltage rail (e.g., VDD or VSS) at a first voltage; closing a second switching device (e.g., switch S21) coupled between the output of the gate driver and a voltage node (e.g., node 303 or 403) of the gate driver; and closing a third switching device (e.g., switch S22) coupled between the voltage node of the gate driver and a second voltage rail (e.g., VSS or VDD) at a second voltage. In this case, the first path of the gate driver may include the second switching device and the third switching device. For certain aspects, changing the gate voltage of the switching transistor from the second voltage to the third voltage at block 702 involves: the third switching device is opened and a fourth switching device (e.g., switch S3) coupled in series with the voltage clamp (e.g., voltage clamp 302 or 402) is closed. In some cases, the voltage clamp and the fourth switching device may be coupled between the voltage node and a third voltage rail (e.g., VEE or VCC) associated with the third voltage, while in other cases, the voltage clamp and the fourth switching device may be coupled between the output of the gate driver and the third voltage rail (e.g., VEE or VCC) associated with the third voltage. The second path of the gate driver may include a second switching device, a voltage clamp, and a fourth switching device. For other aspects, changing the gate voltage of the switching transistor from the second voltage to the third voltage at block 702 involves: the third switching device is opened and the voltage clamp (e.g., voltage clamp 302 or 402) is enabled. The voltage clamp may be coupled between a voltage node and a third voltage rail (e.g., VEE or VCC) associated with a third voltage. In this case, the second path of the gate driver may include a second switching device and a voltage clamp. For certain aspects, operation 700 further involves at least one of disabling the voltage clamp or opening the fourth switching device when the magnitude of the difference between the second voltage and the first voltage is sufficient for the gate voltage of the switching transistor. This may occur, for example, (1) when the magnitude of the voltage difference is high enough to be suitable for a suitably low on-resistance of the switching transistor, or (2) when a significant voltage increase cannot be achieved by the gate drive auxiliary circuit due to the third voltage being low.

For certain aspects, operation 700 may also involve operating the gate driver to turn off the switching transistor of the switching converter, which is thereby achieved: a first path through which the charging current is routed through the gate driver by changing the gate voltage of the switching transistor from the third voltage to the second voltage; and by changing the gate voltage of the switching transistor from the second voltage to the first voltage and routing the charging current through a third path of the gate driver (e.g., through switch S1) different from the first path and the second path. In this case, changing the gate voltage of the switching transistor from the third voltage to the second voltage may include opening the fourth switching device and closing the third switching device. For other aspects, changing the gate voltage of the switching transistor from the third voltage to the second voltage may include disabling the voltage clamp and closing the third switching device. Changing the gate voltage of the switching transistor from the second voltage to the first voltage may include opening the second switching device and closing the first switching device.

Example aspects

In addition to the various aspects described above, specific combinations of aspects are also within the scope of the present disclosure, some of which are detailed below:

Aspect 1: a power supply circuit, comprising: a switching converter having a switching transistor; and a gate driver having an output coupled to the gate of the switching transistor, the gate driver comprising: a first switching device coupled between an output of the gate driver and a first voltage rail; a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; a third switching device coupled between the voltage node of the gate driver and the second voltage rail; and a voltage clamp coupled in series with the fourth switching device, the voltage clamp and the fourth switching device being coupled between the voltage node and the third voltage rail.

Aspect 2 the power supply circuit according to aspect 1, wherein: the switching transistor is a p-type transistor; the first voltage rail has a first voltage; the second voltage rail has a second voltage lower than the first voltage; and the third voltage rail has a third voltage lower than the second voltage.

Aspect 3 the power supply circuit according to aspect 2, wherein: the first switching means comprises a further p-type transistor and the second switching means, the third switching means and the fourth switching means comprise n-type transistors.

Aspect 4 the power supply circuit according to any one of the preceding aspects, wherein the switching converter comprises an inverting buck-boost converter, and wherein the switching transistor comprises a high-side p-type transistor in the inverting buck-boost converter.

Aspect 5. The power supply circuit according to any one of aspects 1-3, wherein the switching converter comprises a charge pump with switching transistors.

Aspect 6 the power supply circuit according to any one of the preceding aspects, wherein the third switching device comprises an n-type transistor having a drain coupled to the second voltage rail and having a source coupled to the voltage node.

Aspect 7 the power supply circuit according to aspect 1, wherein: the switching transistor is an n-type transistor; the first voltage rail has a first voltage; the second voltage rail has a second voltage higher than the first voltage; and the third voltage rail has a third voltage higher than the second voltage.

Aspect 8 the power supply circuit according to aspect 7, wherein: the first switching means comprises a further n-type transistor and the second switching means, the third switching means and the fourth switching means comprise p-type transistors.

The power supply circuit according to aspect 7 or aspect 8, wherein the switching converter comprises a boost converter, and wherein the switching transistor comprises a low-side n-type transistor in the boost converter.

The power supply circuit according to aspect 7 or aspect 8, wherein the switching converter comprises a buck converter, and wherein the switching transistor comprises a low-side n-type transistor in the buck converter.

Aspect 11 the power supply circuit according to aspect 7 or aspect 8, wherein the switching converter includes a charge pump with switching transistors.

Aspect 12 the power supply circuit according to any one of aspects 7-11, wherein the third switching device comprises a p-type transistor having a drain coupled to the second voltage rail and having a source coupled to the voltage node.

13. A Power Management Integrated Circuit (PMIC) comprising at least a portion of a power circuit according to any of the preceding aspects.

Aspect 14. A method of supplying power, comprising: the gate driver is operated to turn on the switching transistor of the switching converter by: changing a gate voltage of the switching transistor from a first voltage to a second voltage and directing a current through a first path of the gate driver; and changing a gate voltage of the switching transistor from a second voltage to a third voltage, and directing current through a second path of the gate driver, the second path being different from the first path.

Aspect 15 the method of aspect 14, wherein changing the gate voltage of the switching transistor from the first voltage to the second voltage comprises: disconnecting a first switching device coupled between an output of the gate driver and a first voltage rail at a first voltage; closing a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; and closing a third switching device coupled between a voltage node of the gate driver and a second voltage rail at a second voltage, wherein the first path of the gate driver includes the second switching device and the third switching device.

Aspect 16 the method of aspect 15, wherein changing the gate voltage of the switching transistor from the second voltage to the third voltage comprises: opening the third switching means; and closing a fourth switching device coupled in series with the voltage clamp, the voltage clamp and the fourth switching device coupled between the voltage node and a third voltage rail, the third voltage rail associated with a third voltage, wherein the second path of the gate driver includes the second switching device, the voltage clamp, and the fourth switching device.

Aspect 17 the method of aspect 16, further comprising: the gate driver is operated to turn off the switching transistor of the switching converter by: changing a gate voltage of the switching transistor from a third voltage to a second voltage and directing a current through a first path of the gate driver; and changing a gate voltage of the switching transistor from the second voltage to the first voltage, and directing a current through a third path of the gate driver, the third path being different from the first path and the second path.

Aspect 18 the method of aspect 17, wherein changing the gate voltage of the switching transistor from the third voltage to the second voltage comprises: opening the fourth switching device; and closing the third switching means.

Aspect 19 the method of aspect 17 or aspect 18, wherein changing the gate voltage of the switching transistor from the second voltage to the first voltage comprises: opening the second switching means; the first switching means is closed.

Aspect 20 the method of aspect 15, wherein changing the gate voltage of the switching transistor from the second voltage to the third voltage comprises: opening the third switching means; and closing a fourth switching device coupled in series with the voltage clamp, the voltage clamp and the fourth switching device coupled between the output of the gate driver and a third voltage rail, the third voltage rail associated with a third voltage, wherein the second path of the gate driver includes the voltage clamp and the fourth switching device.

Aspect 21. The method according to aspect 20, further comprising: the gate driver is operated to turn off the switching transistor of the switching converter by: changing a gate voltage of the switching transistor from a third voltage to a second voltage and directing a current through a first path of the gate driver; and changing a gate voltage of the switching transistor from the second voltage to the first voltage, and directing current through a third path of the gate driver, the third path being different from the first path and the second path.

Aspect 22 the method of aspect 21, wherein changing the gate voltage of the switching transistor from the third voltage to the second voltage comprises: opening the fourth switching device; and closing the third switching means.

Aspect 23 the method of aspect 21 or aspect 22, wherein changing the gate voltage of the switching transistor from the second voltage to the first voltage comprises: opening the second switching means; the first switching means is closed.

Aspect 24 the method according to any one of aspects 14-23, wherein: the switching transistor is a p-type transistor; the second voltage is lower than the first voltage; and the third voltage is lower than the second voltage.

Aspect 25 the method according to any one of aspects 14-23, wherein: the switching transistor is an n-type transistor; the second voltage is higher than the first voltage; and the third voltage is higher than the second voltage.

Aspect 26. The method according to any one of aspects 14-16, 18-20, and 22-25, further comprising: the gate driver is operated to turn off the switching transistor of the switching converter by: changing a gate voltage of the switching transistor from a third voltage to a second voltage and directing a current through a first path of the gate driver; and changing a gate voltage of the switching transistor from the second voltage to the first voltage, and directing current through a third path of the gate driver, the third path being different from the first path and the second path.

Aspect 27 the method according to any one of aspects 14-26, wherein: the first path of the gate driver is from a first voltage rail at a first voltage to a second voltage rail at a second voltage; and wherein the second path of the gate driver is from the first voltage rail at the first voltage to a third voltage rail associated with a third voltage.

The various operations of the above-described methods may be performed by any suitable means capable of performing the corresponding functions. The apparatus may include various hardware and/or software components and/or modules including, but not limited to, circuits, application Specific Integrated Circuits (ASICs), or processors. Generally, where there are operations shown in the figures, those operations may have corresponding means-plus-function elements with like numbers.

As used herein, the term "determining" includes a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Further, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and so forth. Also, "determining" may include parsing, selecting, choosing, establishing, and the like.

As used herein, a phrase referring to "at least one" in a list of items refers to any combination of those items, including individual members. As an example, "at least one of a, b, or c" is intended to encompass: a. b, c, a-b, a-c, b-c, and a-b-c, and any combination having a plurality of identical elements (e.g., a-a-b, a-a-c, a-b-b, c-c, b-b-b, b-b-c, c-c, and c-c-c, or any other order of a, b, and c).

The methods disclosed herein comprise one or more steps or actions for achieving the described method. Method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

It is to be understood that the claims are not limited to the precise arrangements and instrumentalities described above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A power supply circuit, comprising:

a switching converter having a switching transistor; and

A gate driver having an output coupled to a gate of the switching transistor, the gate driver comprising:

a first switching device coupled between the output of the gate driver and a first voltage rail;

a second switching device coupled between the output of the gate driver and a voltage node of the gate driver;

third switching means coupled between the voltage node of the gate driver and a second voltage rail; and

a voltage clamp is coupled in series with a fourth switching device, the voltage clamp and the fourth switching device being coupled between a third voltage rail and the voltage node or the output of the gate driver.

2. The power supply circuit of claim 1, wherein:

the switching transistor is a p-type transistor;

the first voltage rail has a first voltage;

the second voltage rail has a second voltage lower than the first voltage; and

the third voltage rail has a third voltage that is lower than the second voltage.

3. The power supply circuit of claim 2, wherein:

the first switching device includes another p-type transistor, and

the second, third and fourth switching devices comprise n-type transistors.

4. The power supply circuit of claim 2, wherein the switching converter comprises an inverting buck-boost converter, and wherein the switching transistor comprises a high-side p-type transistor in the inverting buck-boost converter.

5. The power supply circuit of claim 2, wherein the switching converter comprises a charge pump with the switching transistor.

6. The power supply circuit of claim 2, wherein the third switching device comprises an n-type transistor having a drain coupled to the second voltage rail and having a source coupled to the voltage node.

7. The power supply circuit of claim 1, wherein:

the switching transistor is an n-type transistor;

the first voltage rail has a first voltage;

the second voltage rail has a second voltage that is higher than the first voltage; and

the third voltage rail has a third voltage that is higher than the second voltage.

8. The power supply circuit of claim 7, wherein:

the first switching device includes another n-type transistor, and

the second, third and fourth switching devices comprise p-type transistors.

9. The power supply circuit of claim 7, wherein the switching converter comprises a boost converter, and wherein the switching transistor comprises a low-side n-type transistor in the boost converter.

10. The power supply circuit of claim 7, wherein the switching converter comprises a buck converter, and wherein the switching transistor comprises a low-side n-type transistor in the buck converter.

11. The power supply circuit of claim 7, wherein the switching converter comprises a charge pump with the switching transistor.

12. The power supply circuit of claim 7, wherein the third switching device comprises a p-type transistor having a drain coupled to the second voltage rail and having a source coupled to the voltage node.

13. A Power Management Integrated Circuit (PMIC) comprising at least a portion of the power circuit of claim 1.

14. A method of supplying power, comprising:

the gate driver is operated to turn on the switching transistor of the switching converter by:

changing a gate voltage of the switching transistor from a first voltage to a second voltage and routing a current through a first path of the gate driver; and

The method further includes changing the gate voltage of the switching transistor from the second voltage to a third voltage and routing current through a second path of the gate driver, the second path being different from the first path.

15. The method of claim 14, wherein changing the gate voltage of the switching transistor from the first voltage to the second voltage comprises:

disconnecting a first switching device coupled between the output of the gate driver and a first voltage rail at the first voltage;

closing a second switching device coupled between the output of the gate driver and a voltage node of the gate driver; and

closing a third switching device coupled between the voltage node of the gate driver and a second voltage rail at the second voltage, wherein the first path of the gate driver includes the second switching device and the third switching device.

16. The method of claim 15, wherein changing the gate voltage of the switching transistor from the second voltage to the third voltage comprises:

opening the third switching means; and

Closing a fourth switching device coupled in series with a voltage clamp, the voltage clamp and the fourth switching device coupled between the voltage node and a third voltage rail, the third voltage rail associated with the third voltage, wherein the second path of the gate driver includes the second switching device, the voltage clamp, and the fourth switching device.

17. The method of claim 16, further comprising:

the gate driver is operated to turn off the switching transistor of the switching converter by:

changing the gate voltage of the switching transistor from the third voltage to the second voltage and routing a current through the first path of the gate driver; and

changing the gate voltage of the switching transistor from the second voltage to the first voltage and routing current through a third path of the gate driver, the non-third path being different from the first path and the second path.

18. The method of claim 17, wherein changing the gate voltage of the switching transistor from the third voltage to the second voltage comprises:

Opening the fourth switching device; and

closing the third switching means.

19. The method of claim 18, wherein changing the gate voltage of the switching transistor from the second voltage to the first voltage comprises:

opening the second switching means; and

closing the first switching means.

20. The method of claim 15, wherein changing the gate voltage of the switching transistor from the second voltage to the third voltage comprises:

opening the third switching means; and

closing a fourth switching device coupled in series with the voltage clamp, the voltage clamp and the fourth switching device coupled between the output of the gate driver and a third voltage rail associated with the third voltage, wherein the second path of the gate driver includes the voltage clamp and the fourth switching device.

21. The method of claim 20, further comprising:

The method further includes changing the gate voltage of the switching transistor from the second voltage to the first voltage and routing current through a third path of the gate driver, the third path being different from the first path and the second path.

22. The method of claim 21, wherein changing the gate voltage of the switching transistor from the third voltage to the second voltage comprises:

opening the fourth switching device; and

closing the third switching means.

23. The method of claim 22, wherein changing the gate voltage of the switching transistor from the second voltage to the first voltage comprises:

opening the second switching means; and

closing the first switching means.

24. The method according to claim 14, wherein:

the switching transistor is a p-type transistor;

the second voltage is lower than the first voltage; and

the third voltage is lower than the second voltage.

25. The method according to claim 14, wherein:

the switching transistor is an n-type transistor;

the second voltage is higher than the first voltage; and

the third voltage is higher than the second voltage.

26. The method of claim 14, further comprising:

27. The method according to claim 14, wherein:

the first path of the gate driver is from a first voltage rail at the first voltage to a second voltage rail at the second voltage; and is also provided with

The second path of the gate driver is from the first voltage rail at the first voltage to a third voltage rail associated with the third voltage.