CN116111980A - gm-TIA-based low-power consumption receiver analog front-end equalization circuit - Google Patents
gm-TIA-based low-power consumption receiver analog front-end equalization circuit Download PDFInfo
- Publication number
- CN116111980A CN116111980A CN202211609210.1A CN202211609210A CN116111980A CN 116111980 A CN116111980 A CN 116111980A CN 202211609210 A CN202211609210 A CN 202211609210A CN 116111980 A CN116111980 A CN 116111980A
- Authority
- CN
- China
- Prior art keywords
- resistor
- nmos tube
- tube
- nmos
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007850 degeneration Effects 0.000 claims abstract description 89
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 230000003071 parasitic effect Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 30
- 238000012546 transfer Methods 0.000 claims description 7
- 238000013461 design Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 230000006872 improvement Effects 0.000 abstract description 5
- 230000008859 change Effects 0.000 abstract description 2
- 238000004891 communication Methods 0.000 abstract description 2
- 238000005265 energy consumption Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 238000012795 verification Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000003780 insertion Methods 0.000 description 4
- 230000037431 insertion Effects 0.000 description 4
- 230000002500 effect on skin Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/32—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/34—Networks for connecting several sources or loads working on different frequencies or frequency bands, to a common load or source
- H03H11/346—Networks for connecting several sources or loads working on different frequencies or frequency bands, to a common load or source particularly adapted as input circuit for receivers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Networks Using Active Elements (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a gm-TIA-based low-power consumption receiver analog front end equalization circuit, and belongs to the field of integrated circuits and communication. The CTLE comprises an adjustable source degeneration structure and a transconductance improvement structure, wherein the adjustable source degeneration structure can change the direct current gain at low frequency by changing the value of control voltage; compared with the traditional CTLE, the transconductance improving structure improves the direct current gain at high frequency; the TIA comprises a primary differential structure and a super source follower structure, and the problem of balance between large size and high parasitic capacitance is solved by utilizing the super source follower structure. The gm-TIA topological structure formed by the feedback resistor and the feedback inductor further improves the overall equalization capacity of the circuit. The invention has simple design, higher gain effect and energy consumption ratio and lower design cost; the method can meet the requirement of high-speed transmission of future data, and provides a reliable equalization scheme for the problem of inter-code crosstalk generated during data transmission.
Description
Technical Field
The invention relates to a gm-TIA-based low-power consumption receiver analog front end equalization circuit, belonging to the field of integrated circuits and communication.
Background
In the age of rapid development of the internet of things technology, high-speed serial interfaces (SerDes) are widely used for data transmission between chips and back plates. However, the design error of the filter and the variation of the channel characteristics always exist a certain inter-symbol interference (ISI) at the sampling time of the system, which ultimately seriously affects the performance of the system, so that an equalization circuit needs to be designed to compensate. In the case of high-speed data transmission, frequency domain equalization has been replaced by time domain equalization, and nonlinear time domain equalization is currently focused as a key module of the analog front end of the receiver in the system. In Integrated Circuit (IC) design, critical issues such as high bandwidth, low power consumption, and feature size are in need of solution. Therefore, a receiver analog front-end circuit design of CTLE with high energy efficiency ratio, low power consumption and high integration level is very important.
Patent CN110022277a discloses a CTLE with adjustable power consumption, the circuit design of which is shown in fig. 8, and includes a CTLE circuit and a bias circuit connected to the CTLE circuit. The bias circuit is composed of a plurality of sub-circuits with MOS connected in sequence, so that the power consumption of the equalizer can be adjusted on the premise that the basic function of the CTLE structure is unchanged, and the low power consumption requirement is met.
Although the scheme can meet the low power consumption requirement of the system, the CTLE still adopts a traditional source degeneration structure, the high-frequency compensation capability of the circuit is limited, and the higher-speed signal transmission is difficult to realize.
Disclosure of Invention
In order to solve the problems, the invention provides a gm-TIA-based low-power consumption receiver analog front end equalization circuit, which comprises the following technical scheme:
a first object of the present invention is to provide a receiver analog front-end equalization circuit comprising in cascade: continuous-time linear equalizer CTLE and transimpedance amplifier TIA, which adopt gm-TIA topology;
and a feedback resistor and a feedback inductor which are connected in series are connected between the output end and the input end of the transimpedance amplifier TIA.
Optionally, the continuous time linear equalizer CTLE includes: an adjustable source degeneration structure and a transconductance enhancement structure;
the tunable source degeneration structure includes: the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the second PMOS tube P2, the third NMOS tube N3 and the fourth NMOS tube N4;
the grid electrode of the first NMOS tube N1 is used as a first input end of the CTLE to be connected with a first input signal, the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1, and the source electrode of the first NMOS tube N1 is connected with the drain electrode of the third NMOS tube N3 and the adjustable source degeneration circuit;
the grid electrode of the second NMOS tube N2 is used as a second input end of the CTLE to be connected with a second input signal, the drain electrode of the second NMOS tube N2 is connected with the drain electrode of the second PMOS tube P2, and the source electrode of the second NMOS tube N2 is connected with the drain electrode of the fourth NMOS tube N4 and the adjustable source degeneration circuit;
the grid electrode of the first PMOS tube P1 is connected with the PMOS current mirror circuit to input PMOS bias voltage, the source electrode of the first PMOS tube P1 is connected with the power supply VDD, and the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1;
the grid electrode of the second PMOS tube P2 is connected with the PMOS current mirror circuit to input PMOS bias voltage, the source electrode of the second PMOS tube P2 is connected with the power supply VDD, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the second NMOS tube N2;
the grid electrode of the third NMOS tube N3 is connected with the NMOS current mirror circuit to input NMOS bias voltage, the source electrode of the third NMOS tube N3 is grounded, and the drain electrode of the third NMOS tube N3 is connected with the source electrode of the first NMOS tube N1;
the grid electrode of the fourth NMOS tube N4 is connected with the NMOS current mirror circuit to input NMOS bias voltage, the source electrode of the fourth NMOS tube N4 is grounded, and the drain electrode of the fourth NMOS tube N4 is connected with the source electrode of the second NMOS tube N2;
the transconductance-enhancing structure includes: the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the first resistor R1 and the second resistor R2;
the grid electrode of the third PMOS tube P3 is respectively connected with the drain electrode of the first NMOS tube N1 and the drain electrode of the first PMOS tube P1, the source electrode of the third PMOS tube P3 is connected with the power supply VDD, and the drain electrode is connected with the adjustable source degeneration circuit and the source electrode of the first NMOS tube N1;
the grid electrode of the fourth PMOS tube P4 is respectively connected with the drain electrode of the second NMOS tube N2 and the drain electrode of the second PMOS tube, the source electrode of the fourth PMOS tube is connected with the power supply VDD, and the drain electrode of the fourth PMOS tube is connected with the adjustable source degeneration circuit and the source electrode of the second NMOS tube N2;
the grid electrode of the fifth PMOS tube P5 is respectively connected with the drain electrode of the first NMOS tube N1 and the drain electrode of the first PMOS tube P1, the source electrode of the fifth PMOS tube P5 is connected with the power supply VDD, and the drain electrode is connected with the first output end of the CTLE and the first end of the first resistor R1;
the grid electrode of the sixth PMOS tube P6 is connected with the drain electrode of the second NMOS tube N2 and the drain electrode of the second PMOS tube P2, the source electrode of the sixth PMOS tube P6 is connected with the power supply VDD, and the drain electrode is connected with the second output end of the CTLE and the first end of the second resistor R2;
the first end of the first resistor R1 is connected with the drain electrode of the fifth PMOS tube P5 and the first output end of the CTLE, and the second end of the first resistor R1 is grounded;
the first end of the second resistor R2 is connected with the drain electrode of the sixth PMOS tube P6 and the second output end of the CTLE, and the second end of the second resistor R2 is grounded;
the adjustable source degeneration circuit changes the low-frequency direct current gain of the whole circuit by adjusting the resistance value, thereby adapting to signals with different transmission rates.
Optionally, the tunable source degeneration circuit includes: a first source degeneration resistor Rg1, a second source degeneration resistor Rg2, a first source degeneration capacitor Cg1, a second source degeneration capacitor Cg2, and a first NMOS switch Nt1;
after the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 are connected in series, the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 are integrally connected between the drains of the first NMOS tube N1 and the second NMOS tube N2 in parallel with the first NMOS switch Nt1;
after the first source degeneration capacitor Cg1 and the second source degeneration capacitor Cg2 are connected in series, the first source degeneration capacitor Cg1 and the second source degeneration capacitor Cg2 are integrally connected between the drains of the first NMOS transistor N1 and the second NMOS transistor N2 in parallel, and are connected in parallel with the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2, and are connected in parallel with the first NMOS switch Nt1;
the gate of the first NMOS switch Nt1 is connected to the tuning voltage input as a control voltage, the drain is connected to the source of the first NMOS transistor N1, and the source is connected to the source of the second NMOS transistor N2.
Optionally, the transimpedance amplifier TIA includes: a first level differential structure and a super source follower structure;
the primary differential structure comprises: a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a seventh PMOS tube P7 and an eighth PMOS tube P8;
the grid electrode of the fifth NMOS tube N5 is connected with the drain electrode of a ninth NMOS tube N9 in the super source follower, the drain electrode of the fifth NMOS tube N5 is connected with the drain electrode of the seventh PMOS tube P7, and the source electrode of the fifth NMOS tube N5 is connected with the drain electrode of the seventh NMOS tube P7 and the TIA first output end;
the grid electrode of the sixth NMOS tube N6 is connected with the drain electrode of a tenth NMOS tube N10 in the super source follower, the drain electrode of the sixth NMOS tube N6 is connected with the drain electrode of the eighth PMOS tube P8, and the source electrode of the sixth NMOS tube N6 is connected with the drain electrode of the eighth NMOS tube P8 and the TIA second output end;
the grid electrode of the seventh PMOS tube P7 is connected with the PMOS current mirror circuit to input bias voltage, the source electrode of the seventh PMOS tube P7 is connected with the power supply VDD, and the drain electrode of the seventh PMOS tube P7 is connected with the drain electrode of the fifth NMOS tube N5;
the grid electrode of the eighth PMOS tube P8 is connected with the PMOS current mirror circuit to input bias voltage, the source electrode of the eighth PMOS tube P8 is connected with the power supply VDD, and the drain electrode of the eighth PMOS tube P8 is connected with the drain electrode of the sixth NMOS tube N6;
the grid electrode of the seventh NMOS tube N7 is connected with the input bias voltage of the NMOS current mirror circuit, the source electrode of the seventh NMOS tube N7 is grounded, and the drain electrode of the seventh NMOS tube N7 is connected with the source electrode of the fifth NMOS tube and the first output end of the TIA;
the grid electrode of the eighth NMOS tube N8 is connected with the input bias voltage of the NMOS current mirror circuit, the source electrode of the eighth NMOS tube N8 is grounded, and the drain electrode of the eighth NMOS tube N8 is connected with the source electrode of the sixth NMOS tube N6 and the second output end of the TIA;
the super source follower includes: a ninth NMOS tube N9, a tenth NMOS tube N10, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;
the grid electrode of the ninth NMOS tube N9 is used as the first input end of the TIA and is connected with the first output end of the CTLE, the drain electrode of the ninth NMOS tube N9 is connected with the second end of the third resistor R3 and the grid electrode of the fifth NMOS tube N5, and the source electrode of the ninth NMOS tube N9 is connected with the first end of the fifth resistor R5;
the first end of the third resistor R3 is connected with a power supply VDD, and the second end of the third resistor R3 is connected with the drain electrode of the ninth NMOS tube N9;
the first end of the fifth resistor R5 is connected with the source electrode of the ninth NMOS tube N9, and the second end of the fifth resistor R5 is grounded;
the gate of the tenth NMOS transistor N10 is used as the second input end of the TIA and connected to the second output end of the CTLE, the drain of the tenth NMOS transistor N10 is connected to the second end of the fourth resistor R4 and the gate of the sixth NMOS transistor N6, and the source of the ninth NMOS transistor N9 is connected to the first end of the sixth resistor R6;
the first end of the fourth resistor R4 is connected with the power supply VDD, and the second end of the fourth resistor R4 is connected with the drain electrode of the tenth NMOS tube N10;
the first end of the sixth resistor R6 is connected to the source of the tenth NMOS transistor N10, and the second end of the sixth resistor R6 is grounded.
Optionally, the feedback resistor and the feedback inductor include: a seventh resistor R7, an eighth resistor R8, a first inductance L1 and a second inductance L2;
a first end of the first inductor L1 is connected with a first input end of the TIA, and a second end of the first inductor L1 is connected with a first end of the seventh resistor R7;
a first end of the seventh resistor R7 is connected with the second end of the first inductor L1, and a second end of the seventh resistor R7 is connected with the first output end of the TIA;
a first end of the second inductor L2 is connected with a second input end of the TIA, and a second end of the second inductor L2 is connected with a first end of the eighth resistor R8;
the first end of the eighth resistor R8 is connected with the second end of the second inductor L2, and the second end of the eighth resistor R8 is connected with the second output end of the TIA.
Alternatively, the transfer function of the CTLE is expressed as:
wherein omega Z Zero point, omega P1 For the first pole, omega P2 The second pole is respectively the following value:
wherein g m Is the transconductance of the first NMOS tube N1 and the second NMOS tube N2, A 0 For applying gain to transconductance of the first NMOS transistor N1 and the second NMOS transistor N2, wherein R S For source degeneration resistance, C S R is the source degeneration capacitance value L Parasitic load resistance value of CTLE output node, C L Parasitic load capacitance value for CTLE output node.
Optionally, the CTLE has a dc gain of:
optionally, the transfer function formula of the receiver analog front-end circuit is:
wherein:
in the above formula, for convenience of expression, let
Wherein A is DC Represents the overall DC gain g m,TIA Representing the total transconductance of TIA, R F Represents the feedback resistance value, C LL Representing the parasitic load capacitance value of TIA output node, R D Representing TIA output node parasitic load resistance, L F Representing feedback inductance value
Optionally, the values of the third resistor R3 and the fourth resistor R4 are larger than the values of the fifth resistor R5 and the sixth resistor R6.
A second object of the present invention is to provide a receiver analog front-end equalization method, implemented based on the above-mentioned receiver analog front-end equalization circuit, comprising: and an input alternating current signal is accessed from a first input end and a second input end of the CTLE, and the signals are output by a first output end and a second output end of the TIA after being equalized by the analog front-end equalization circuit of the receiver.
The invention has the beneficial effects that:
the gm-TIA-based low-power consumption receiver analog front-end equalization circuit comprises the continuous-time linear equalizer CTLE and the transimpedance amplifier TIA, and the gm-TIA structure is integrally adopted, so that the performance of the circuit can be remarkably improved.
Furthermore, the continuous time linear equalizer CTLE of the invention uses the third PMOS tube and the fourth PMOS tube as transconductance enhancement circuits, samples signals from the drains of the first NMOS tube and the second NMOS tube, and establishes feedback by connecting the drains with the source degeneration resistor and capacitor as a feedback stage. The third PMOS tube and the fourth PMOS tube can be equivalent to an operational amplifier, and the drain voltages of the first NMOS tube and the second NMOS tube are locked according to the virtual short and the virtual break of the operational amplifier, and the output voltages of the operational amplifier are sampled. Because the output voltage is sampled, in order to ensure that the output voltage of feedback sampling is equal to the input voltage, the output impedance of the circuit is reduced, and the transconductance gm is equivalently improved. The fifth PMOS tube and the sixth PMOS tube are connected with the output end and the load resistor and serve as a source-stage follower to improve linearity and reduce gain loss caused by low impedance. The source degeneration capacitor resistor still plays a role of passing high frequency resistance and low frequency, a zero pole is added to the basic filter structure, so that the requirement of high gain at high frequency is met, and an adjustable structure is added, so that the change of resistance values can be adjusted according to different input voltages, and further the low frequency direct current gain of the whole circuit is changed, and signals with different transmission rates are adapted; compared with the CTLE with the traditional source degeneration structure, the CTLE designed by the invention has better balance effect under smaller area and power consumption.
Further, the transimpedance amplifier TIA of the present invention is improved over conventional differential amplifier structures. In a conventional gm-TIA architecture, there is a trade-off between dc operating point and circuit performance. To obtain a proper dc operating point, the PMOS size needs to be increased, which introduces a larger parasitic capacitance on the output node, resulting in a reduced bandwidth of the circuit. To solve this problem, a super source follower structure is used in the TIA design, which can reduce the output impedance by increasing the total current flowing into the output node, avoiding the trade-off between gain and bandwidth caused by oversized PMOS.
The power consumption of the whole circuit is only 9.7mW, and compared with the traditional equalizer, the circuit has lower power consumption, simple structure and easy realization, and has more excellent equalizing effect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a complete architecture diagram of a receiver analog front-end equalization circuit of the present invention.
Fig. 2 is an adjustable source degeneration circuit of the present invention.
Fig. 3 is a schematic diagram of equivalent circuits of an NMOS input current mirror and a PMOS input current mirror according to the present invention, where (a) is the NMOS input current mirror and (b) is the PMOS input current mirror.
Fig. 4 is a graph showing the frequency response of an integrated receiver analog front end according to the present invention as a function of the source degeneration circuit regulated voltage Vctrl.
Fig. 5 is a plot of insertion loss and return loss for a pcie3.0 channel of the present invention.
Fig. 6 is an eye diagram of a signal at 10Gbps without turning on and turning on a receiver circuit through a pcie3.0 channel transmission line according to an embodiment of the present invention.
Fig. 7 is an eye diagram of a signal at 14Gbps without turning on and turning on a receiver circuit through a pcie3.0 channel transmission line according to an embodiment of the present invention.
Fig. 8 is a circuit diagram of a CTLE with adjustable power consumption in the prior art.
The reference numerals are explained as follows:
the circuit comprises a CTLE circuit 101, a first input end of the CTLE, 102, a second input end of the CTLE, 103, a first input end of the PMOS tube bias voltage CTLE, 104, a second input end of the PMOS tube bias voltage CTLE, 105, a first input end of the NMOS tube bias voltage CTLE, 106, a second input end of the NMOS tube bias voltage CTLE, 107, a first output end of the CTLE, 108 and a second output end of the CTLE.
3. Feedback resistance and feedback inductance.
4. Return loss.
5. Insertion loss.
N1, a first NMOS tube, N2, a second NMOS tube, P1, a first PMOS tube, P2, a second PMOS tube, P3, a third PMOS tube, P4, a fourth PMOS tube, N3, a third NMOS tube, N4, a fourth NMOS tube, P5, a fifth PMOS tube, P6, a sixth PMOS tube, R1, a first resistor, R2, a second resistor, C1, a first capacitor, C2 and a second capacitor; n5, fifth NMOS tube, N6, sixth NMOS tube, N7 seventh NMOS tube, N8, eighth NMOS tube, N9, ninth NMOS tube, N10, tenth NMOS tube, P7, seventh PMOS tube, P8, eighth PMOS tube, R3, third resistor, R4, fourth resistor, R5, fifth resistor, R6, sixth resistor; l1, a first inductor, L2, a second inductor, R7, a seventh resistor, R8 and an eighth resistor; c3, third capacitor, C4, fourth capacitor; rg1, a first source degeneration resistor, rg2, a second source degeneration resistor, cg1, a first source degeneration capacitor, cg2, a second source degeneration capacitor, nt1 and an NMOS switch; vbiasp, PMOS bias voltage, vbiasn, NMOS bias voltage.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Embodiment one:
the embodiment provides an analog front-end equalization circuit of a receiver, which comprises the following cascaded components: continuous-time linear equalizer CTLE and transimpedance amplifier TIA, continuous-time linear equalizer CTLE and transimpedance amplifier TIA adopt gm-TIA topological structure;
and a feedback resistor and a feedback inductor which are connected in series are connected between the output end and the input end of the transimpedance amplifier TIA.
Embodiment two:
the embodiment provides an analog front-end equalization circuit of a receiver, which comprises the following cascaded components: continuous-time linear equalizer CTLE and transimpedance amplifier TIA, continuous-time linear equalizer CTLE and transimpedance amplifier TIA adopt gm-TIA topological structure;
and a feedback resistor and a feedback inductor which are connected in series are connected between the output end and the input end of the transimpedance amplifier TIA.
The continuous time linear equalizer CTLE includes: a tunable source degeneration structure and a transconductance enhancement structure.
The tunable source degeneration structure of this embodiment includes: the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the second PMOS tube P2, the third NMOS tube N3 and the fourth NMOS tube N4;
the grid electrode of the first NMOS tube N1 is used as a first input end of the CTLE to be connected with a first input signal, the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1, and the source electrode of the first NMOS tube N1 is connected with the drain electrode of the third NMOS tube N3 and the adjustable source degeneration circuit;
the grid electrode of the second NMOS tube N2 is used as a second input end of the CTLE to be connected with a second input signal, the drain electrode of the second NMOS tube N2 is connected with the drain electrode of the second PMOS tube P2, and the source electrode of the second NMOS tube N2 is connected with the drain electrode of the fourth NMOS tube N4 and the adjustable source degeneration circuit;
the grid electrode of the first PMOS tube P1 is connected with the PMOS bias voltage input by the PMOS current mirror circuit, the source electrode of the first PMOS tube P1 is connected with the power supply VDD, and the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1;
the grid electrode of the second PMOS tube P2 is connected with the PMOS bias voltage input by the PMOS current mirror circuit, the source electrode of the second PMOS tube P2 is connected with the power supply VDD, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the second NMOS tube N2;
the grid electrode of the third NMOS tube N3 is connected with the NMOS bias voltage input by the NMOS current mirror circuit, the source electrode of the third NMOS tube N3 is grounded, and the drain electrode of the third NMOS tube N3 is connected with the source electrode of the first NMOS tube N1;
the grid electrode of the fourth NMOS tube N4 is connected with the NMOS bias voltage input by the NMOS current mirror circuit, the source electrode of the fourth NMOS tube N4 is grounded, and the drain electrode of the fourth NMOS tube N4 is connected with the source electrode of the second NMOS tube N2;
the transconductance enhancing structure of the present embodiment includes: the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the first resistor R1 and the second resistor R2;
the grid electrode of the third PMOS tube P3 is respectively connected with the drain electrode of the first NMOS tube N1 and the drain electrode of the first PMOS tube P1, the source electrode of the third PMOS tube P3 is connected with the power supply VDD, and the drain electrode is connected with the adjustable source degeneration circuit and the source electrode of the first NMOS tube N1;
the grid electrode of the fourth PMOS tube P4 is respectively connected with the drain electrode of the second NMOS tube N2 and the drain electrode of the second PMOS tube, the source electrode of the fourth PMOS tube is connected with the power supply VDD, and the drain electrode is connected with the adjustable source degeneration circuit and the source electrode of the second NMOS tube N2;
the grid electrode of the fifth PMOS tube P5 is respectively connected with the drain electrode of the first NMOS tube N1 and the drain electrode of the first PMOS tube P1, the source electrode of the fifth PMOS tube P5 is connected with the power supply VDD, and the drain electrode is connected with the first output end of the CTLE and the first end of the first resistor R1;
the grid electrode of the sixth PMOS tube P6 is connected with the drain electrode of the second NMOS tube N2 and the drain electrode of the second PMOS tube P2, the source electrode of the sixth PMOS tube P6 is connected with the power supply VDD, and the drain electrode is connected with the second output end of the CTLE and the first end of the second resistor R2;
the first end of the first resistor R1 is connected with the drain electrode of the fifth PMOS tube P5 and the first output end of the CTLE, and the second end of the first resistor R1 is grounded;
the first end of the second resistor R2 is connected with the drain electrode of the sixth PMOS tube P6 and the second output end of the CTLE, and the second end of the second resistor R2 is grounded;
the adjustable source degeneration circuit changes the low-frequency direct current gain of the whole circuit by adjusting the resistance value, thereby adapting to signals with different transmission rates.
The tunable source degeneration circuit of this embodiment includes: a first source degeneration resistor Rg1, a second source degeneration resistor Rg2, a first source degeneration capacitor Cg1, a second source degeneration capacitor Cg2, and a first NMOS switch Nt1;
after the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 are connected in series, the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 are integrally connected between the drains of the first NMOS tube N1 and the second NMOS tube N2 in a bridging manner, and are connected with the first NMOS switch Nt1 in parallel;
after the first source degeneration capacitor Cg1 and the second source degeneration capacitor Cg2 are connected in series, the first source degeneration capacitor Cg1 and the second source degeneration capacitor Cg2 are integrally connected between the drains of the first NMOS tube N1 and the second NMOS tube N2 in parallel, and are connected with the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 in parallel and the first NMOS switch Nt1 in parallel;
the gate of the first NMOS switch Nt1 is connected with a tuning voltage input as a control voltage, the drain is connected with the source of the first NMOS tube N1, and the source is connected with the source of the second NMOS tube N2.
The transimpedance amplifier TIA of the present embodiment includes: a first level differential structure and a super source follower structure;
the first-order differential structure of the present embodiment includes: a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a seventh PMOS tube P7 and an eighth PMOS tube P8;
the grid electrode of the fifth NMOS tube N5 is connected with the drain electrode of a ninth NMOS tube N9 in the super source follower, the drain electrode of the fifth NMOS tube N5 is connected with the drain electrode of a seventh PMOS tube P7, and the source electrode of the fifth NMOS tube N5 is connected with the drain electrode of the seventh NMOS tube P7 and the first output end of the TIA;
the grid electrode of the sixth NMOS tube N6 is connected with the drain electrode of a tenth NMOS tube N10 in the super source follower, the drain electrode of the sixth NMOS tube N6 is connected with the drain electrode of an eighth PMOS tube P8, and the source electrode of the sixth NMOS tube N6 is connected with the drain electrode of the eighth NMOS tube P8 and the second output end of the TIA;
the grid electrode of the seventh PMOS tube P7 is connected with the PMOS current mirror circuit to input bias voltage, the source electrode of the seventh PMOS tube P7 is connected with the power supply VDD, and the drain electrode of the seventh PMOS tube P7 is connected with the drain electrode of the fifth NMOS tube N5;
the grid electrode of the eighth PMOS tube P8 is connected with the PMOS current mirror circuit to input bias voltage, the source electrode of the eighth PMOS tube P8 is connected with the power supply VDD, and the drain electrode of the eighth PMOS tube P8 is connected with the drain electrode of the sixth NMOS tube N6;
the grid electrode of the seventh NMOS tube N7 is connected with the input bias voltage of the NMOS current mirror circuit, the source electrode of the seventh NMOS tube N7 is grounded, and the drain electrode of the seventh NMOS tube N7 is connected with the source electrode of the fifth NMOS tube and the first output end of the TIA;
the grid electrode of the eighth NMOS tube N8 is connected with the input bias voltage of the NMOS current mirror circuit, the source electrode of the eighth NMOS tube N8 is grounded, and the drain electrode of the eighth NMOS tube N8 is connected with the source electrode of the sixth NMOS tube N6 and the second output end of the TIA;
the super source follower of the present embodiment includes: a ninth NMOS tube N9, a tenth NMOS tube N10, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;
the grid electrode of the ninth NMOS tube N9 is used as a first input end of the TIA and is connected with a first output end of the CTLE, the drain electrode of the ninth NMOS tube N9 is connected with the second end of the third resistor R3 and the grid electrode of the fifth NMOS tube N5, and the source electrode of the ninth NMOS tube N9 is connected with the first end of the fifth resistor R5;
the first end of the third resistor R3 is connected with the power supply VDD, and the second end of the third resistor R3 is connected with the drain electrode of the ninth NMOS tube N9;
the first end of the fifth resistor R5 is connected with the source electrode of the ninth NMOS tube N9, and the second end of the fifth resistor R5 is grounded;
the grid electrode of the tenth NMOS tube N10 is used as a second input end of the TIA and is connected with a second output end of the CTLE, the drain electrode of the tenth NMOS tube N10 is connected with the second end of the fourth resistor R4 and the grid electrode of the sixth NMOS tube N6, and the source electrode of the ninth NMOS tube N9 is connected with the first end of the sixth resistor R6;
the first end of the fourth resistor R4 is connected with the power supply VDD, and the second end of the fourth resistor R4 is connected with the drain electrode of the tenth NMOS tube N10;
the first end of the sixth resistor R6 is connected with the source electrode of the tenth NMOS tube N10, and the second end of the sixth resistor R6 is grounded.
The feedback resistor and feedback inductor of the present embodiment include: a seventh resistor R7, an eighth resistor R8, a first inductance L1 and a second inductance L2;
the first end of the first inductor L1 is connected with the first input end of the TIA, and the second end of the first inductor L1 is connected with the first end of the seventh resistor R7;
the first end of the seventh resistor R7 is connected with the second end of the first inductor L1, and the second end of the seventh resistor R7 is connected with the first output end of the TIA;
the first end of the second inductor L2 is connected with the second input end of the TIA, and the second end of the second inductor L2 is connected with the first end of the eighth resistor R8;
the first end of the eighth resistor R8 is connected with the second end of the second inductor L2, and the second end of the eighth resistor R8 is connected with the second output end of the TIA.
The embodiment provides an analog front-end circuit of a SerDes receiver composed of CTLE and TIA with adjustable power consumption, which can send a transmission signal with a specific rate under a lossy channel and observe the equalization capability of the whole circuit to the signal.
In order to further verify the equalizing effect of the equalizing circuit of the present invention on signal transmission, experimental verification was performed, and as shown in fig. 1, the circuit of the present experiment is composed of a terminal with a differential impedance of 100 ohms, a CTLE and a TIA. The input of the circuit is matched with the device by adopting a 100 ohm resistor, and NRZ signals with different frequencies are input. The high efficiency and feasibility of the present invention was verified using 10Gbps and 14Gbps rates in this example. The CTLE and TIA adopt gm-TIA topological structures to compensate channel loss at 5GHz and 7GHz Nyquist frequencies respectively, and output amplitude is adjusted under the condition of not influencing bandwidth attenuation.
The first input end of the CTLE and the second input end of the CTLE are connected with input alternating current signals, signals are output by the first output end of the TIA and the second output end of the TIA after being balanced by the whole circuit, and then follow-up processing is carried out on data.
The circuit design diagram of CTLE is shown in fig. 1, and as the first stage of the circuit of the front end of SerDes receiver, the amplitude of the input signal and the attenuation loss of the channel can be matched by tuning by using the adjustable source degeneration structure, so as to obtain good linearity. In fig. 2, a resistor Rg1, a resistor Rg2, a capacitor Cg1 and a capacitor Cg2 are used as source degeneration resistors and capacitors to be connected with a first NMOS switch, and the resistance is adjusted by an input voltage Vctrl, so that the position of a zero pole of a circuit is changed, and further, the requirements of different transmission rates of signals are met; after that, the signals are equalized by the analog front-end circuit of the receiver designed by the invention after passing through the channel, and the final signals are output by the TIA first output end and the TIA second output end.
The external current mirrors of the first PMOS transistor P1, the second PMOS transistor P2, the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are shown in fig. 3, and Vbiasn and Vbiasp are used as bias voltage inputs, and the driving circuit maintains the stability of high frequency. In order to meet the requirements of high bandwidth and high gain, the CTLE of the AFE front end is shown in fig. 1, and the improvement of the dc gain at the high frequency of the equalizer by using the transconductance improvement technology is considered first, wherein the third PMOS transistor P3 and the fourth PMOS transistor P4 can be equivalently used as an operational amplifier structure, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are equivalently used as source followers, the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 can be regarded as input ends, and the output endsThe ends of the third PMOS tube P3 and the fourth PMOS tube P4 are connected with the source degeneration resistor and the source degeneration capacitor, and feedback is completed from the source stages of the first NMOS tube N1 and the second NMOS tube N2; applying gain to transconductance of the first NMOS transistor N1 and the second NMOS transistor N2, namely small signal open loop gain A of transconductance amplifier 0 This is the product of their transconductance multiplied by the output node impedance, the modified transconductance becomes g m (1+A 0 ). Wherein g m The transconductance of the first NMOS transistor N1 and the second NMOS transistor N2. The first PMOS transistor P1, the second PMOS transistor P2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are responsible for generating a quiescent current, instead of a current source driving circuit.
Wherein, the transfer function of CTLE can be expressed as:
wherein omega Z Zero point, omega P1 For the first pole, omega P2 For the second pole, they take the values:
according to the formula, compared with CTLE of a traditional structure, the invention improves the DC gain at high frequency due to the improvement of transconductance, and the low-frequency DC gain of the circuit is adjustable through a stable and adjustable source degeneration structure, and the DC gain of the circuit is expressed as follows:
the TIA and CTLE adopted by the invention are cascaded to improve the bandwidth and gain of the equalizing circuit, and as shown in figure 1, the TIA adopts a super source follower structure on the basis of a primary differential structure, and the total transconductance of the TIA is equivalent to the parallel summation of the transconductance of a fifth NMOS tube N5 and a ninth PMOS tube P9. This structure keeps the product of the resistance and capacitance of the parasitic node output constant and minimizes it to achieve greater bandwidth operation.
As shown in FIG. 1, the fifth NMOS tube N5 and the sixth NMOS tube N6 are used as amplifying stages, signals after being balanced by the first-stage equalizer are input, the seventh PMOS tube P7 and the eighth PMOS tube P8 are driven by a PMOS current mirror to replace a load resistor, the gain at a high frequency is kept, the seventh NMOS tube N7 and the eighth NMOS tube N8 are connected with an NMOS current mirror to input NMOS bias voltage, an equivalent high-impedance current source is used for driving the whole circuit, the ninth NMOS tube N9 and the tenth NMOS tube N10 respectively form a super source follower with a third resistor R3, a fifth resistor R5, a fourth resistor R4 and a sixth resistor R6, the bandwidth and the gain of the amplifier are improved, the circuit current is controlled by the resistor, from the direct current angle analysis, the current sources are essentially replaced by resistors, and therefore, the direct current is equivalent to the alternating current generated by the amplifier only by the values larger than that of the fifth resistor R5 and the sixth resistor R6, and normal operation is realized.
As shown in fig. 1, a gm-TIA topology of TIA circuits and CTLEs is described, which connects the output of CTLE to TIA input, and TIA output and input cross-connect feedback resistor and feedback inductance, spreading its peak to higher frequencies.
In the invention, the overall SerDes receiver analog front end circuit transfer function formula is as follows:
wherein:
in the above expression, for convenience of expression, let
It can be seen that the transfer function introduces a zero point and a pole point in addition to the traditional CTLE, and has transconductance improvement compared with the traditional CTLE, thereby solving the defects of high gain and low bandwidth of the traditional CTLE.
The verification example provided by the invention uses PCIE3.0 protocol hard disk to transmit data to verify the feasibility of the invention.
In the verification example provided by the invention, the NRZ coding signals with the rates of 10Gbps and 14Gbps generated by a transmitter are respectively simulated for verification, the frequency response curve of the designed receiver front-end equalization circuit is shown in fig. 4, the frequency at the peak value is 7GHz, the gain is 13.2dB, and the direct current gain at different low frequencies can be changed through the difference of the input voltage Vctrl due to the fact that the source degeneration resistance is an adjustable structure, and meanwhile, the peak value gain is kept unchanged so as to be suitable for channels with different propagation speeds and different losses; the insertion loss and return loss data for the pcie3.0 channel used in the verification example is shown in fig. 5.
First, a signal with an analog transmission rate of 10Gbps passes through a channel with an insertion loss of-13.3 dB and a return loss of-16.5 dB at the nyquist frequency of 5GHz at its rate. The analog front-end circuit of the receiver designed by the invention compensates the loss caused by the skin effect of the channel, and the obtained eye diagram is shown in figure 6, when the equalization circuit is not opened, the eye diagram is completely closed, when the equalization circuit is opened, the eye diagram is about 1.07V, and the eye width is opened by about 0.83UI, so that the equalization effect is ideal.
By varying the regulated voltage Vctrl as a signal at a transmission rate of 14Gbps passes through the channel, the dc gain of the signal at low frequencies is affected and the high frequency gain is maintained constant to prevent over-equalization. The 7GHz loss of the channel at its Nyquist frequency is-18.2 dB and-22.2 dB, respectively. The signal is equalized through the designed front end of the receiver, so that the loss caused by the skin effect of the channel is compensated, the equalized eye diagram is shown in fig. 7, the eye height is about 0.68V after equalization when the opening degree of the non-equalizer is 0, and the eye width is opened by about 0.82UI, so that the ideal equalization effect is also achieved.
In summary, the analog front-end circuit of the SerDes receiver designed by the invention uses a transconductance boosting technology, a gm-TIA topological structure and TIA using a super source follower technology, so that the SerDes receiver has larger bandwidth and higher high-frequency gain; and the NMOS switch can be used for adjusting the resistance value of the source degeneration resistor, so that the DC gain at low frequency is changed to adapt to different transmission rates. In the verification example, signals at different speeds can be effectively balanced after passing through PCIE3.0 channels, so that tailing effect is reduced from the system perspective, and inter-code crosstalk is removed.
Some steps in the embodiments of the present invention may be implemented by using software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A receiver analog front-end equalization circuit, the receiver analog front-end equalization circuit comprising a cascade connection: continuous-time linear equalizer CTLE and transimpedance amplifier TIA, which adopt gm-TIA topology;
and a feedback resistor and a feedback inductor which are connected in series are connected between the output end and the input end of the transimpedance amplifier TIA.
2. The receiver analog front-end equalization circuit of claim 1, wherein the continuous-time linear equalizer CTLE comprises: an adjustable source degeneration structure and a transconductance enhancement structure;
the tunable source degeneration structure includes: the first NMOS tube N1, the second NMOS tube N2, the first PMOS tube P1, the second PMOS tube P2, the third NMOS tube N3 and the fourth NMOS tube N4;
the grid electrode of the first NMOS tube N1 is used as a first input end of the CTLE to be connected with a first input signal, the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1, and the source electrode of the first NMOS tube N1 is connected with the drain electrode of the third NMOS tube N3 and the adjustable source degeneration circuit;
the grid electrode of the second NMOS tube N2 is used as a second input end of the CTLE to be connected with a second input signal, the drain electrode of the second NMOS tube N2 is connected with the drain electrode of the second PMOS tube P2, and the source electrode of the second NMOS tube N2 is connected with the drain electrode of the fourth NMOS tube N4 and the adjustable source degeneration circuit;
the grid electrode of the first PMOS tube P1 is connected with the PMOS current mirror circuit to input PMOS bias voltage, the source electrode of the first PMOS tube P1 is connected with the power supply VDD, and the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1;
the grid electrode of the second PMOS tube P2 is connected with the PMOS current mirror circuit to input PMOS bias voltage, the source electrode of the second PMOS tube P2 is connected with the power supply VDD, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the second NMOS tube N2;
the grid electrode of the third NMOS tube N3 is connected with the NMOS current mirror circuit to input NMOS bias voltage, the source electrode of the third NMOS tube N3 is grounded, and the drain electrode of the third NMOS tube N3 is connected with the source electrode of the first NMOS tube N1;
the grid electrode of the fourth NMOS tube N4 is connected with the NMOS current mirror circuit to input NMOS bias voltage, the source electrode of the fourth NMOS tube N4 is grounded, and the drain electrode of the fourth NMOS tube N4 is connected with the source electrode of the second NMOS tube N2;
the transconductance-enhancing structure includes: the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the first resistor R1 and the second resistor R2;
the grid electrode of the third PMOS tube P3 is respectively connected with the drain electrode of the first NMOS tube N1 and the drain electrode of the first PMOS tube P1, the source electrode of the third PMOS tube P3 is connected with the power supply VDD, and the drain electrode is connected with the adjustable source degeneration circuit and the source electrode of the first NMOS tube N1;
the grid electrode of the fourth PMOS tube P4 is respectively connected with the drain electrode of the second NMOS tube N2 and the drain electrode of the second PMOS tube, the source electrode of the fourth PMOS tube is connected with the power supply VDD, and the drain electrode of the fourth PMOS tube is connected with the adjustable source degeneration circuit and the source electrode of the second NMOS tube N2;
the grid electrode of the fifth PMOS tube P5 is respectively connected with the drain electrode of the first NMOS tube N1 and the drain electrode of the first PMOS tube P1, the source electrode of the fifth PMOS tube P5 is connected with the power supply VDD, and the drain electrode is connected with the first output end of the CTLE and the first end of the first resistor R1;
the grid electrode of the sixth PMOS tube P6 is connected with the drain electrode of the second NMOS tube N2 and the drain electrode of the second PMOS tube P2, the source electrode of the sixth PMOS tube P6 is connected with the power supply VDD, and the drain electrode is connected with the second output end of the CTLE and the first end of the second resistor R2;
the first end of the first resistor R1 is connected with the drain electrode of the fifth PMOS tube P5 and the first output end of the CTLE, and the second end of the first resistor R1 is grounded;
the first end of the second resistor R2 is connected with the drain electrode of the sixth PMOS tube P6 and the second output end of the CTLE, and the second end of the second resistor R2 is grounded;
the adjustable source degeneration circuit changes the low-frequency direct current gain of the whole circuit by adjusting the resistance value, thereby adapting to signals with different transmission rates.
3. The receiver analog front end equalization circuit of claim 2, wherein said adjustable source degeneration circuit comprises: a first source degeneration resistor Rg1, a second source degeneration resistor Rg2, a first source degeneration capacitor Cg1, a second source degeneration capacitor Cg2, and a first NMOS switch Nt1;
after the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 are connected in series, the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2 are integrally connected between the drains of the first NMOS tube N1 and the second NMOS tube N2 in parallel with the first NMOS switch Nt1;
after the first source degeneration capacitor Cg1 and the second source degeneration capacitor Cg2 are connected in series, the first source degeneration capacitor Cg1 and the second source degeneration capacitor Cg2 are integrally connected between the drains of the first NMOS transistor N1 and the second NMOS transistor N2 in parallel, and are connected in parallel with the first source degeneration resistor Rg1 and the second source degeneration resistor Rg2, and are connected in parallel with the first NMOS switch Nt1;
the gate of the first NMOS switch Nt1 is connected to the tuning voltage input as a control voltage, the drain is connected to the source of the first NMOS transistor N1, and the source is connected to the source of the second NMOS transistor N2.
4. The receiver analog front end equalization circuit of claim 3, wherein said transimpedance amplifier TIA comprises: a first level differential structure and a super source follower structure;
the primary differential structure comprises: a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a seventh PMOS tube P7 and an eighth PMOS tube P8;
the grid electrode of the fifth NMOS tube N5 is connected with the drain electrode of a ninth NMOS tube N9 in the super source follower, the drain electrode of the fifth NMOS tube N5 is connected with the drain electrode of the seventh PMOS tube P7, and the source electrode of the fifth NMOS tube N5 is connected with the drain electrode of the seventh NMOS tube P7 and the TIA first output end;
the grid electrode of the sixth NMOS tube N6 is connected with the drain electrode of a tenth NMOS tube N10 in the super source follower, the drain electrode of the sixth NMOS tube N6 is connected with the drain electrode of the eighth PMOS tube P8, and the source electrode of the sixth NMOS tube N6 is connected with the drain electrode of the eighth NMOS tube P8 and the TIA second output end;
the grid electrode of the seventh PMOS tube P7 is connected with the PMOS current mirror circuit to input bias voltage, the source electrode of the seventh PMOS tube P7 is connected with the power supply VDD, and the drain electrode of the seventh PMOS tube P7 is connected with the drain electrode of the fifth NMOS tube N5;
the grid electrode of the eighth PMOS tube P8 is connected with the PMOS current mirror circuit to input bias voltage, the source electrode of the eighth PMOS tube P8 is connected with the power supply VDD, and the drain electrode of the eighth PMOS tube P8 is connected with the drain electrode of the sixth NMOS tube N6;
the grid electrode of the seventh NMOS tube N7 is connected with the input bias voltage of the NMOS current mirror circuit, the source electrode of the seventh NMOS tube N7 is grounded, and the drain electrode of the seventh NMOS tube N7 is connected with the source electrode of the fifth NMOS tube and the first output end of the TIA;
the grid electrode of the eighth NMOS tube N8 is connected with the input bias voltage of the NMOS current mirror circuit, the source electrode of the eighth NMOS tube N8 is grounded, and the drain electrode of the eighth NMOS tube N8 is connected with the source electrode of the sixth NMOS tube N6 and the second output end of the TIA;
the super source follower includes: a ninth NMOS tube N9, a tenth NMOS tube N10, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;
the grid electrode of the ninth NMOS tube N9 is used as the first input end of the TIA and is connected with the first output end of the CTLE, the drain electrode of the ninth NMOS tube N9 is connected with the second end of the third resistor R3 and the grid electrode of the fifth NMOS tube N5, and the source electrode of the ninth NMOS tube N9 is connected with the first end of the fifth resistor R5;
the first end of the third resistor R3 is connected with a power supply VDD, and the second end of the third resistor R3 is connected with the drain electrode of the ninth NMOS tube N9;
the first end of the fifth resistor R5 is connected with the source electrode of the ninth NMOS tube N9, and the second end of the fifth resistor R5 is grounded;
the gate of the tenth NMOS transistor N10 is used as the second input end of the TIA and connected to the second output end of the CTLE, the drain of the tenth NMOS transistor N10 is connected to the second end of the fourth resistor R4 and the gate of the sixth NMOS transistor N6, and the source of the ninth NMOS transistor N9 is connected to the first end of the sixth resistor R6;
the first end of the fourth resistor R4 is connected with the power supply VDD, and the second end of the fourth resistor R4 is connected with the drain electrode of the tenth NMOS tube N10;
the first end of the sixth resistor R6 is connected to the source of the tenth NMOS transistor N10, and the second end of the sixth resistor R6 is grounded.
5. The receiver analog front end equalization circuit of claim 4, wherein said feedback resistor and feedback inductance comprise: a seventh resistor R7, an eighth resistor R8, a first inductance L1 and a second inductance L2;
a first end of the first inductor L1 is connected with a first input end of the TIA, and a second end of the first inductor L1 is connected with a first end of the seventh resistor R7;
a first end of the seventh resistor R7 is connected with the second end of the first inductor L1, and a second end of the seventh resistor R7 is connected with the first output end of the TIA;
a first end of the second inductor L2 is connected with a second input end of the TIA, and a second end of the second inductor L2 is connected with a first end of the eighth resistor R8;
the first end of the eighth resistor R8 is connected with the second end of the second inductor L2, and the second end of the eighth resistor R8 is connected with the second output end of the TIA.
6. The receiver analog front-end equalization circuit of claim 5, wherein the transfer function of the CTLE is expressed as:
wherein omega Z Zero point, omega P1 For the first pole, omega P2 The second pole is respectively the following value:
wherein g m Is the transconductance of the first NMOS tube N1 and the second NMOS tube N2, A 0 Gain applied to the transconductance of the first NMOS transistor N1 and the second NMOS transistor N2; r is R S For source degeneration resistance, C S R is the source degeneration capacitance value L Parasitic load resistance value of CTLE output node, C L Parasitic load capacitance value for CTLE output node.
7. The receiver analog front-end equalization circuit of claim 6, wherein the CTLE has a dc gain of:
8. the receiver analog front-end equalization circuit of claim 7, wherein the transfer function equation of the receiver analog front-end circuit is:
wherein, let the
Wherein A is DC Represents the overall DC gain g m,TIA Representing the total transconductance, R, of TIA device F Represents the feedback resistance value, C LL Representing the parasitic load capacitance value of TIA output node, R D Representing TIA output node parasitic load resistance, L F Representing the feedback inductance value.
9. The receiver analog front-end equalization circuit of claim 5, wherein the values of said third resistor R3 and fourth resistor R4 are greater than the values of said fifth resistor R5 and sixth resistor R6.
10. A method of receiver analog front end equalization, the method being implemented based on the receiver analog front end equalization circuit of any of claims 1-9, comprising: and an input alternating current signal is accessed from a first input end and a second input end of the CTLE, and the signals are output by a first output end and a second output end of the TIA after being equalized by the analog front-end equalization circuit of the receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211609210.1A CN116111980A (en) | 2022-12-14 | 2022-12-14 | gm-TIA-based low-power consumption receiver analog front-end equalization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211609210.1A CN116111980A (en) | 2022-12-14 | 2022-12-14 | gm-TIA-based low-power consumption receiver analog front-end equalization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116111980A true CN116111980A (en) | 2023-05-12 |
Family
ID=86257156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211609210.1A Pending CN116111980A (en) | 2022-12-14 | 2022-12-14 | gm-TIA-based low-power consumption receiver analog front-end equalization circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116111980A (en) |
-
2022
- 2022-12-14 CN CN202211609210.1A patent/CN116111980A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10313165B2 (en) | Finite impulse response analog receive filter with amplifier-based delay chain | |
| US10116470B2 (en) | Combined low and high frequency continuous-time linear equalizers | |
| US8964825B2 (en) | Analog signal current integrators with tunable peaking function | |
| US10193515B2 (en) | Continuous time linear equalizer with two adaptive zero frequency locations | |
| US7598811B2 (en) | Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading | |
| US6169764B1 (en) | Analog adaptive line equalizer | |
| US11165456B2 (en) | Methods and apparatus for a continuous time linear equalizer | |
| CN108183696B (en) | Low-voltage high-speed programmable equalization circuit | |
| KR20120053466A (en) | Differential equalizers with source degeneration and feedback circuits | |
| CN103346778A (en) | Broadband linear equalization circuit | |
| CN113422586B (en) | Energy-efficient equalizer architecture | |
| CN113691234A (en) | High-bandwidth continuous time linear equalization circuit | |
| Balachandran et al. | A 0.013-mm 2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS | |
| Li et al. | A 56-Gb/s PAM4 receiver analog front-end with fixed peaking frequency and bandwidth in 40-nm CMOS | |
| CN111756333A (en) | High-low frequency gain-adjustable analog equalizer | |
| CN103379063A (en) | Linear equalizer | |
| Aghighi et al. | A low-power 10 to 15 Gb/s common-gate CTLE based on optimized active inductors | |
| CN111431618B (en) | BiCMOS (Bipolar complementary Metal oxide semiconductor) optical transmitter driving circuit based on PAM4 modulation mode | |
| Chen et al. | A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard | |
| CN116111980A (en) | gm-TIA-based low-power consumption receiver analog front-end equalization circuit | |
| CN116886205B (en) | Self-adaptive equalization system for PAM4 optical receiver | |
| Zhang et al. | A 20Gbps CTLE with active inductor | |
| Zhang et al. | A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS | |
| Hernandez-Garduno et al. | A CMOS 1 Gb/s 5-tap fractionally-spaced equalizer | |
| US20230370038A1 (en) | Low-voltage high-speed programmable equalization circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |