CN116110858A - Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer - Google Patents

Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer Download PDF

Info

Publication number
CN116110858A
CN116110858A CN202211540582.3A CN202211540582A CN116110858A CN 116110858 A CN116110858 A CN 116110858A CN 202211540582 A CN202211540582 A CN 202211540582A CN 116110858 A CN116110858 A CN 116110858A
Authority
CN
China
Prior art keywords
chip
plastic package
ball
package body
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211540582.3A
Other languages
Chinese (zh)
Inventor
李伟
刘卫东
刘志农
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Nanjing Co Ltd
Original Assignee
Huatian Technology Nanjing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Nanjing Co Ltd filed Critical Huatian Technology Nanjing Co Ltd
Priority to CN202211540582.3A priority Critical patent/CN116110858A/en
Publication of CN116110858A publication Critical patent/CN116110858A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

Abstract

The invention discloses a chip superposition packaging structure adopting plastic package as a dielectric layer, which comprises a substrate, a first chip, a first ball, a plastic package body, a second chip, bottom filling glue, heat-dissipating glue, acrylic hot melt glue and a heat-dissipating cover. According to the invention, after the first chip is packaged on the substrate, the second chip is packaged again by taking the plastic package body as the substrate, and the lamination packaging is not required on the wafer structure, so that the packaging difficulty can be reduced, the packaging procedure is locked in a normal flip-chip packaging factory, and the input cost is reduced; the support is added in the heat dissipation cover, and the plastic package body and the heat dissipation cover are supported and pulled, so that the surface of the plastic package body and the surface of the heat dissipation cover are always parallel, the problem of warping in the packaging thermal process is avoided, and the yield of the packaging structure can be improved.

Description

Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer
Technical field:
the invention belongs to the technical field of semiconductor chip packaging, and particularly relates to a chip superposition packaging structure and a packaging method adopting plastic packaging as a dielectric layer.
The background technology is as follows:
the normal flip chip ball grid array (FC-BGA) chip is stacked by a WLCSP (Wafer Level Chip Scale Packaging) wafer level package structure, and the package mode has extremely high requirements and lower package yield; the traditional flip-chip process is not compatible with the packaging process on the wafer, so that the number of manufacturers capable of carrying out WLCSP wafer level packaging substitution is small, and the input cost is also extremely high; it is therefore necessary to develop a new chip stack package structure that can be produced by a flip-chip process; on the other hand, when a plurality of chips are packaged on a substrate by the existing flip-chip technology, warpage can also occur, a cry/smile face structure is presented, PI is adopted as a dielectric layer conventionally, but PI materials are high in price and high in production cost, so that the defects are optimized if a new chip stacking and packaging structure produced by the flip-chip technology is adopted, the yield of packaged products is improved, and meanwhile, the production cost is reduced.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
The invention comprises the following steps:
the invention aims to provide a chip stacking packaging structure and a packaging method adopting plastic packaging as a dielectric layer, thereby overcoming the defects in the prior art.
In order to achieve the above object, the present invention provides a chip stacking package structure using plastic package as a dielectric layer, including:
a substrate;
the first chip is positioned on the substrate and is electrically connected with the substrate;
the first implant ball is positioned on the substrate and is electrically connected with the substrate;
the plastic package body is positioned on the substrate and is used for plastic packaging the first chip and the first ball implant inside, wherein the top of the first ball implant is exposed out of the plastic package body;
the second chip is positioned on the first ball implant;
the underfill is positioned on the plastic package body and surrounds the side surface of the second chip and the underfill;
the heat dissipation glue is positioned on the second chip;
the acrylic acid hot melt adhesive is positioned on the plastic package body;
and the heat dissipation cover is positioned on the acrylic hot melt adhesive to cover the heat dissipation adhesive.
Further, preferably, at least one of the second chips is provided.
Further, preferably, a support is further added in the heat dissipation cover, and an acrylic acid hot melt adhesive is also arranged at a position on the plastic package body corresponding to the support, wherein the acrylic acid hot melt adhesive is used for adhering the support to the plastic package body.
Further, preferably, a metal pad is penetrated in the substrate, a second ball is implanted at the bottom, and the metal pad is communicated with the first ball implantation and the second ball implantation.
Further, preferably, a third ball is implanted at the bottom of the first chip, and the third ball is also conducted with the metal pad.
Further, preferably, a fourth implant ball is implanted at the bottom of the second chip, a nickel metal layer is plated on a portion of the first implant ball exposed out of the plastic package body, and the fourth implant ball is located on the nickel metal layer.
A packaging method of a chip superposition packaging structure adopting plastic package as a dielectric layer comprises the following steps:
the first step: planting a third planting ball at the bottom of the first chip;
and a second step of: planting a first planting ball above the substrate, and simultaneously carrying out plastic package on the first chip and the first planting ball by using a plastic package body;
and a third step of: thinning the plastic package body, grinding out the first implant balls, but not exposing the first chip, and polishing the surface of the plastic package body to be smooth;
fourth step: plating nickel metal layer on the surface of the first ball-planting surface;
fifth step: planting a fourth planting ball at the bottom of the second chip;
sixth step: packaging the second chip on the plastic package body by using underfill, wherein the underfill fills the bottom gap and the side surface of the second chip;
seventh step: ion cleaning is carried out on the surface of the plastic package body, acrylic acid hot melt adhesive is added on the plastic package body after cleaning is finished, and heat dissipation adhesive is coated on the second chip;
eighth step: the heat dissipation cover is planted on the acrylic acid hot melt adhesive to cover the heat dissipation adhesive, a support is arranged in the heat dissipation cover, the acrylic acid hot melt adhesive is also arranged at the position corresponding to the support on the plastic package body, and the acrylic acid hot melt adhesive is used for adhering the support to the plastic package body;
ninth step: and implanting a second implant ball at the bottom of the substrate to obtain the final package.
Further, preferably, the height of the first ball is greater than the thickness of the first chip in the second step.
Further, preferably, the sixth step of filling the underfill is followed by ion cleaning.
Further, preferably, the substrate is internally penetrated with a metal pad, and the first implant ball and the second implant ball are both positioned on the metal pad.
Compared with the prior art, one aspect of the invention has the following beneficial effects:
(1) According to the invention, after the first chip is packaged on the substrate, the second chip is packaged again by taking the plastic package body as the substrate, and the lamination packaging is not required on the wafer structure, so that the packaging difficulty can be reduced, the packaging procedure is locked in a normal flip-chip packaging factory, and the input cost is reduced;
(2) Compared with the conventional method which uses PI as the dielectric layer, the plastic package body is used as the dielectric layer, so that the material cost is lower, and the production cost can be reduced;
(3) The support is added in the heat dissipation cover, and the plastic package body and the heat dissipation cover are supported and pulled, so that the surface of the plastic package body and the surface of the heat dissipation cover are always parallel, the problem of warping in the packaging thermal process is avoided, and the yield of the packaging structure can be improved.
Description of the drawings:
FIG. 1 is a schematic structural view of embodiment 1 of the present invention;
FIG. 2 is a flow chart of a packaging method according to embodiment 1 of the present invention;
FIG. 3 is a schematic structural view of embodiment 2 of the present invention;
FIG. 4 is a top view showing a part of the structure of embodiment 2 of the present invention;
reference numerals: 1-base plate, 2-first chip, 3-first ball of planting, 4-plastic envelope, 5-second chip, 6-underfill, 7-heat-dissipating glue, 8-acrylic acid hot melt adhesive, 9-heat-dissipating cover, 10-support, 11-metal bonding pad, 12-second ball of planting, 13-third ball of planting, 14-fourth ball of planting, 15-nickel metal layer.
The specific embodiment is as follows:
the following detailed description of specific embodiments of the invention is, but it should be understood that the invention is not limited to specific embodiments.
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
Example 1:
as shown in fig. 1, a chip stacking package structure using plastic package as a dielectric layer includes:
the substrate 1, the metal pad 11 is penetrated in the substrate 1, the second implant ball 12 is implanted at the bottom, and the second implant ball 12 is communicated with the metal pad 11;
the first chip 2 is positioned on the substrate 1, a third implant ball 13 is implanted at the bottom of the first chip 2, and the third implant ball 13 is communicated with the metal bonding pad 11;
the first ball implantation device comprises a first ball implantation device 3, wherein the first ball implantation device 3 is positioned on a substrate 1 and is communicated with a metal bonding pad 11;
the plastic package body 4 is positioned on the substrate 1 and is used for plastic packaging the first chip 2 and the first planting ball 3 inside, wherein the plastic package body 4 is exposed out of the top of the first planting ball 3, and the plastic package body 4 is made of a common insulating epoxy material;
the second chip 5, a fourth implanting ball 14 is implanted at the bottom of the second chip 5, a nickel metal layer 15 is plated on the part of the first implanting ball 3 exposed out of the plastic package body 4, the fourth implanting ball 14 is positioned on the nickel metal layer 15, two second chips 5 are symmetrically positioned at two sides of the first chip 2;
an underfill 6, wherein the underfill 6 is positioned on the plastic package body 4 and surrounds the side surface and the bottom of the second chip 5;
the heat dissipation glue 7 is positioned on the second chip 5;
the acrylic acid hot melt adhesive 8 is positioned on the plastic package body 4;
and the heat dissipation cover 9 is positioned on the acrylic hot melt adhesive 8 to cover the heat dissipation adhesive 7.
As shown in fig. 2, a packaging method of a chip stacking packaging structure using plastic package as a dielectric layer includes the following steps:
the first step: a third implanting ball 13 is implanted at the bottom of the first chip 2;
and a second step of: a first ball-planting device 3 is planted above the substrate 1, and the first chip 2 and the first ball-planting device 3 are subjected to plastic package by a plastic package body 4, wherein the height of the first ball-planting device is larger than the thickness of the first chip, the height of the first ball-planting device is larger than 150 mu m, and the thickness of the first chip is 50-100 mu m;
and a third step of: thinning the plastic package body 4, grinding the first implant ball 3, but not exposing the first chip 2, and polishing the surface of the plastic package body 4 to be smooth;
fourth step: the surface of the first ball 3 is plated with a nickel metal layer 15, which is used for preventing the first ball 3 from oxidizing and preventing the first ball 3 from melting back when the chip is packaged for the second time, thus causing the problem of circuit disconnection;
fifth step: a fourth implanting ball 14 is implanted at the bottom of the second chip 5;
sixth step: packaging the second chip 5 on the plastic package body 4 by using the underfill 6, filling the underfill 6 into the bottom gap and the side surface of the second chip 5, and performing ion cleaning after filling the underfill;
seventh step: ion cleaning is carried out on the surface of the plastic package body 4, after the cleaning is finished, an acrylic acid hot melt adhesive 8 is added on the plastic package body 4, and a heat dissipation adhesive 7 is coated on the second chip 5;
eighth step: a heat dissipation cover 9 is planted on the acrylic hot melt adhesive 8 to cover the heat dissipation adhesive 7;
ninth step: and implanting second implanting balls 12 at the bottom of the substrate 1 to obtain a final package.
Example 2:
in example 1, as shown in fig. 3 and 4, preferably, a support 10 is further added in the heat dissipating cover 9, and an acrylic hot melt adhesive 8 is also disposed on the plastic package 4 at a position corresponding to the support 10, wherein the acrylic hot melt adhesive 8 is used for adhering the support 10 to the plastic package 4. The surface of the plastic package body 4 and the surface of the heat dissipation cover 9 can be always kept parallel, the problem of warping in the packaging heat process is avoided, and the yield of the packaging structure can be improved.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A chip superposition packaging structure adopting plastic package as a dielectric layer is characterized by comprising:
a substrate;
the first chip is positioned on the substrate and is electrically connected with the substrate;
the first implant ball is positioned on the substrate and is electrically connected with the substrate;
the plastic package body is positioned on the substrate and is used for plastic packaging the first chip and the first ball implant inside, wherein the top of the first ball implant is exposed out of the plastic package body;
the second chip is positioned on the first ball implant;
the underfill is positioned on the plastic package body and surrounds the side surface of the second chip and the underfill;
the heat dissipation glue is positioned on the second chip;
the acrylic acid hot melt adhesive is positioned on the plastic package body;
and the heat dissipation cover is positioned on the acrylic hot melt adhesive to cover the heat dissipation adhesive.
2. The chip attach package structure of claim 1 wherein at least one of said second chips is a plastic package.
3. The chip stacking and packaging structure adopting plastic package as a dielectric layer according to claim 2, wherein a support is further added in the heat dissipation cover, and an acrylic hot melt adhesive is also arranged at a position on the plastic package body corresponding to the support, and the acrylic hot melt adhesive is used for adhering the support to the plastic package body.
4. The chip stacking and packaging structure adopting plastic package as a dielectric layer according to claim 1, wherein the metal bonding pad penetrates through the substrate, the second ball is implanted at the bottom, and the metal bonding pad is communicated with the first ball implantation and the second ball implantation.
5. The chip stacking and packaging structure adopting plastic package as dielectric layer according to claim 4, wherein a third ball is implanted at the bottom of the first chip, and the third ball is also connected with the metal bonding pad.
6. The chip stacking and packaging structure adopting plastic package as a dielectric layer according to claim 1, wherein a fourth implant ball is implanted at the bottom of the second chip, a nickel metal layer is plated on a part of the first implant ball exposed out of the plastic package body, and the fourth implant ball is positioned on the nickel metal layer.
7. The packaging method of the chip superposition packaging structure adopting plastic package as a dielectric layer is characterized by comprising the following steps of:
the first step: planting a third planting ball at the bottom of the first chip;
and a second step of: planting a first planting ball above the substrate, and simultaneously carrying out plastic package on the first chip and the first planting ball by using a plastic package body;
and a third step of: thinning the plastic package body, grinding out the first implant balls, but not exposing the first chip, and polishing the surface of the plastic package body to be smooth;
fourth step: plating nickel metal layer on the surface of the first ball-planting surface;
fifth step: planting a fourth planting ball at the bottom of the second chip;
sixth step: packaging the second chip on the plastic package body by using underfill, wherein the underfill fills the bottom gap and the side surface of the second chip;
seventh step: ion cleaning is carried out on the surface of the plastic package body, acrylic acid hot melt adhesive is added on the plastic package body after cleaning is finished, and heat dissipation adhesive is coated on the second chip;
eighth step: the heat dissipation cover is planted on the acrylic acid hot melt adhesive to cover the heat dissipation adhesive, a support is arranged in the heat dissipation cover, the acrylic acid hot melt adhesive is also arranged at the position corresponding to the support on the plastic package body, and the acrylic acid hot melt adhesive is used for adhering the support to the plastic package body;
ninth step: and implanting a second implant ball at the bottom of the substrate to obtain the final package.
8. The method of claim 7, wherein the height of the first ball is greater than the thickness of the first chip in the second step.
9. The method of claim 7, wherein the sixth step of filling the underfill is followed by ion cleaning.
10. The method of claim 7, wherein the metal bonding pads penetrate through the substrate, and the first and second balls are located on the metal bonding pads.
CN202211540582.3A 2022-12-01 2022-12-01 Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer Pending CN116110858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211540582.3A CN116110858A (en) 2022-12-01 2022-12-01 Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211540582.3A CN116110858A (en) 2022-12-01 2022-12-01 Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer

Publications (1)

Publication Number Publication Date
CN116110858A true CN116110858A (en) 2023-05-12

Family

ID=86253466

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211540582.3A Pending CN116110858A (en) 2022-12-01 2022-12-01 Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer

Country Status (1)

Country Link
CN (1) CN116110858A (en)

Similar Documents

Publication Publication Date Title
US7936060B2 (en) Reworkable electronic device assembly and method
TWI533412B (en) Semiconductor device package structure and forming method of the same
US7989959B1 (en) Method of forming stacked-die integrated circuit
US9806038B2 (en) Reinforcement structure and method for controlling warpage of chip mounted on substrate
TW200832644A (en) Water level package with good CTE performance and method of the same
TW200839988A (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
TW201023277A (en) Packaging structural member
TWI249796B (en) Semiconductor device having flip chip package
JP2013080912A (en) Semiconductor device and manufacturing method of the same
CN101221936A (en) Wafer level package with die receiving through-hole and method of the same
TW200931628A (en) Stacking die package structure for semiconductor devices and method of the same
TW201338126A (en) Chip stack structure and method of fabricating the same
CN103681374A (en) Method for manufacturing package
CN102034768A (en) Embedded-dice-inside type substrate structure with redistribution layer covered on both side and method thereof
CN111785646B (en) Ultra-thin welding stack packaging mode
TW200411891A (en) High density multi-chip module structure and manufacturing method thereof
JP2012164951A (en) Device and method for peeling semiconductor chip
WO2023097896A1 (en) Packaging structure for chip and packaging method
JP2012209449A (en) Method of manufacturing semiconductor device
KR20080114603A (en) Semiconductor device package having pseudo chips
TW200849503A (en) Package-on-package structure and method for making the same
CN110246812A (en) A kind of semiconductor package and preparation method thereof
TW200807682A (en) Semiconductor package and method for manufacturing the same
CN107919333B (en) Three-dimensional POP packaging structure and packaging method thereof
CN116110858A (en) Chip superposition packaging structure and packaging method adopting plastic package as dielectric layer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination