CN116110450A - Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor - Google Patents

Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor Download PDF

Info

Publication number
CN116110450A
CN116110450A CN202310129169.6A CN202310129169A CN116110450A CN 116110450 A CN116110450 A CN 116110450A CN 202310129169 A CN202310129169 A CN 202310129169A CN 116110450 A CN116110450 A CN 116110450A
Authority
CN
China
Prior art keywords
search
pulse width
fefet
vdd
matching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310129169.6A
Other languages
Chinese (zh)
Inventor
黄如
徐伟凯
黄芊芊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University
Original Assignee
Peking University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University filed Critical Peking University
Priority to CN202310129169.6A priority Critical patent/CN116110450A/en
Publication of CN116110450A publication Critical patent/CN116110450A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a method for realizing an analog and multi-value content addressable memory based on a pulse width modulation ferroelectric field effect transistor, belonging to the technical field of novel storage and calculation. Compared with the traditional implementation modes of ACAM and MCAM, the invention does not need additional transistors and complex analog peripheral circuits, can be realized by only sharing a few logic gates, has a simpler implementation mode and lower hardware cost, only needs one voltage amplitude VDD in the search process, and is more compatible with a digital system. In addition, the encoding mode of the search query and the memory entry based on pulse width ensures that the memory range is not limited by the memory window of the FeFET, and MCAM with more bits can be obtained, so that the memory density and the search energy efficiency of the CAM are further improved, and the method has wide application prospect.

Description

Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor
Technical Field
The invention relates to the technical field of novel storage and calculation, in particular to an analog and multi-value content addressable memory design based on a pulse width modulation ferroelectric field effect transistor.
Background
Content Addressable Memory (CAM) performs search operations efficiently and in parallel, and is widely used in efficient machine learning models such as routers, database searches, in-memory computing, and neuromorphic computing. CAM is a special type of memory for parallel searching that can perform unique search operations in addition to read and write operations with conventional memory. The CAM is initially used for accelerating the relevant table lookup operations such as data packet forwarding and classification in a network router, and because the CAM can complete the whole search operation within one clock period, compared with other search systems based on hardware or software, the CAM has a remarkable accelerating effect, a Ternary Content Addressable Memory (TCAM) with the capability of storing a mask 'X' state is further developed on the basis of the CAM, and the TCAM can realize accurate matching or fuzzy matching and improve table lookup efficiency. In the big data age, the CAM can complete the matching operation of an input vector (query) and all storage vectors (entry) in one search period, and perform feature retrieval based on distance measurement according to the degree of mismatching, so that the CAM has great attraction in processing of edge-end machine learning tasks such as pattern matching, video and image processing and the like.
CAM designs based on conventional Static Random Access Memories (SRAM) occupy a large cell area, limit their storage density for computationally intensive algorithm mapping, and the resulting large parasitic capacitance further increases search latency and power consumption. Based on various emerging nonvolatile memories, such as Resistive Random Access Memory (RRAM), phase Change Memory (PCM), and ferroelectric field effect transistor (FeFET), etc., CAMs are designed with reduced cell area and search delay and power consumption. In addition, the Analog Content Addressable Memory (ACAM) further designed by utilizing the multi-value capacity of the emerging nonvolatile memory not only can improve the storage density of the CAM by being quantized into the multi-value content addressable memory (MCAM), but also can be used for more extensive application scenes such as decision trees, deep random forests and the like based on the unique range matching operation. However, the current ACAM and MCAM designs based on the emerging nonvolatile memory are required to be realized through additional hardware overhead, namely, through additional control transistors or additional peripheral complex circuits, to realize matching operation between analog input and memory range, and the corresponding programming and searching modes are also more complex. In combination with the analysis, the ACAM and MCAM design which is more compact and simple to operate is realized, and has very remarkable significance.
Disclosure of Invention
Compared with the existing ACAM and MCAM designs, the invention does not need an additional control transistor and a complex peripheral circuit, and the matching range of the ACAM based on the pulse width modulation FeFET is not limited by a FeFET storage window because of the encoding mode of the search query and the storage entry based on the pulse width, can be quantized into MCAM with more bits, improves the storage density and the search energy efficiency of the CAM, only needs one voltage amplitude in the search process, and is more compatible with a digital system.
The technical scheme of the invention is as follows:
a method for realizing an analog content addressable memory ACAM based on pulse width modulation FeFET is characterized by comprising a CAM array formed by CAM cells, each CAM cell is formed by two N-type FeFETs, and the drain electrode of the FeFET is connected with two matching lines ML and ML b The grid of the FeFET is connected with two search lines SL and SL b The source of the FeFET is grounded, and in the CAM array, a row of CAM cells shares two match lines ML and ML b ML and ML b As two inputs of an and gate shared by the rows, the output of the and gate is the matching result Vout of the row; one column of CAM cells shares two search lines SL and SL b The search signal SL and the reference signal Ref of each column are taken as two inputs of an exclusive OR gate shared by the columns, and the output of the exclusive OR gate is SL b The method comprises the steps of carrying out a first treatment on the surface of the The precharge circuit is used for charging the two match lines of each row; in the programming of ACAM memory, a certain programming voltage is applied to the gates of two FeFETs, respectively, and the FEFETs are programmed to a certain threshold voltage V TH1 And V TH2 When the voltage VDD is applied to the gates of the two FeFETs, ML is precharged to VDD by a precharge circuit 1 And ML (ML) 2 Exhibits a discharge rate related to the FeFET threshold voltage, and discharges to VDD/2 for a time t, respectively 1 And t 2 In the searching stage, ML is first performed by a pre-charge circuit 1 And ML (ML) 2 Pre-charge to VDD, SL side application with certainPulse width T SL And the search voltage V with the amplitude of VDD SL ，T SL Corresponding to the size of the search query, the reference signal Ref has a width T Ref The signal at SLb end is pulse width T Ref -T SL And the search voltage V with the amplitude of VDD SLb When V SL Pulse width T of (2) SL Less than the discharge time t of the FeFET it acts on 1 And V is SLb Pulse width T of (2) Ref -T SL Less than the discharge time t of the FeFET it acts on 2 During the search, ML 1 And ML (ML) 2 The voltage of (2) is not discharged below VDD/2, and the output Vout of AND gate remains high, indicating a match, so that a match range of T can be obtained SL At T Ref -t 2 To t 1 By programming the two FeFETs separately, different discharge times t can be obtained 1 And t 2 And further different matching ranges are obtained. If V is SL Is larger, will cause T SL Greater than t 1 So that V SL ML of acting FeFET 1 Falls below VDD/2 during the search phase, if V SL Is smaller, will cause T SL Less than T Ref -t 2 Will lead to V SLb ML of acting FeFET 2 In the search phase, the output result Vout is changed to be low level in the search phase under the condition of VDD/2, which indicates no match, and the range matching operation of ACAM units is realized.
Further, by programming CAM cells in the array into a plurality of non-overlapping pulse width matching ranges, i.e., the analog CAM can be quantized into the multi-valued CAM MCAM, the plurality of discrete pulse width matching ranges represent the multi-stage entry states of the MCAM, and the pulse width of the quantized multi-stage search query corresponding to the entry can take the intermediate value of the storage range, then during the search operation, V of the corresponding pulse width is applied according to the search query SL V only when the multilevel search query is consistent with the multilevel storage entry SL Is within a matching range such that V SL And V SLb Each acting onThe time on the FeFETs is less than the discharge time of the corresponding FeFET, so that ML during search 1 And ML (ML) 2 Are all greater than VDD/2 so that the output Vout is high indicating a match. Otherwise, when the multi-level search query is inconsistent with the multi-level storage entry, V will be caused SL Is outside the matching range, such that ML 1 Or ML (ML) 2 The search stage drops below VDD/2 so that the output Vout goes low, indicating a mismatch, and an MCAM match operation is implemented.
Pulse width T of reference signal Ref Ref The FeFET can be adjusted according to the discharge time of the FeFET after programming, and can be programmed to be in a low threshold state and a high threshold state, so that the FeFET is in a complete on state and an off state respectively when the grid electrode inputs the VDD voltage, and the corresponding discharge time is very short time and near infinite time, therefore, the storage range of the ACAM based on the FeFET with pulse width modulation can be changed from a very small pulse width range to a theoretically infinite pulse width range by modulating the threshold voltage of the FeFET and selecting proper Ref, and the quantifiable state number can be further improved if the FeFET is used for MCAM.
In summary, the ACAM and MCAM designs based on the FeFET with pulse width complementary information are realized, and compared with the conventional ACAM implementation, only one voltage amplitude VDD is needed in the search process, which is compatible with the digital system.
The invention provides ACAM and MCAM designs based on pulse width modulation FeFET, wherein ferroelectric materials need to adopt HfO 2 Zr (HZO) and HfO doped 2 Al (HfAlO) doped with various HfO 2 The doped multi-domain ferroelectric material, the device gate stack can be based on a variety of structures such as MFMIS, MFIS, MFS.
The invention has the following technical effects:
1. compared with the traditional ACAM implementation mode, the ACAM design based on the pulse width modulation FeFET is realized by utilizing the complementary information of the pulse width, does not need additional transistors and complex analog peripheral circuits in a unit, can be realized by only needing a plurality of logic gates which can be shared, has a more concise implementation mode and lower hardware cost, and is more compatible with a digital system because only one voltage amplitude VDD is needed in the search process.
2. The MCAM design based on the pulse width modulation FeFET provided by the invention is based on the coding mode of the search query and the memory entry of the pulse width, so that the memory range is not limited by the memory window of the FeFET, and the MCAM with more bits can be obtained, thereby further improving the memory density and the search energy efficiency of the CAM.
Drawings
FIG. 1 is a schematic diagram of a CAM cell according to the present invention based on a pulse width modulation FeFET;
FIG. 2 is a schematic diagram of an ACAM function implementation of the present invention based on a pulse width modulated FeFET; in the figure: a) I for two FeFETs per CAM cell D -V G A characteristic diagram; b) Schematic of the discharge characteristics of the two fefets per CAM cell; c) A search signal waveform schematic for each CAM cell; d) Schematic of the output results for each CAM cell;
fig. 3 is a schematic diagram of the MCAM function implementation of the present invention based on a pulse width modulated FeFET.
Detailed Description
The present invention will be further clarified and fully explained by the following detailed description of embodiments, which are to be taken in connection with the accompanying drawings.
The CAM array structure based on pulse width modulation FeFET of the present invention is shown in FIG. 1, and the CAM cell is formed by two N-type FeFETs (F 1 And F 2 ) Two-input exclusive-OR gate shared by rows, two-input AND gate shared by columns and precharge circuit, F 1 And F 2 The grid electrode of the (B) is respectively connected with two search lines SL and SLb, SL and a reference signal Ref are used as two input of an exclusive OR gate, and the output of the exclusive OR gate is SLb, F 1 And F 2 Is connected with two matching lines ML 1 And ML (ML) 2 ，ML 1 And ML (ML) 2 Two as AND gatesThe output of AND gate is the matching result Vout of the row, and during search operation, two matching lines ML are first passed through the precharge circuit 1 And ML (ML) 2 Charging to VDD and then applying a search voltage, if Vout remains high during the search, indicating a match, otherwise indicating a mismatch.
FIG. 2 is a schematic diagram of the implementation of the function of the FeFET based on pulse width modulation in the present embodiment, at the stage of programming the ACAM memory entry, for F respectively 1 And F 2 A programming voltage greater than the coercive voltage is applied to the gate of (C), and its threshold voltage is programmed to V TH1 And V TH2 When at F 1 And F 2 Is applied with a voltage VDD, ML precharged to VDD by a precharge circuit 1 And ML (ML) 2 Exhibit a relationship with F 1 And F 2 The discharge speed related to the threshold voltage is respectively t when the discharge time reaches VDD/2 1 And t 2 The method comprises the steps of carrying out a first treatment on the surface of the In the searching stage, ML is first performed by a pre-charge circuit 1 And ML (ML) 2 Precharging to VDD, applying pulse width T corresponding to search query to SL terminal SL Search voltage V of (2) SL The reference signal Ref has a width T Ref The signal at SLb end is pulse width T SLb Is T Ref -T SL Only when V SL Pulse width T of (2) SL Less than F 1 Is set to be a discharge time t of 1 And V is SLb Pulse width T of (2) SLb Less than F 2 Is set to be a discharge time t of 2 Can ensure ML in the searching process 1 And ML (ML) 2 The voltage of (2) will not discharge below VDD/2 and the output of AND gate Vout will remain high, indicating a match, i.e., the match range is T SL At T Ref -t 2 To t 1 Between them. If V is SL Is larger, will cause T SL Greater than t 1 So that ML 1 By F in the search phase 1 The discharge drops below VDD/2 if V SL Is smaller, will cause T SL Less than T Ref -t 2 Would make ML 2 By F in the search phase 2 The discharge drops below VDD/2 causing the output Vout to go low during the search phase, indicating a mismatch.
As shown in fig. 3, the CAM cells in the array may be quantized into MCAM by programming the CAM cells into a plurality of non-overlapping pulse width matching ranges, where the plurality of discrete pulse width matching ranges represent the multi-stage entry states of the MCAM, and the pulse width of the quantized multi-stage search query corresponding to the entry may take the intermediate value of the pulse width matching ranges to obtain a larger detection margin and robustness. During search operation, V with corresponding pulse width is applied according to search query SL When the multi-level search query is consistent with the multi-level storage entry, V SL Is within a matching range such that V SL And V SLb The respective time of action on the FeFETs is less than the discharge time of the corresponding FeFET, ML during search 1 And ML (ML) 2 Are all larger than VDD/2, and the output result Vout is high level and indicates matching; otherwise, when the multi-level search query is inconsistent with the multi-level storage entry, V SL Is outside the matching range, ML 1 Or ML (ML) 2 The output result Vout goes low, indicating a mismatch, when the search phase falls below VDD/2.
The implementation manner of the ACAM and the MCAM based on the pulse width modulation FeFET is fully and specifically described in this embodiment, and the ACAM function is implemented by using the complementary information of the pulse width, compared with the conventional implementation manner of the ACAM, no additional transistor and complicated analog peripheral circuit are needed in the unit, and the encoding manner of the search query and the memory entry based on the pulse width can be quantized into the MCAM with more bits, so as to improve the storage density and the search energy efficiency of the CAM.
Finally, it should be noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.

Claims (4)

1. Realizing analog content addressable memoryA method for storing ACAM is characterized by comprising a CAM array composed of CAM cells, each CAM cell is composed of two N-type FeFETs, and the drain electrode of each FeFET is connected with two matching lines ML and ML b The grid of the FeFET is connected with two search lines SL and SL b The source of the FeFET is grounded, and in the CAM array, a row of CAM cells shares two match lines ML and ML b ML and ML b As two inputs of an and gate shared by the rows, the output of the and gate is the matching result Vout of the row; one column of CAM cells shares two search lines SL and SL b The search signal SL and the reference signal Ref of each column are taken as two inputs of an exclusive OR gate shared by the columns, and the output of the exclusive OR gate is SL b The method comprises the steps of carrying out a first treatment on the surface of the The precharge circuit is used for charging the two match lines of each row; in the programming of ACAM memory entry, a certain programming voltage is applied to the gates of two FeFETs of a CAM cell, and the two FEFETs are programmed to a certain threshold voltage V TH1 And V TH2 When the voltage VDD is applied to the gates of the two FeFETs, ML is precharged to VDD by a precharge circuit 1 And ML (ML) 2 Exhibits a discharge rate related to the FeFET threshold voltage, and discharges to VDD/2 for a time t, respectively 1 And t 2 In the searching stage, ML is first performed by a pre-charge circuit 1 And ML (ML) 2 Pre-charge to VDD, SL end application with a certain pulse width T SL And the search voltage V with the amplitude of VDD SL ，T SL Corresponding to the size of the search query, the reference signal Ref has a width T Ref The signal at SLb end is pulse width T Ref -T SL And the search voltage V with the amplitude of VDD SLb When V SL Pulse width T of (2) SL Less than the discharge time t of the FeFET it acts on 1 And V is SLb Pulse width T of (2) Ref -T SL Less than the discharge time t of the FeFET it acts on 2 During the search, ML 1 And ML (ML) 2 The voltage of (2) will not discharge below VDD/2 and the output of AND gate Vout will remain high, indicating a match, resulting in a match range of T SL At T Ref -t 2 To t 1 Between them; if V is SL Is large in pulse width, T SL Greater than t 1 So that V SL ML of acting FeFET 1 Falling below VDD/2 during the search phase, or if V SL Is small in pulse width, T SL Less than T Ref -t 2 ，V SLb ML of acting FeFET 2 When the search stage falls below VDD/2, the output result Vout becomes low level in the search stage, which indicates no match, and ACAM matching operation is realized.
2. A method for realizing multi-value content addressable memory (ACAM) is characterized in that the ACAM as claimed in claim 1 is adopted to program CAM cells in an array into a plurality of non-overlapping pulse width matching ranges, the plurality of discrete pulse width matching ranges represent multi-stage entry states of MCAM, and V with corresponding pulse width is applied according to search query during search operation SL When the multi-level search query is consistent with the multi-level storage entry, V SL Is within a matching range such that V SL And V SLb The respective time of action on the FeFETs is less than the discharge time of the corresponding FeFET, ML during search 1 And ML (ML) 2 Are all larger than VDD/2, and the output result Vout is high level and indicates matching; otherwise, when the multi-level search query is inconsistent with the multi-level storage entry, V SL Is outside the matching range, ML 1 Or ML (ML) 2 In the search stage, the output result Vout goes low, indicating a mismatch, and the MCAM matching operation is implemented.
3. The method of claim 1 or 2, wherein the FeFET is a MFMIS, MFIS, MFS-based device.
4. The method of claim 3, wherein the ferroelectric material of the FeFET is HfO 2 Zr-doped or HfO-doped 2 Al is doped.
CN202310129169.6A 2023-02-08 2023-02-08 Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor Pending CN116110450A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310129169.6A CN116110450A (en) 2023-02-08 2023-02-08 Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310129169.6A CN116110450A (en) 2023-02-08 2023-02-08 Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor

Publications (1)

Publication Number Publication Date
CN116110450A true CN116110450A (en) 2023-05-12

Family

ID=86254072

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310129169.6A Pending CN116110450A (en) 2023-02-08 2023-02-08 Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor

Country Status (1)

Country Link
CN (1) CN116110450A (en)

Similar Documents

Publication Publication Date Title
US11322195B2 (en) Compute in memory system
KR100258837B1 (en) Nonvolatile content addressable memory
US10461751B2 (en) FE-FET-based XNOR cell usable in neuromorphic computing
Hu et al. In-memory computing with associative memories: A cross-layer perspective
CN111126579B (en) In-memory computing device suitable for binary convolutional neural network computation
CN113593623B (en) Analog content addressable memory using three-terminal memory device
CN110751279B (en) Ferroelectric capacitance coupling neural network circuit structure and multiplication method of vector and matrix in neural network
CN113936717B (en) Storage and calculation integrated circuit for multiplexing weight
CN114758695B (en) Method for realizing multi-value content addressable memory MCAM based on ferroelectric tunneling field effect transistor FeTFET
CN115472194A (en) Method for realizing content addressable memory based on field effect transistor with bipolar characteristic
Yang et al. An ultra-high-density and energy-efficient content addressable memory design based on 3D-NAND flash
US11587623B2 (en) Content-addressable memory and operation method thereof
US20240005977A1 (en) Compute-in-memory devices, neural network accelerators, and electronic devices
CN117350344A (en) Neural network circuit structure, memory module, component, system and operation method
CN116110450A (en) Method for realizing analog and multi-value content addressable memory based on pulse width modulation ferroelectric field effect transistor
CN114743578B (en) Method for realizing ternary content addressable memory TCAM based on ferroelectric tunneling field effect transistor FeTFET
CN110245749B (en) Computing unit, neural network and method for performing exclusive nor operation
CN114898792A (en) Multi-bit memory inner product and exclusive-or unit, exclusive-or vector and operation method
Tseng et al. An Analog In-Memory-Search Solution based on 3D-NAND Flash Memory for Brain-Inspired Computing
Sheikholeslami et al. A multiple-valued ferroelectric content-addressable memory
Tseng et al. A Hybrid In-Memory-Searching and In-Memory-Computing Architecture for NVM Based AI Accelerator
CN221327082U (en) Accumulation operation system
Song et al. Improve the Linearity of NOR Flash Memory Used for Vector Matrix Multiplication
US11875850B2 (en) Content addressable memory device, content addressable memory cell and method for data searching with a range or single-bit data
US20230027768A1 (en) Neural network computing device and computing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination