CN116107639A - Register renaming and instruction decoding method and device, processor and electronic equipment - Google Patents
Register renaming and instruction decoding method and device, processor and electronic equipment Download PDFInfo
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- CN116107639A CN116107639A CN202211574058.8A CN202211574058A CN116107639A CN 116107639 A CN116107639 A CN 116107639A CN 202211574058 A CN202211574058 A CN 202211574058A CN 116107639 A CN116107639 A CN 116107639A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application provides a register renaming and instruction decoding method, a processor, a chip and electronic equipment, wherein the register renaming method comprises the following steps: acquiring a first micro-operation and a second micro-operation, wherein the first micro-operation depends on the second micro-operation, a target logic register and a source logic register of the first micro-operation are respectively a first logic register and a second logic register, and the target logic register of the second micro-operation is the second logic register; if the register renaming table is queried for the second micro-operation and the first physical register mapped by the second logic register is recorded, setting the mapping relation between the first logic register and the first physical register for the first micro-operation in the register renaming table. The register renaming and instruction decoding method, the processor, the chip and the electronic equipment provided by the embodiment of the application can improve the utilization rate of the physical register in the register renaming stage.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a register renaming and instruction decoding method.
Background
The computer performs various tasks by executing instructions in the instruction set, and when executing the instructions, the instructions are decoded into micro-operations (μops), thereby performing the execution of the instructions by executing the micro-operations.
When the computer executes the micro-operation, the calculation result of the micro-operation can be stored in a logic register appointed on the instruction set architecture, and the logic register can be mapped with a physical register in the processor; the mapping of logical registers to physical registers may be implemented in a register renaming stage. Under the above circumstances, how to increase the utilization rate of the physical register in the register renaming stage as a hardware resource actually existing in the processor, thereby improving the performance of the processor, is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In order to achieve the above purpose, the embodiment of the present application provides the following technical solutions:
in a first aspect, an embodiment of the present application provides a register renaming method, including:
acquiring a first micro-operation and a second micro-operation, wherein the first micro-operation depends on the second micro-operation, a destination logic register of the first micro-operation is a first logic register, a source logic register of the first micro-operation is a second logic register, and a destination logic register of the second micro-operation is a second logic register;
Querying a register renaming table for whether a physical register mapped by the second logical register is recorded for the second micro-operation;
and if the register renaming table is queried to record a first physical register mapped by the second logic register aiming at the second micro-operation, setting the mapping relation between the first logic register and the first physical register for the first micro-operation in the register renaming table.
In a second aspect, an embodiment of the present application provides an instruction decoding method, including:
acquiring an instruction;
decoding the instruction to obtain a plurality of micro-operations; the plurality of micro-operations includes a first micro-operation and a second micro-operation;
setting a dependence relationship of a first micro-operation on a second micro-operation, wherein a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is a second logical register, and is used for setting a mapping relationship between the first logical register and the first physical register according to a mapping relationship between the second logical register and the first physical register, which are set for the second micro-operation, in a register renaming table in a register renaming stage.
In a third aspect, an embodiment of the present application further provides an instruction decoding apparatus, including:
an instruction acquisition unit adapted to acquire an instruction;
the decoding unit is suitable for decoding the instruction to obtain a plurality of micro-operations; the plurality of micro-operations includes a first micro-operation and a second micro-operation;
the dependency setting unit is adapted to set a dependency relationship of a first micro-operation depending on a second micro-operation, wherein a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is the second logical register, and is configured to set a mapping relationship between the second logical register set for the second micro-operation and the first physical register in the register renaming table according to the mapping relationship between the second logical register set for the second micro-operation and the first physical register in the register renaming table.
In a fourth aspect, embodiments of the present application provide a processor, including a register renaming unit, and a decoding unit; the register renaming unit is configured to perform the register renaming method as described in the first aspect and the instruction decoding method as described in the second aspect.
In a fifth aspect, embodiments of the present application provide a chip including the processor of the third aspect.
In a sixth aspect, an embodiment of the present application provides an electronic device, including the chip in the fourth aspect.
According to the register renaming method provided by the embodiment of the application, the first micro-operation and the second micro-operation can be acquired in a register renaming stage, wherein the first micro-operation depends on the second micro-operation, a source logic register of the first micro-operation is a second logic register, a target logic register is a first logic register, and a target logic register of the second micro-operation is a second logic register; based on the fact that the first micro-operation depends on the second micro-operation, in the case that the destination logical register of the second micro-operation (namely, the second logical register) is mapped with the physical register, the embodiment of the application can multiplex the physical register mapped by the destination logical register of the second micro-operation to the destination logical register of the first micro-operation (namely, the first logical register), so that the effect of multiplexing the physical registers is achieved; based on this, for the obtained first micro-operation and second micro-operation, the embodiment of the present application may query whether a register renaming table records a physical register mapped by the second logical register for the second micro-operation, where the register renaming table records a mapping relationship between the logical register and the physical register for the micro-operation; if the register renaming table is queried to aim at the second micro-operation, the mapping between the second logic register and the first physical register is recorded, and the fact that the second logic register is mapped with the physical register is indicated, and the physical register is the first physical register, so that the embodiment of the application can set the mapping relation between the first logic register and the first physical register in the register renaming table for the first micro-operation, and multiplexing the first physical register to the first logic register of the first micro-operation is realized.
Therefore, according to the register renaming method provided by the embodiment of the application, after the first micro-operation is acquired, the physical register which is mapped is not selected from the released physical registers, but the first physical register which is mapped in the second micro-operation is selected, so that multiplexing of the mapped first physical registers is realized, the number of physical registers which are required to be used is reduced, and the utilization rate of the physical registers is improved; meanwhile, it is worth noting that the application is not limited to selecting the mapping from the physical registers without mapping any more by multiplexing the physical registers, so that special release micro-operation is not required to be set, and the execution time of a micro-operation sequence is reduced; therefore, by multiplexing the physical registers, the execution duration of the micro-operation sequence can be not prolonged, and the number of the mappable physical registers can not be excessively reduced, so that the performance of the processor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1a is a schematic diagram of an instruction execution;
FIG. 1b is an exemplary diagram of a sequence of micro-operations;
FIG. 1c is a schematic diagram of another sequence of micro-operations;
FIG. 2 is a flowchart of a register renaming method according to an embodiment of the disclosure;
FIG. 3 is a flowchart illustrating a register renaming method according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a micro-operation according to an embodiment of the present disclosure;
FIG. 5a is a schematic diagram of a micro-operation sequence processed by the register renaming method according to the embodiments of the present application;
FIG. 5b is a state diagram of a register renaming table according to the register renaming method of the present embodiment;
FIG. 5c is a diagram illustrating another state of a register renaming table according to the register renaming method of the embodiments of the present application;
FIG. 5d is a diagram illustrating another state of a register renaming table according to the register renaming method of the embodiments of the present application;
FIG. 5e is a diagram illustrating another state of a register renaming table according to the register renaming method of the embodiments of the present application;
FIG. 6 is a flowchart illustrating a register renaming method according to an embodiment of the present disclosure; .
FIG. 7 is a flowchart illustrating a register renaming method according to an embodiment of the disclosure;
FIG. 8 is a schematic diagram of a micro-operation sequence of the register renaming method according to the embodiments of the present application;
FIG. 9 is a flow chart of a method for decoding instructions according to an embodiment of the present disclosure;
FIG. 10 is a flowchart of an instruction decoding method according to an embodiment of the present disclosure;
FIG. 11 is a flowchart illustrating a method for decoding an instruction according to an embodiment of the present disclosure;
fig. 12 is a schematic diagram of an instruction decoding apparatus according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the architecture of a computer system, all high-level languages are decoded into machine language and finally converted into instruction sequences, and a CPU controls the computer to process data by executing instructions in the instruction sequences. In the process of executing each instruction in the instruction sequence, the CPU further decodes each instruction into a micro-operation sequence formed by micro-operations (μops), and the execution of the instruction is realized by executing each micro-operation in the micro-operation sequence. FIG. 1a schematically illustrates an instruction execution, as shown in FIG. 1a, in which an instruction sequence is input to a decoding circuit, decoded by the decoding circuit, and then a micro-operation sequence is output.
In one example, FIG. 1b schematically illustrates an example graph of a micro-operation sequence, as shown in FIG. 1b, consisting of two micro-operations μop0 and μop1. In μop0, the opcode ADD indicates that the micro-operation is an ADD operation, temp0, ymm0, and ymm1 are logical registers of the micro-operation μop 0; wherein, the logical register temp0 following the ADD operation code is the destination logical register of the micro-operation μop0, and the remaining logical registers ymm0 and ymm1 are the source logical registers; the source logic register provides source data, and after the source data is operated by the operation code, a result value is stored into the destination logic register. The micro-operation μop0 illustrated in fig. 1b thus represents adding the source data stored in the source logical registers ymm0 and ymm1 and storing the added result data in the destination logical register temp 0. Similarly, the micro operation μop1 represents adding the source data in the source logical registers ymm0 and temp0, and storing the result data in the destination logical register ymm 2.
It should be noted that there may be an execution dependency relationship between the multiple micro-operations, that is, the next micro-operation is executed depending on the result data of the previous micro-operation. For example, when the destination logical register of the previous micro-operation stores correct result data, the next micro-operation can be started to execute; that is, the execution of the next micro-operation is triggered on the premise that the destination logical register of the previous micro-operation stores the correct result data. Taking the example that the micro-operation μop1 depends on the micro-operation μop0, the execution of the micro-operation μop1 is premised on that the correct data is stored in the logic register temp0, and only the execution of the micro-operation μop0 can store the correct result data (i.e. the added value of ymm0 and ymm 1) in the logic register temp0, so that in the micro-operation sequence, the micro-operation μop1 can be executed only after the execution of the micro-operation μop0 is completed, which is called an execution dependency relationship, for example, the micro-operation μop1 depends on the micro-operation μop0.
With continued reference to FIG. 1a, after the decode circuitry converts each instruction of the instruction sequence into a sequence of micro-operations, the instruction sequence is converted into a sequence of micro-operation programs. The micro-operation program sequence input register renaming and controlling circuit performs renaming of a logic register and control of micro-operation, and it is easy to understand that only the logic register is used in the micro-operation, and renaming of the logic register is mapping of the logic register and the physical register, so that access to data can be physically realized. With continued reference to FIG. 1b, upon register renaming of the micro-op 0, the destination logical register temp0 and a specific physical register (assumed to be physical register A) are mapped; for example, in a previous micro-operation that has preceded micro-operation μop0 by source logical registers ymm0 and ymm1, the destination logical register that is the previous micro-operation is mapped with the corresponding physical register; thus the micro-operation μop0 is actually the fetching of data from the physical register mapped by the source logical register ymm0 and the physical register mapped by the source logical register ymm1, after which the fetching of data is added (e.g. input to an adder) the result is input to the physical register mapped by the destination logical register temp 0. Similarly, when register renaming is performed on the micro-op 1, the physical registers are mapped for the destination logical register ymm 2.
After the execution of the micro-operation μop0 is completed, the control circuit is informed that the physical register a is ready, so that the control circuit can learn that the source logic register mapped with the physical register a is ready, and when all the source logic registers of a micro-operation are ready, the micro-operation can be sent to the operation circuit to implement the execution of the micro-operation, specifically, taking fig. 1b as an example, the complete process of the control circuit can be expressed as: all (two) source logic registers of the micro-operation μop0 are ready, while the active logic register (temp 0) in the micro-operation μop1 is not ready, so that the micro-operation μop0 is sent to the operation circuit to operate on the data in the micro-operation μop0, thereby executing the micro-operation μop0, and when the micro-operation μop0 is executed, the logic register temp0 of the micro-operation μop1 is also ready, so that all the source registers of the micro-operation μop1 are ready, and the control circuit sends the micro-operation μop1 to the operation circuit to execute.
With continued reference to fig. 1a, the operation circuit performs the operation of the micro-operation, the physical register file is formed by the physical registers mapped with the logical registers, the operation circuit fetches data from the physical registers of the physical register file to perform the operation, stores the operation result into the physical registers, completes the execution of the micro-operation, and finally realizes the execution of the sequence of the micro-operation program.
From the foregoing, it is known that only if a logical register in a micro-operation is provided with a mapped physical register, a subsequent flow can be performed and the execution of the micro-operation is finally completed, but since the physical register is usually limited, and a micro-operation program sequence usually contains a large number of logical registers, the mapping between the logical register and the physical register needs to be continuously updated, and the mapping between the logical register and the physical register is released, so that the physical register is released, and the released physical register can be mapped with a new logical register, so as to ensure that the new micro-operation can be performed.
There are two main ways to rename existing logical registers:
one is to explicitly release the mapped physical registers when mapping is not needed, please refer to fig. 1c, fig. 1c is a schematic diagram of another micro-operation sequence, as shown in fig. 1c, the mapping of the logical register temp0 and the physical registers is newly built in the micro-operations μop0 and μop1, and the mapping of the logical register temp1 and the physical registers is newly built, after the utilization of the logical register temp0 and the logical register temp1 is completed in the micro-operations μop2 and μop3, the physical registers mapped by temp0 and temp1 are released in the micro-operations μop4 and μop5 (i.e. the operation indicated by the operation code release is the mapping of the destination logical register and the physical register), so that the physical registers can map the logical registers of the subsequent micro-operations;
The other is that the mapped physical register is not explicitly released, and in combination with the method shown in fig. 1b, after the physical register is mapped for the destination logical registers temp0 and ymm2 in the micro-operation μop0 and the micro-operation μop1, the method starts to occupy the physical register; after the execution of the micro-operations μop0 and μop1 is finished, the mapped physical registers are not released until a new micro-operation with temp0 or ymm2 as a destination logical register is acquired, the old mapping is not released, and the physical registers are remapped for the destination logical register, and in extreme cases, if the micro-operation with temp0 or ymm2 as the destination logical register does not appear any more, the mapped physical registers are not released consistently, are occupied all the time, cannot be used for mapping the destination logical register of the new micro-operation, and a situation that the new micro-operation has no physical logical register available may appear.
Therefore, in the register renaming method in the prior art, the number of the physical registers that can be mapped without immediately releasing the mapped physical registers is excessively reduced, so that the execution of new micro-operations is affected, and the performance of the processor is also reduced.
Therefore, how to improve the utilization rate of the physical registers in the register renaming stage, and further improve the performance of the processor, is a technical problem that needs to be solved by those skilled in the art.
In order to solve the foregoing technical problems, embodiments of the present application provide a register renaming method, which improves the utilization rate of physical registers, so as to not only not prolong the execution duration of a micro-operation sequence, but also not excessively reduce the number of mappable physical registers, thereby improving the performance of a processor.
As an alternative implementation, please refer to fig. 2, fig. 2 shows a flowchart of a register renaming method provided in an embodiment of the present application. As shown in the drawings, the register renaming method provided in the embodiment of the present application includes:
in step S11, a first micro-operation and a second micro-operation are acquired, where the first micro-operation depends on the second micro-operation, and a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and a destination logical register of the second micro-operation is a second logical register.
The second logic register is a source logic register for providing source data in the first micro-operation, and the first logic register is a destination logic register for storing result data in the first micro-operation. The first logical register and the second logical register represent logical registers that are not both identical; it is noted that the first logical register and the second logical register may be different logical registers of the same kind, such as: the first logical register and the second logical register both belong to a temporary register, while the first logical register is a temporary register temp0 and the second logical register is another temporary register temp1. Of course, the first logic register and the second logic register may be different types of logic registers.
The first logic register and the second logic register may be any type of logic register, may be an architectural register such as an add register, or may be a temporary register, as long as they are required to be mapped to physical registers, so that the embodiments of the present application may be implemented.
The second micro-operation is a prior micro-operation with timing prior to the first micro-operation, wherein the second micro-operation takes the second logic register as a destination register, so that the mapped first physical register is allocated to the second logic register, and the first physical register mapped with the second logic register is not released before the first micro-operation is acquired. It is noted that the second micro-operation may be in the same sequence as the first micro-operation or may be in a different sequence than the first micro-operation, as long as the second micro-operation maps the second logical register and the first physical register before the first micro-operation and is not released at all times, which means that the first physical register is not released explicitly or implicitly as described above.
In some embodiments, there may be a plurality of source logical registers mapped with the physical registers in advance in the first micro-operation, and only one destination logical register, where only one source logical register can be selected from the plurality of source logical registers as the second logical register, the selection manner may not be limited.
The first physical register refers to a physical register mapped with a destination logical register of the second micro-operation (i.e., the second logical register), and the type of the physical register is not limited.
In order to multiplex the first physical register based on the dependency relationship of the first micro-operation and the second micro-operation in the register renaming stage, in the instruction decoding stage, the embodiment of the application may decode to obtain the first micro-operation and the second micro-operation, and as an optional implementation, fig. 9 is a flowchart of an instruction decoding method provided in the embodiment of the application.
As shown in fig. 9, the instruction decoding method provided in the embodiment of the present application includes:
in step S41, an instruction is acquired.
The instruction is an instruction in an instruction set that needs to be executed.
In step S42, the instruction is decoded to obtain a plurality of micro-operations, including a first micro-operation and a second micro-operation.
And decoding the instruction to finally obtain a micro-operation sequence which is formed by a plurality of micro-operations and is equivalent to the instruction, and executing the instruction by executing the micro-operation sequence.
In step S43, a dependency relationship of a first micro-operation on a second micro-operation is set, where a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is the second logical register, and in a register renaming stage, according to a mapping relationship between the second logical register and the first physical register, which are set for the second micro-operation, in a register renaming table, and in the register renaming table, a mapping relationship between the first logical register and the first physical register is set.
In this way, the micro-operation sequence with the second micro-operation and the first micro-operation depending on the second micro-operation can be obtained in the decoding stage, so that the technical scheme of multiplexing the physical register can be realized in the renaming stage, and the utilization rate of the physical register is improved.
In step S12, a register renaming table is queried as to whether a physical register mapped by the second logical register is recorded for the second micro-operation, where the register renaming table records a mapping relationship between the logical register and the physical register.
For ease of understanding, please refer to fig. 5b, fig. 5b is a schematic diagram of a register renaming table of the register renaming method according to the embodiments of the present application.
As shown in the figure, the register renaming table records a logical register and a current physical register, in some embodiments, a history physical register may be recorded, where the history physical register indicates that the recorded physical register has been used, and the history physical register will be released when a mapping relationship is configured for the logical register corresponding to the history physical register next time, so that the logical register only has a mapping relationship with the physical register recorded in the current physical register. For example, as shown in FIG. 5b, logical register temp0 releases physical register 1, which maps to physical register 100, while logical register temp1, logical register Ymm1_lo, and logical register Ymm1_hi have released the mapping relationship to physical registers, and none of them currently maps to physical registers.
In this way, by querying the register renaming table, it is determined whether the first logical register of the second micro-operation has a mapping relationship with the physical register according to whether the physical register is recorded in the current physical register corresponding to the destination logical register of the second micro-operation.
In step S13, it is determined whether the first physical register mapped by the second logical register is recorded for the second micro-operation in the register renaming table, if yes, step S14 is executed, otherwise step S15 is executed.
In step S14, a mapping relationship between the first logical register and the first physical register is set for the first micro-operation in the register renaming table.
It is noted that when mapping the first logical register and the first physical register, the mapping between the second logical register and the first physical register is not released, so that the first physical register is mapped with the first logical register and the second logical register at the same time.
For ease of understanding, please refer to fig. 5 a-5 e, fig. 5a is a schematic diagram of a micro-operation sequence processed by the register renaming method according to the embodiment of the present application; FIG. 5b is a state diagram of a register renaming table according to the register renaming method of the present embodiment; FIG. 5c is a diagram illustrating another state of a register renaming table according to the register renaming method of the embodiments of the present application; FIG. 5d is a diagram illustrating another state of a register renaming table according to the register renaming method of the embodiments of the present application; FIG. 5e is a diagram illustrating another state of a register renaming table according to the register renaming method of the embodiments of the present application.
As shown, micro-operation μop2 depends on micro-operation μop0 and μop3 depends on μop1, thus requiring register renaming for μop0 prior to register renaming for micro-operation μop2 and for μop1 prior to register renaming for μop3, with no order between μop0 and μop1, nor with μop2 and μop3.
Assuming that register renaming is preferentially performed on the micro-operation μop0 and the micro-operation μop1, and mapping is performed on each logic register in the μop0 and the μop1 with a physical register, then data in a register renaming table at this time is: the current physical register of the Temp0 map is physical register 100 and the current physical register of the Temp1 map is physical register 101.
Then register renaming may be performed on μop2 or μop3, and assuming that register renaming is performed on μop2 first, the micro-operation μop2 is the first micro-operation, and as shown in the figure, the destination logical register Ymm1_lo of μop2 is the first logical register, temp0 is the second logical register, and the physical register 100 is the first physical register, so Ymm1 _1_lo maps to the physical register 100. When register renaming μop3, ymm1_hi is mapped to physical register 101 in the same manner.
In the execution phase of the illustrated program, the micro-operation μop0 stores the processed data (assumed to be first data) into the physical register 100, the data (assumed to be second data) processed by the μop1 is stored into the physical register 101, then when the μop2 is executed, the first data stored in the physical register 100 is first read as source data, the μop2 is operated to obtain result data, the obtained result data is restored into the physical register 100, the μop3 obtains the second data through similar steps, and the obtained result data of the μop3 is stored into the physical register 101 after the processing.
Thus, for the micro-operation μop2 and the micro-operation μop3, after judging that they belong to the first micro-operation, the physical registers to be mapped are not selected from the physical registers that have been released, but the physical registers that have been mapped are multiplexed, thereby reducing the physical registers that need to be used.
In step S15, the process ends.
Of course, the end does not refer to the renaming of the sequence of micro-operations or the end of execution, but rather to the mapping of the first micro-operation and the first physical register.
Therefore, according to the register renaming method provided by the embodiment of the application, after the first micro-operation is acquired, the physical register which is mapped is not selected from the released physical registers, but the first physical register which is mapped in the second micro-operation is selected, so that multiplexing of the mapped first physical registers is realized, the number of physical registers which are required to be used is reduced, and the utilization rate of the physical registers is improved; meanwhile, it is worth noting that the application is not limited to selecting the mapping from the physical registers without mapping any more by multiplexing the physical registers, so that special release micro-operation is not required to be set, and the execution time of a micro-operation sequence is reduced; therefore, by multiplexing the physical registers, the execution duration of the micro-operation sequence can be not prolonged, and the number of the mappable physical registers can not be excessively reduced, so that the performance of the processor is improved.
In one embodiment, after the mapping between the second logical register and the first physical register is established by the first micro-operation and before the mapping is released, there may be a plurality of micro-operations using the second logical register as the source logical register, and when the first micro-operation depends on the micro-operation, the micro-operation is called a third micro-operation, so as not to cause a data processing error, please refer to fig. 3, fig. 3 is another flowchart of a register renaming method provided in the embodiment of the present application, and as shown in the drawing, the register renaming method provided in the embodiment of the present application further includes:
in step S21, at least one third micro-operation is acquired, the third micro-operation being dependent on the second micro-operation, the first micro-operation being dependent on the at least one third micro-operation.
For an understanding of the multiple micro-operations including the first logical register in the source logical register, please refer to fig. 4, fig. 4 is a schematic diagram of the micro-operations provided in the embodiment of the present application. As shown in fig. 4, the logical register temp0 is a first logical register and is mapped with a first physical register, and μops 1 and μops 2 each include temp0 (first logical register) as a source logical register.
With continued reference to FIG. 4, the μop2 also has a logical register xmm4 as the source logical register, and logical register xmm4 is the destination logical register for μop1, so μop2 also depends on μop1. Thus, although μop1 and μop2 are both dependent on μop0, μop1 is the third micro-operation since μop2 is dependent on μop1.
In step S22, at least one second physical register, different from the first physical register, is mapped in the register renaming table for the destination logical register of the at least one third micro-operation.
It is noted that when there are multiple third micro-operations, each of the third micro-operations may be mapped to a respective second physical register, the "at least one second physical register" does not mean that each of the third micro-operations is mapped to the same physical register (e.g., is mapped to physical register 100), but that each of the third micro-operations needs to be mapped to a physical register other than the first physical register, thereby preventing data processing errors.
To facilitate understanding of what is wrong in data processing, please continue to refer to fig. 4, assuming that the micro-operations shown in fig. 4 are all add operations, and that the value in the logic register source1 is 1, the value in the source2 is 2, the value in xmm3 is 3, and the logic register temp0 and the physical register 100 are already mapped, the logic register xmm4 and the physical register 200, the logic register xmm6 and the physical register 300 are both absent, and therefore, the micro-operations μop1 and μop2 are not considered ready for execution, and the μop0 can be executed because all source logic registers (the logic register source1 and the logic register source 2) are all ready, and the result data 3 is obtained by adding, and the value is stored in the physical register 100 mapped by the logic register temp0, and the micro-operations μop2 are still not ready for execution because of the absence of the value of the logic register xmm4, and the micro-operations μop1 and μop2 are not considered ready for execution, and the result data 9 is also obtained by the micro-operations 9, and the existing mode that the micro-operations are not well-executed by the logic register 3 is easy to obtain; now, suppose that xmm4 is changed to map the physical register 100 as well, after the execution of the micro-operation μop0, the result data 3 is stored in the physical register 100, and after the execution of the micro-operation μop1, the result data 6 is stored in the physical register 100, so that when the micro-operation μop2 is executed, since the physical register mapped by the logical register temp0 is also the physical register 100 and the value stored in the physical register has been changed to 6, the result data obtained by the execution of the micro-operation μop2 is 12, the error result is obtained, and the data processing error is obtained.
Therefore, by mapping the destination logical register of the third micro-operation with the second physical register of the non-first physical register, it is possible to avoid a data processing error while improving the use efficiency of the physical registers.
It should be noted that, in the source logical register, there may be a plurality of micro-operations including the first logical register, and the micro-operations are not dependent on the first micro-operation and are not the third micro-operation, so that the execution sequence of the micro-operations and the first micro-operation is not determined, and in order to prevent a data processing error, in an embodiment, please refer to fig. 6, fig. 6 is a flowchart of a register renaming method according to an embodiment of the present application.
As shown in fig. 6, the register renaming method provided in the embodiment of the present application includes:
in step S31, a first micro-operation and a second micro-operation are acquired, where the first micro-operation depends on the second micro-operation, and a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and a destination logical register of the second micro-operation is a second logical register.
For the specific process of step S31, please refer to the related description of step S11.
In step S32, it is determined whether the second logical register of the second micro-operation belongs to a type logical register that cannot be reused, if yes, step S36 is executed, and if no, step S33 is executed.
The class-not-to-multiplex logic register is a class of the logic register division in the embodiment of the present application, and by dividing the logic register into the class-not-to-multiplex and the class-capable multiplexing in advance, in the instruction decoding stage of decoding the instruction into the micro instruction sequence, according to the actual situation of the micro instruction sequence, it is determined whether the above-mentioned process for improving the utilization rate of the physical register needs to be performed on the first micro operation, for example: when the destination logical register is a plurality of micro-operations of the first logical register and has no dependency relationship with each other, the processing for improving the utilization rate of the physical register is easy to cause data processing errors, so that the processing for improving the utilization rate of the physical register is judged according to whether the micro-operation logical register belongs to the non-multiplexing category in the renaming stage by setting the related micro-operation logical register to the non-multiplexing category.
Specifically, in an alternative embodiment of setting the logic register as a logic register of a type that cannot be reused in the instruction decoding stage, fig. 11 may be taken, and fig. 11 is another flowchart of the instruction decoding method provided in the embodiment of the present application.
As shown in the figure, the instruction decoding method provided in the embodiment of the present application includes:
in step S61, an instruction is acquired.
In step S62, decoding the instruction to obtain a plurality of micro-operations; the plurality of micro-operations includes a first micro-operation and a second micro-operation.
In step S63, a dependency relationship of a first micro-operation on a second micro-operation is set, where a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is the second logical register, and in a register renaming stage, according to a mapping relationship between the second logical register and the first physical register, which are set for the second micro-operation, in a register renaming table, and in the register renaming table, a mapping relationship between the first logical register and the first physical register is set.
For details of steps S61-S63, please refer to the description of steps S41-S43.
In step S64, the second logical register is set to a preset non-multiplexing type logical register, so that in a register renaming stage, a step of executing whether the physical register mapped by the second logical register is recorded for the second micro operation by the query register renaming table is not triggered.
In this way, when the instruction is decoded in the instruction decoding stage, the second logic register is set as the type logic register which cannot be multiplexed, so that simple and complex situations can be distinguished, and whether to perform the above-mentioned processing for improving the efficiency of the physical register on the micro-operation can be selected according to the actual situation of the micro-instruction sequence.
Of course, in other embodiments, the above-mentioned process of improving the utilization of the physical register may be performed by adding a dependency to the micro-operation that is not dependent in the instruction decoding stage.
In step S33, a register renaming table is queried as to whether a physical register mapped by the second logical register is recorded for the second micro-operation, and the register renaming table records a mapping relationship between the logical register and the physical register for the micro-operation.
When the second micro-operation uses the second logic register as the destination logic register, in some embodiments, there may be multiple micro-operations using the second logic register as the source logic register, each micro-operation has a different destination logic register, and the multiple micro-operations may have no dependency relationship with each other, so that the execution sequence is not determined, and the last micro-operation executed in the actual execution cannot be determined, and the multiplexing of physical registers may cause a data processing error.
In order to avoid data processing errors, the first micro-operation may be obtained by presetting the dependency relationship between the micro-operations that are dependent on the second micro-operation, please refer to fig. 10, fig. 10 is a flowchart of an instruction decoding method according to an embodiment of the present application.
As shown in fig. 10, the embodiment of the present application further provides an instruction decoding method, where the execution decoding method is applicable to the register renaming method, and includes:
in step S51, an instruction is acquired.
For details of step S51, please refer to the description related to step S41.
In step S52, the instruction is decoded to obtain a plurality of micro-operations including a first micro-operation, a second micro-operation, and at least one third micro-operation.
Of course, the second micro-operation uses the second logic register as a destination logic register, the first micro-operation and the third micro-operation both use the second logic register as a source logic register, and no dependency exists between the second micro-operation and the third micro-operation.
In step S53, a dependency relationship between the first micro-operation, the second micro-operation and the at least one third micro-operation is set for mapping at least one second physical register in the register renaming table for a destination logical register of the at least one third micro-operation, the second physical register being different from the first physical register.
Specifically, the destination logical register of each third micro-operation may be added in the source logical register of the first micro-operation, so that the first micro-operation depends on the second micro-operation and also depends on the third micro-operation, thereby determining that the first micro-operation is executed after all the third micro-operations are executed, and avoiding that multiplexing the first micro-operation into the first physical register results in a calculation error.
In this way, the micro-operation sequence obtained by instruction decoding can avoid triggering multiplexing of the first physical register when the first micro-operation depends on the second micro-operation in the renaming stage, so that the first physical register is prevented from being multiplexed to cause data processing errors when the micro-operation sequence comprises a plurality of micro-operations which depend on the second micro-operation and no dependency exists among the micro-operations.
In step S34, it is determined whether the first physical register mapped by the second logical register is recorded for the second micro-operation in the register renaming table, if yes, step S35 is executed, otherwise step S36 is executed.
In step S35, a mapping relationship between the first logical register and the first physical register is set for the first micro-operation in the register renaming table.
Step S36, ends.
For the specific process of step S34 to step S36, refer to the description related to step S13 and step S15.
In this way, by setting the logical register of the type that cannot be reused, when it is determined that the logical register belongs to the type that cannot be reused, no attempt is made to multiplex the physical register with respect to the logical register, so that mapping between the first logical register and the first physical register in a complex situation, particularly in a situation that there is no dependency relationship between them, is avoided, and data processing errors are caused.
In order to have a plurality of micro-operations dependent on the second micro-operation, and without referring to fig. 7 among the micro-operations, fig. 7 is a flowchart of a register renaming method according to an embodiment of the present application;
as shown, to perform the multiplexing of the first micro-operation to the physical register under the premise of preventing the data processing error, in a specific embodiment, the method may include:
in step S71, a copy micro-operation is obtained, the copy micro-operation being dependent on a second micro-operation, a source logical register of the copy micro-operation comprising the second logical register, a destination logical register of the copy micro-operation comprising a third logical register, the copy micro-operation being adapted to copy a value in the second logical register into the third logical register.
It is readily understood that the copy micro-operation is of a type suitable for retaining data in a source logical register while moving the data in the source logical register to data in a destination logical register, and that the first micro-operation described herein does not include a copy micro-operation.
In step S72, a third physical register is mapped for the third logical register of the copy micro-operation in the register renaming table.
The third physical register is a physical register that is different from the first physical register of the first micro-operation.
In this way, the data is stored in two different physical registers, and by setting the copy micro-operation, the value in the first physical register of the second micro-operation can be copied into the third physical register, so that after the first micro-operation maps the first physical register and changes the value in the first physical register, the value before the change is stored in the third physical register, and the data is not lost, and when the data needs to be used, the data can be obtained from the third physical register (the third logical register of the copy micro-operation).
When there are multiple micro-operations that depend on the second micro-operation and have no dependency relationship with each other, the dependency relationship of the micro-operations may be further changed in the instruction decoding stage, please continue to refer to fig. 7, in step S73, a fourth micro-operation is obtained, where the fourth micro-operation depends on the copy micro-operation, the source logic register of the fourth micro-operation includes the third logic register, and the destination logic register includes the fourth logic register.
The fourth micro-operation may be a micro-operation that is originally dependent on the second micro-operation and that is independent of the first micro-operation. And changing the dependency relationship of the fourth micro-operation, in particular changing the destination logic register of the fourth micro-operation from the second logic register to the third logic register. In step S74, the third physical register is mapped for the fourth logical register of the copy micro-operation in the register renaming table.
In this way, when the first micro-operation is executed prior to and changes the value in the first physical register, the fourth micro-operation does not thus acquire the changed error value, but acquires the correct value through the third physical register, so that an error in data processing can be avoided while the physical registers are multiplexed.
And the data in the third logic register is consistent with the data in the second logic register, and the first logic register included in the source logic register of the first micro-operation is replaced by the third logic register, so that the first micro-operation is converted into the second micro-operation, and the second micro-operation is different from the micro-operation on which the first micro-operation depends, so that the problem of data processing errors during execution is solved.
In order to enable the above-mentioned processing of copy micro-operations in the renaming stage, in the instruction decoding stage, in a specific implementation manner, the embodiment of the present application further provides an instruction decoding method, including:
setting the copy micro-operation depends on the second micro-operation, wherein a source logic register of the copy micro-operation is the second logic register, a destination logic register is the third logic register, and the copy micro-operation is suitable for taking the first logic register as the source logic register, taking the third logic register as the destination logic register and copying the value in the first logic register to the third logic register in a renaming stage.
Therefore, the second logic register is taken as a source logic register, the third logic register is taken as a target logic register in the renaming stage by adding the copy micro-operation in the instruction decoding stage, and the numerical value in the second logic register is copied to the third logic register, so that part of micro-operation can be changed to enable the third logic register to be taken as the target logic register, and the utilization rate of the physical register is improved while the correct data processing is ensured.
After mapping the second logical register and the first physical register of the first micro-operation, the first physical register is mapped with the first logical register and the second logical register at the same time, and when there is a micro-operation dependent on the first micro-operation in the micro-operation program sequence, an error in data processing may occur, and referring to fig. 8, fig. 8 is a schematic diagram of a micro-operation sequence of the register renaming method according to the embodiment of the present application.
As shown, μop2 depends on μop1, μop1 depends on μop0, μop1 is a first micro-operation, where the first logical register is temp0 and the second logical register is ymm3, where temp0 is configured in μop0 to map with the first physical register, and therefore the ymm3 also maps with the first physical register; similarly, μop2 is also the first micro-operation, where the first logical register is ymm3 and the second logical register is ymm5, so that ymm5 also maps with the first physical register.
In the execution stage, μop0 is executed first, the processed data is stored in the first physical register, and then the information that the first physical register has been executed is acquired by the execution circuit, but since ymm3 is mapped to the first physical register, the control circuit may consider that ymm3 mapped to the first physical register has been executed, thereby considering that μop1 has been executed, and executing micro-operation μop2, resulting in an error in data processing.
In order to avoid the occurrence of the above-mentioned data processing error, in a register renaming stage, in an embodiment, the register renaming method provided in the embodiment of the present application includes:
acquiring a broadcast carrying a first physical register and identification data, wherein the identification data is arranged in the register renaming table when a mapping relation between the second logic register and the first physical register is set in the register renaming table for the second micro-operation, so as to indicate that the logic register mapped to the first physical register is the second logic register;
and inquiring a register renaming table according to the first physical register and the identification data carried by the broadcast so as to determine that the micro-operation corresponding to the second logic register indicated by the identification data is executed and is in a ready state.
In this way, by setting the identification data, whether the physical register is executed by the first micro-operation can be distinguished according to the identification data, so that the micro-operation which depends on the first micro-operation can be prevented from being executed in advance, and the error of data processing can be prevented.
From the above analysis, it is clear that there may be many cases when multiplexing the first logical register, and thus implementation is complicated, and thus, in a specific embodiment, the first logical register includes a temporary register.
As known from the above, the logic registers include temporary registers and architecture registers, wherein the temporary registers have characteristics different from the architecture registers, and the applicant has found that the technical problem can be better solved by combining the characteristics with the register renaming method provided in the present application.
Firstly, in a micro-operation program sequence, after a temporary register is used as a target logic register to map a physical register, only one micro-operation usually takes the temporary register as a source logic register, and the mapping between the temporary register and the physical register is not reused, so that the multiplexing of a first physical register can be directly carried out with high probability, and for the case of few reuse, the multiplexing of the complex cases can be avoided by setting the temporary register as a type logic register which cannot be multiplexed in an instruction decoding stage; meanwhile, the performance of the processor can be obviously improved because multiplexing under complex conditions is not needed.
Of course, there are also special architecture registers in the architecture registers that the mapping relationship with the physical registers would be used only once, and in some embodiments, the first logical registers may also include the special architecture registers.
It should be noted that, when only the temporary register is used as the first logic register, the first micro-operation identifier may include a temporary register identifier bit, and by adding the temporary register identifier bit in the register renaming table in advance, the second logic register is identified as belonging to the temporary register, so as to determine whether the execution of the first micro-operation is completed. Thus, the difficulty in setting the identification data can be reduced.
In order to solve the foregoing problems, the embodiment of the present application further provides an instruction decoding device, please refer to fig. 12, and fig. 12 is an instruction decoding device provided in the embodiment of the present application.
As shown in the drawings, the instruction decoding device provided in the embodiments of the present application includes:
an instruction acquisition unit 1 adapted to acquire an instruction;
a decoding unit 2 adapted to decode the instruction to obtain a plurality of micro-operations; the plurality of micro-operations includes a first micro-operation and a second micro-operation;
the dependency setting unit 3 is adapted to set a dependency relationship of a first micro-operation depending on a second micro-operation, where a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is the second logical register, and is configured to set a mapping relationship between the first physical register and the first logical register according to a mapping relationship between the second logical register set for the second micro-operation in the register renaming table and the first physical register in the register renaming table.
In a specific embodiment, the plurality of micro-operations further includes at least one third micro-operation;
the instruction decoding device further includes:
a third micro-operation dependency setting unit adapted to set a dependency relationship between the first micro-operation, the second micro-operation and the at least one third micro-operation for mapping at least one second physical register in the register renaming table for a destination logical register of the at least one third micro-operation, the second physical register being different from the first physical register.
In a specific embodiment, the plurality of micro-operations further includes a copy micro-operation;
the instruction decoding device further includes:
the copy micro-operation dependence setting unit is adapted to set the copy micro-operation to depend on the second micro-operation, wherein a source logic register of the copy micro-operation is the second logic register, a destination logic register is the third logic register, the copy micro-operation is adapted to take the first logic register as the source logic register, take the third logic register as the destination logic register in a renaming stage, and copy the value in the first logic register to the third logic register.
In one embodiment, the instruction decoding device further includes:
and the non-multiplexing type logic register setting unit is suitable for setting the second logic register to be a preset non-multiplexing type logic register, and is used for not triggering and executing the step of searching whether the physical register mapped by the second logic register is recorded by the register renaming table aiming at the second micro-operation in the register renaming stage.
Therefore, the instruction decoding device provided by the embodiment of the application can acquire the micro-operation sequence with the second micro-operation and the first micro-operation depending on the second micro-operation in the decoding stage, so that the technical scheme of multiplexing the physical register can be realized in the renaming stage, and the utilization rate of the physical register is improved.
The embodiment of the application also provides a processor, which comprises a register renaming unit and a decoding unit; the register renaming unit being configured to perform a register renaming method as claimed in any preceding claim and the decode unit being configured to perform an instruction decode method as claimed in any preceding claim.
The embodiment of the application also provides a chip, which comprises the processor.
The embodiment of the application also provides electronic equipment, which comprises the chip.
Therefore, after the processor, the chip and the electronic device provided by the embodiment of the application acquire the first micro-operation, the physical register to be mapped is not selected from the released physical registers, but the first physical register to be mapped in the second micro-operation is selected, so that multiplexing of the first physical register to be mapped is realized, the number of physical registers to be used is reduced, and the utilization rate of the physical registers is improved; meanwhile, it is worth noting that the application is not limited to selecting the mapping from the physical registers without mapping any more by multiplexing the physical registers, so that special release micro-operation is not required to be set, and the execution time of a micro-operation sequence is reduced; therefore, by multiplexing the physical registers, the execution duration of the micro-operation sequence can be not prolonged, and the number of the mappable physical registers can not be excessively reduced, so that the performance of the processor is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing describes a number of embodiments provided by embodiments of the present application, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible, all of which may be considered embodiments disclosed and disclosed by embodiments of the present application.
Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention shall be defined by the appended claims.
Claims (16)
1. A method of register renaming, comprising:
acquiring a first micro-operation and a second micro-operation, wherein the first micro-operation depends on the second micro-operation, a destination logic register of the first micro-operation is a first logic register, a source logic register of the first micro-operation is a second logic register, and a destination logic register of the second micro-operation is a second logic register;
querying a register renaming table for whether a physical register mapped by the second logical register is recorded for the second micro-operation;
And if the register renaming table is queried to record a first physical register mapped by the second logic register aiming at the second micro-operation, setting the mapping relation between the first logic register and the first physical register for the first micro-operation in the register renaming table.
2. The register renaming method of claim 1, further comprising: obtaining at least one third micro-operation, the third micro-operation being dependent on the second micro-operation, the first micro-operation being dependent on the at least one third micro-operation;
at least one second physical register is mapped in the register renaming table for a destination logical register of the at least one third micro-operation, the second physical register being different from the first physical register.
3. The register renaming method of claim 1, further comprising, before the query register renaming table records the second logical register mapped physical register for the second micro-operation:
and judging whether the second logic register of the second micro-operation belongs to a non-multiplexing type logic register, and triggering and executing the step of inquiring whether a register renaming table records a physical register mapped by the second logic register for the second micro-operation when the second logic register does not belong to the non-multiplexing type logic register.
4. The register renaming method of claim 1, wherein the first micro-operation is not a copy micro-operation; the method further comprises the steps of:
obtaining a copy micro-operation, the copy micro-operation being dependent on a second micro-operation, a source logical register of the copy micro-operation comprising the second logical register, a destination logical register of the copy micro-operation comprising a third logical register, the copy micro-operation being adapted to copy values in the second logical register into the third logical register;
in the register renaming table, a third physical register is mapped for the third logical register of the copy micro-operation.
5. The register renaming method of claim 4, further comprising:
acquiring a fourth micro-operation, wherein the fourth micro-operation depends on the copy micro-operation, a source logic register of the fourth micro-operation comprises the third logic register, and a destination logic register comprises a fourth logic register;
the third physical register is mapped for the fourth logical register of the copy micro-operation in the register renaming table.
6. The register renaming method of claim 1, further comprising:
Acquiring a broadcast carrying a first physical register and identification data, wherein the identification data is arranged in the register renaming table when a mapping relation between the second logic register and the first physical register is set in the register renaming table for the second micro-operation, so as to indicate that the logic register mapped to the first physical register is the second logic register;
and inquiring a register renaming table according to the first physical register and the identification data carried by the broadcast so as to determine that the micro-operation corresponding to the second logic register indicated by the identification data is executed and is in a ready state.
7. The register renaming method of claims 1-6, wherein the second logical register comprises a temporary register.
8. The register renaming method of claim 7, wherein the method further comprises:
when the register renaming table records the mapping relation between the second logic register and the first physical register, a temporary register identification bit is added in the register renaming table, and the temporary register identification bit is suitable for identifying that the second logic register belongs to a temporary register.
9. A method of instruction decoding, comprising:
acquiring an instruction;
decoding the instruction to obtain a plurality of micro-operations; the plurality of micro-operations includes a first micro-operation and a second micro-operation;
setting a dependence relationship of a first micro-operation on a second micro-operation, wherein a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is a second logical register, and is used for setting a mapping relationship between the first logical register and the first physical register according to a mapping relationship between the second logical register and the first physical register, which are set for the second micro-operation, in a register renaming table in a register renaming stage.
10. The instruction decode method according to claim 9, wherein said plurality of micro-operations further includes at least one third micro-operation;
the method further comprises the steps of:
and setting the dependency relationship among the first micro-operation, the second micro-operation and the at least one third micro-operation, and mapping at least one second physical register in the register renaming table for a destination logical register of the at least one third micro-operation, wherein the second physical register is different from the first physical register.
11. The instruction decoding method of claim 9, wherein the plurality of micro-operations further comprises a copy micro-operation;
the method further comprises the steps of:
setting the copy micro-operation depends on the second micro-operation, wherein a source logic register of the copy micro-operation is the second logic register, a destination logic register is the third logic register, and the copy micro-operation is suitable for taking the first logic register as the source logic register, taking the third logic register as the destination logic register and copying the value in the first logic register to the third logic register in a renaming stage.
12. The instruction decoding method of claim 9, further comprising:
and setting the second logic register as a preset non-multiplexing type logic register, wherein the preset non-multiplexing type logic register is used for not triggering and executing the step of searching whether the physical register mapped by the second logic register is recorded for the second micro operation by the register renaming table in a register renaming stage.
13. An instruction decoding device, comprising:
an instruction acquisition unit adapted to acquire an instruction;
The decoding unit is suitable for decoding the instruction to obtain a plurality of micro-operations; the plurality of micro-operations includes a first micro-operation and a second micro-operation;
the dependency setting unit is adapted to set a dependency relationship of a first micro-operation depending on a second micro-operation, wherein a destination logical register of the first micro-operation is a first logical register, a source logical register of the first micro-operation is a second logical register, and the destination logical register of the second micro-operation is the second logical register, and is configured to set a mapping relationship between the second logical register set for the second micro-operation and the first physical register in the register renaming table according to the mapping relationship between the second logical register set for the second micro-operation and the first physical register in the register renaming table.
14. A processor, comprising a register renaming unit, and a decoding unit; the register renaming unit being configured to perform the register renaming method according to claims 1-8 and the decode unit being configured to perform the instruction decode method according to claims 9-12.
15. A chip comprising the processor of claim 14.
16. An electronic device comprising the chip of claim 15.
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| CN116700792B (en) * | 2023-06-09 | 2024-03-08 | 合芯科技有限公司 | Mapping method, structure, storage medium and chip of instruction stream register |
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